fsl_esdhc_imx.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
  4. * Copyright 2019 NXP Semiconductors
  5. * Andy Fleming
  6. * Yangbo Lu <yangbo.lu@nxp.com>
  7. *
  8. * Based vaguely on the pxa mmc code:
  9. * (C) Copyright 2003
  10. * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  11. */
  12. #include <config.h>
  13. #include <common.h>
  14. #include <command.h>
  15. #include <clk.h>
  16. #include <cpu_func.h>
  17. #include <errno.h>
  18. #include <hwconfig.h>
  19. #include <log.h>
  20. #include <mmc.h>
  21. #include <part.h>
  22. #include <asm/cache.h>
  23. #include <dm/device_compat.h>
  24. #include <linux/bitops.h>
  25. #include <linux/delay.h>
  26. #include <linux/err.h>
  27. #include <power/regulator.h>
  28. #include <malloc.h>
  29. #include <fsl_esdhc_imx.h>
  30. #include <fdt_support.h>
  31. #include <asm/io.h>
  32. #include <dm.h>
  33. #include <asm-generic/gpio.h>
  34. #include <dm/pinctrl.h>
  35. #if !CONFIG_IS_ENABLED(BLK)
  36. #include "mmc_private.h"
  37. #endif
  38. DECLARE_GLOBAL_DATA_PTR;
  39. #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
  40. IRQSTATEN_CINT | \
  41. IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
  42. IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
  43. IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
  44. IRQSTATEN_DINT)
  45. #define MAX_TUNING_LOOP 40
  46. #define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
  47. struct fsl_esdhc {
  48. uint dsaddr; /* SDMA system address register */
  49. uint blkattr; /* Block attributes register */
  50. uint cmdarg; /* Command argument register */
  51. uint xfertyp; /* Transfer type register */
  52. uint cmdrsp0; /* Command response 0 register */
  53. uint cmdrsp1; /* Command response 1 register */
  54. uint cmdrsp2; /* Command response 2 register */
  55. uint cmdrsp3; /* Command response 3 register */
  56. uint datport; /* Buffer data port register */
  57. uint prsstat; /* Present state register */
  58. uint proctl; /* Protocol control register */
  59. uint sysctl; /* System Control Register */
  60. uint irqstat; /* Interrupt status register */
  61. uint irqstaten; /* Interrupt status enable register */
  62. uint irqsigen; /* Interrupt signal enable register */
  63. uint autoc12err; /* Auto CMD error status register */
  64. uint hostcapblt; /* Host controller capabilities register */
  65. uint wml; /* Watermark level register */
  66. uint mixctrl; /* For USDHC */
  67. char reserved1[4]; /* reserved */
  68. uint fevt; /* Force event register */
  69. uint admaes; /* ADMA error status register */
  70. uint adsaddr; /* ADMA system address register */
  71. char reserved2[4];
  72. uint dllctrl;
  73. uint dllstat;
  74. uint clktunectrlstatus;
  75. char reserved3[4];
  76. uint strobe_dllctrl;
  77. uint strobe_dllstat;
  78. char reserved4[72];
  79. uint vendorspec;
  80. uint mmcboot;
  81. uint vendorspec2;
  82. uint tuning_ctrl; /* on i.MX6/7/8/RT */
  83. char reserved5[44];
  84. uint hostver; /* Host controller version register */
  85. char reserved6[4]; /* reserved */
  86. uint dmaerraddr; /* DMA error address register */
  87. char reserved7[4]; /* reserved */
  88. uint dmaerrattr; /* DMA error attribute register */
  89. char reserved8[4]; /* reserved */
  90. uint hostcapblt2; /* Host controller capabilities register 2 */
  91. char reserved9[8]; /* reserved */
  92. uint tcr; /* Tuning control register */
  93. char reserved10[28]; /* reserved */
  94. uint sddirctl; /* SD direction control register */
  95. char reserved11[712];/* reserved */
  96. uint scr; /* eSDHC control register */
  97. };
  98. struct fsl_esdhc_plat {
  99. struct mmc_config cfg;
  100. struct mmc mmc;
  101. };
  102. struct esdhc_soc_data {
  103. u32 flags;
  104. };
  105. /**
  106. * struct fsl_esdhc_priv
  107. *
  108. * @esdhc_regs: registers of the sdhc controller
  109. * @sdhc_clk: Current clk of the sdhc controller
  110. * @bus_width: bus width, 1bit, 4bit or 8bit
  111. * @cfg: mmc config
  112. * @mmc: mmc
  113. * Following is used when Driver Model is enabled for MMC
  114. * @dev: pointer for the device
  115. * @non_removable: 0: removable; 1: non-removable
  116. * @broken_cd: 0: use GPIO for card detect; 1: Do not use GPIO for card detect
  117. * @wp_enable: 1: enable checking wp; 0: no check
  118. * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
  119. * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
  120. * @caps: controller capabilities
  121. * @tuning_step: tuning step setting in tuning_ctrl register
  122. * @start_tuning_tap: the start point for tuning in tuning_ctrl register
  123. * @strobe_dll_delay_target: settings in strobe_dllctrl
  124. * @signal_voltage: indicating the current voltage
  125. * @cd_gpio: gpio for card detection
  126. * @wp_gpio: gpio for write protection
  127. */
  128. struct fsl_esdhc_priv {
  129. struct fsl_esdhc *esdhc_regs;
  130. unsigned int sdhc_clk;
  131. struct clk per_clk;
  132. unsigned int clock;
  133. unsigned int mode;
  134. unsigned int bus_width;
  135. #if !CONFIG_IS_ENABLED(BLK)
  136. struct mmc *mmc;
  137. #endif
  138. struct udevice *dev;
  139. int non_removable;
  140. int broken_cd;
  141. int wp_enable;
  142. int vs18_enable;
  143. u32 flags;
  144. u32 caps;
  145. u32 tuning_step;
  146. u32 tuning_start_tap;
  147. u32 strobe_dll_delay_target;
  148. u32 signal_voltage;
  149. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  150. struct udevice *vqmmc_dev;
  151. struct udevice *vmmc_dev;
  152. #endif
  153. #if CONFIG_IS_ENABLED(DM_GPIO)
  154. struct gpio_desc cd_gpio;
  155. struct gpio_desc wp_gpio;
  156. #endif
  157. };
  158. /* Return the XFERTYP flags for a given command and data packet */
  159. static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
  160. {
  161. uint xfertyp = 0;
  162. if (data) {
  163. xfertyp |= XFERTYP_DPSEL;
  164. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  165. xfertyp |= XFERTYP_DMAEN;
  166. #endif
  167. if (data->blocks > 1) {
  168. xfertyp |= XFERTYP_MSBSEL;
  169. xfertyp |= XFERTYP_BCEN;
  170. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  171. xfertyp |= XFERTYP_AC12EN;
  172. #endif
  173. }
  174. if (data->flags & MMC_DATA_READ)
  175. xfertyp |= XFERTYP_DTDSEL;
  176. }
  177. if (cmd->resp_type & MMC_RSP_CRC)
  178. xfertyp |= XFERTYP_CCCEN;
  179. if (cmd->resp_type & MMC_RSP_OPCODE)
  180. xfertyp |= XFERTYP_CICEN;
  181. if (cmd->resp_type & MMC_RSP_136)
  182. xfertyp |= XFERTYP_RSPTYP_136;
  183. else if (cmd->resp_type & MMC_RSP_BUSY)
  184. xfertyp |= XFERTYP_RSPTYP_48_BUSY;
  185. else if (cmd->resp_type & MMC_RSP_PRESENT)
  186. xfertyp |= XFERTYP_RSPTYP_48;
  187. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  188. xfertyp |= XFERTYP_CMDTYP_ABORT;
  189. return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
  190. }
  191. #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
  192. /*
  193. * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
  194. */
  195. static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
  196. struct mmc_data *data)
  197. {
  198. struct fsl_esdhc *regs = priv->esdhc_regs;
  199. uint blocks;
  200. char *buffer;
  201. uint databuf;
  202. uint size;
  203. uint irqstat;
  204. ulong start;
  205. if (data->flags & MMC_DATA_READ) {
  206. blocks = data->blocks;
  207. buffer = data->dest;
  208. while (blocks) {
  209. start = get_timer(0);
  210. size = data->blocksize;
  211. irqstat = esdhc_read32(&regs->irqstat);
  212. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
  213. if (get_timer(start) > PIO_TIMEOUT) {
  214. printf("\nData Read Failed in PIO Mode.");
  215. return;
  216. }
  217. }
  218. while (size && (!(irqstat & IRQSTAT_TC))) {
  219. udelay(100); /* Wait before last byte transfer complete */
  220. irqstat = esdhc_read32(&regs->irqstat);
  221. databuf = in_le32(&regs->datport);
  222. *((uint *)buffer) = databuf;
  223. buffer += 4;
  224. size -= 4;
  225. }
  226. blocks--;
  227. }
  228. } else {
  229. blocks = data->blocks;
  230. buffer = (char *)data->src;
  231. while (blocks) {
  232. start = get_timer(0);
  233. size = data->blocksize;
  234. irqstat = esdhc_read32(&regs->irqstat);
  235. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
  236. if (get_timer(start) > PIO_TIMEOUT) {
  237. printf("\nData Write Failed in PIO Mode.");
  238. return;
  239. }
  240. }
  241. while (size && (!(irqstat & IRQSTAT_TC))) {
  242. udelay(100); /* Wait before last byte transfer complete */
  243. databuf = *((uint *)buffer);
  244. buffer += 4;
  245. size -= 4;
  246. irqstat = esdhc_read32(&regs->irqstat);
  247. out_le32(&regs->datport, databuf);
  248. }
  249. blocks--;
  250. }
  251. }
  252. }
  253. #endif
  254. static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  255. struct mmc_data *data)
  256. {
  257. int timeout;
  258. struct fsl_esdhc *regs = priv->esdhc_regs;
  259. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  260. dma_addr_t addr;
  261. #endif
  262. uint wml_value;
  263. wml_value = data->blocksize/4;
  264. if (data->flags & MMC_DATA_READ) {
  265. if (wml_value > WML_RD_WML_MAX)
  266. wml_value = WML_RD_WML_MAX_VAL;
  267. esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
  268. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  269. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  270. addr = virt_to_phys((void *)(data->dest));
  271. if (upper_32_bits(addr))
  272. printf("Error found for upper 32 bits\n");
  273. else
  274. esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
  275. #else
  276. esdhc_write32(&regs->dsaddr, (u32)data->dest);
  277. #endif
  278. #endif
  279. } else {
  280. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  281. flush_dcache_range((ulong)data->src,
  282. (ulong)data->src+data->blocks
  283. *data->blocksize);
  284. #endif
  285. if (wml_value > WML_WR_WML_MAX)
  286. wml_value = WML_WR_WML_MAX_VAL;
  287. if (priv->wp_enable) {
  288. if ((esdhc_read32(&regs->prsstat) &
  289. PRSSTAT_WPSPL) == 0) {
  290. printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
  291. return -ETIMEDOUT;
  292. }
  293. } else {
  294. #if CONFIG_IS_ENABLED(DM_GPIO)
  295. if (dm_gpio_is_valid(&priv->wp_gpio) &&
  296. dm_gpio_get_value(&priv->wp_gpio)) {
  297. printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
  298. return -ETIMEDOUT;
  299. }
  300. #endif
  301. }
  302. esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
  303. wml_value << 16);
  304. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  305. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  306. addr = virt_to_phys((void *)(data->src));
  307. if (upper_32_bits(addr))
  308. printf("Error found for upper 32 bits\n");
  309. else
  310. esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
  311. #else
  312. esdhc_write32(&regs->dsaddr, (u32)data->src);
  313. #endif
  314. #endif
  315. }
  316. esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
  317. /* Calculate the timeout period for data transactions */
  318. /*
  319. * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
  320. * 2)Timeout period should be minimum 0.250sec as per SD Card spec
  321. * So, Number of SD Clock cycles for 0.25sec should be minimum
  322. * (SD Clock/sec * 0.25 sec) SD Clock cycles
  323. * = (mmc->clock * 1/4) SD Clock cycles
  324. * As 1) >= 2)
  325. * => (2^(timeout+13)) >= mmc->clock * 1/4
  326. * Taking log2 both the sides
  327. * => timeout + 13 >= log2(mmc->clock/4)
  328. * Rounding up to next power of 2
  329. * => timeout + 13 = log2(mmc->clock/4) + 1
  330. * => timeout + 13 = fls(mmc->clock/4)
  331. *
  332. * However, the MMC spec "It is strongly recommended for hosts to
  333. * implement more than 500ms timeout value even if the card
  334. * indicates the 250ms maximum busy length." Even the previous
  335. * value of 300ms is known to be insufficient for some cards.
  336. * So, we use
  337. * => timeout + 13 = fls(mmc->clock/2)
  338. */
  339. timeout = fls(mmc->clock/2);
  340. timeout -= 13;
  341. if (timeout > 14)
  342. timeout = 14;
  343. if (timeout < 0)
  344. timeout = 0;
  345. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
  346. if ((timeout == 4) || (timeout == 8) || (timeout == 12))
  347. timeout++;
  348. #endif
  349. #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  350. timeout = 0xE;
  351. #endif
  352. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
  353. return 0;
  354. }
  355. static void check_and_invalidate_dcache_range
  356. (struct mmc_cmd *cmd,
  357. struct mmc_data *data) {
  358. unsigned start = 0;
  359. unsigned end = 0;
  360. unsigned size = roundup(ARCH_DMA_MINALIGN,
  361. data->blocks*data->blocksize);
  362. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  363. dma_addr_t addr;
  364. addr = virt_to_phys((void *)(data->dest));
  365. if (upper_32_bits(addr))
  366. printf("Error found for upper 32 bits\n");
  367. else
  368. start = lower_32_bits(addr);
  369. #else
  370. start = (unsigned)data->dest;
  371. #endif
  372. end = start + size;
  373. invalidate_dcache_range(start, end);
  374. }
  375. #ifdef CONFIG_MCF5441x
  376. /*
  377. * Swaps 32-bit words to little-endian byte order.
  378. */
  379. static inline void sd_swap_dma_buff(struct mmc_data *data)
  380. {
  381. int i, size = data->blocksize >> 2;
  382. u32 *buffer = (u32 *)data->dest;
  383. u32 sw;
  384. while (data->blocks--) {
  385. for (i = 0; i < size; i++) {
  386. sw = __sw32(*buffer);
  387. *buffer++ = sw;
  388. }
  389. }
  390. }
  391. #endif
  392. /*
  393. * Sends a command out on the bus. Takes the mmc pointer,
  394. * a command pointer, and an optional data pointer.
  395. */
  396. static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  397. struct mmc_cmd *cmd, struct mmc_data *data)
  398. {
  399. int err = 0;
  400. uint xfertyp;
  401. uint irqstat;
  402. u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
  403. struct fsl_esdhc *regs = priv->esdhc_regs;
  404. unsigned long start;
  405. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  406. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  407. return 0;
  408. #endif
  409. esdhc_write32(&regs->irqstat, -1);
  410. sync();
  411. /* Wait for the bus to be idle */
  412. while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
  413. (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
  414. ;
  415. while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
  416. ;
  417. /* Wait at least 8 SD clock cycles before the next command */
  418. /*
  419. * Note: This is way more than 8 cycles, but 1ms seems to
  420. * resolve timing issues with some cards
  421. */
  422. udelay(1000);
  423. /* Set up for a data transfer if we have one */
  424. if (data) {
  425. err = esdhc_setup_data(priv, mmc, data);
  426. if(err)
  427. return err;
  428. if (data->flags & MMC_DATA_READ)
  429. check_and_invalidate_dcache_range(cmd, data);
  430. }
  431. /* Figure out the transfer arguments */
  432. xfertyp = esdhc_xfertyp(cmd, data);
  433. /* Mask all irqs */
  434. esdhc_write32(&regs->irqsigen, 0);
  435. /* Send the command */
  436. esdhc_write32(&regs->cmdarg, cmd->cmdarg);
  437. #if defined(CONFIG_FSL_USDHC)
  438. esdhc_write32(&regs->mixctrl,
  439. (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
  440. | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
  441. esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
  442. #else
  443. esdhc_write32(&regs->xfertyp, xfertyp);
  444. #endif
  445. if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
  446. (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
  447. flags = IRQSTAT_BRR;
  448. /* Wait for the command to complete */
  449. start = get_timer(0);
  450. while (!(esdhc_read32(&regs->irqstat) & flags)) {
  451. if (get_timer(start) > 1000) {
  452. err = -ETIMEDOUT;
  453. goto out;
  454. }
  455. }
  456. irqstat = esdhc_read32(&regs->irqstat);
  457. if (irqstat & CMD_ERR) {
  458. err = -ECOMM;
  459. goto out;
  460. }
  461. if (irqstat & IRQSTAT_CTOE) {
  462. err = -ETIMEDOUT;
  463. goto out;
  464. }
  465. /* Switch voltage to 1.8V if CMD11 succeeded */
  466. if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
  467. esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  468. printf("Run CMD11 1.8V switch\n");
  469. /* Sleep for 5 ms - max time for card to switch to 1.8V */
  470. udelay(5000);
  471. }
  472. /* Workaround for ESDHC errata ENGcm03648 */
  473. if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
  474. int timeout = 50000;
  475. /* Poll on DATA0 line for cmd with busy signal for 5000 ms */
  476. while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
  477. PRSSTAT_DAT0)) {
  478. udelay(100);
  479. timeout--;
  480. }
  481. if (timeout <= 0) {
  482. printf("Timeout waiting for DAT0 to go high!\n");
  483. err = -ETIMEDOUT;
  484. goto out;
  485. }
  486. }
  487. /* Copy the response to the response buffer */
  488. if (cmd->resp_type & MMC_RSP_136) {
  489. u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
  490. cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
  491. cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
  492. cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
  493. cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
  494. cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
  495. cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
  496. cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
  497. cmd->response[3] = (cmdrsp0 << 8);
  498. } else
  499. cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
  500. /* Wait until all of the blocks are transferred */
  501. if (data) {
  502. #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
  503. esdhc_pio_read_write(priv, data);
  504. #else
  505. flags = DATA_COMPLETE;
  506. if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
  507. (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
  508. flags = IRQSTAT_BRR;
  509. }
  510. do {
  511. irqstat = esdhc_read32(&regs->irqstat);
  512. if (irqstat & IRQSTAT_DTOE) {
  513. err = -ETIMEDOUT;
  514. goto out;
  515. }
  516. if (irqstat & DATA_ERR) {
  517. err = -ECOMM;
  518. goto out;
  519. }
  520. } while ((irqstat & flags) != flags);
  521. /*
  522. * Need invalidate the dcache here again to avoid any
  523. * cache-fill during the DMA operations such as the
  524. * speculative pre-fetching etc.
  525. */
  526. if (data->flags & MMC_DATA_READ) {
  527. check_and_invalidate_dcache_range(cmd, data);
  528. #ifdef CONFIG_MCF5441x
  529. sd_swap_dma_buff(data);
  530. #endif
  531. }
  532. #endif
  533. }
  534. out:
  535. /* Reset CMD and DATA portions on error */
  536. if (err) {
  537. esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
  538. SYSCTL_RSTC);
  539. while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
  540. ;
  541. if (data) {
  542. esdhc_write32(&regs->sysctl,
  543. esdhc_read32(&regs->sysctl) |
  544. SYSCTL_RSTD);
  545. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
  546. ;
  547. }
  548. /* If this was CMD11, then notify that power cycle is needed */
  549. if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
  550. printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
  551. }
  552. esdhc_write32(&regs->irqstat, -1);
  553. return err;
  554. }
  555. static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
  556. {
  557. struct fsl_esdhc *regs = priv->esdhc_regs;
  558. int div = 1;
  559. #ifdef ARCH_MXC
  560. #ifdef CONFIG_MX53
  561. /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
  562. int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
  563. #else
  564. int pre_div = 1;
  565. #endif
  566. #else
  567. int pre_div = 2;
  568. #endif
  569. int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
  570. int sdhc_clk = priv->sdhc_clk;
  571. uint clk;
  572. while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
  573. pre_div *= 2;
  574. while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
  575. div++;
  576. pre_div >>= 1;
  577. div -= 1;
  578. clk = (pre_div << 8) | (div << 4);
  579. #ifdef CONFIG_FSL_USDHC
  580. esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
  581. #else
  582. esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
  583. #endif
  584. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
  585. udelay(10000);
  586. #ifdef CONFIG_FSL_USDHC
  587. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
  588. #else
  589. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
  590. #endif
  591. priv->clock = clock;
  592. }
  593. #ifdef MMC_SUPPORTS_TUNING
  594. static int esdhc_change_pinstate(struct udevice *dev)
  595. {
  596. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  597. int ret;
  598. switch (priv->mode) {
  599. case UHS_SDR50:
  600. case UHS_DDR50:
  601. ret = pinctrl_select_state(dev, "state_100mhz");
  602. break;
  603. case UHS_SDR104:
  604. case MMC_HS_200:
  605. case MMC_HS_400:
  606. case MMC_HS_400_ES:
  607. ret = pinctrl_select_state(dev, "state_200mhz");
  608. break;
  609. default:
  610. ret = pinctrl_select_state(dev, "default");
  611. break;
  612. }
  613. if (ret)
  614. printf("%s %d error\n", __func__, priv->mode);
  615. return ret;
  616. }
  617. static void esdhc_reset_tuning(struct mmc *mmc)
  618. {
  619. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  620. struct fsl_esdhc *regs = priv->esdhc_regs;
  621. if (priv->flags & ESDHC_FLAG_USDHC) {
  622. if (priv->flags & ESDHC_FLAG_STD_TUNING) {
  623. esdhc_clrbits32(&regs->autoc12err,
  624. MIX_CTRL_SMPCLK_SEL |
  625. MIX_CTRL_EXE_TUNE);
  626. }
  627. }
  628. }
  629. static void esdhc_set_strobe_dll(struct mmc *mmc)
  630. {
  631. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  632. struct fsl_esdhc *regs = priv->esdhc_regs;
  633. u32 val;
  634. if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
  635. writel(ESDHC_STROBE_DLL_CTRL_RESET, &regs->strobe_dllctrl);
  636. /*
  637. * enable strobe dll ctrl and adjust the delay target
  638. * for the uSDHC loopback read clock
  639. */
  640. val = ESDHC_STROBE_DLL_CTRL_ENABLE |
  641. (priv->strobe_dll_delay_target <<
  642. ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
  643. writel(val, &regs->strobe_dllctrl);
  644. /* wait 1us to make sure strobe dll status register stable */
  645. mdelay(1);
  646. val = readl(&regs->strobe_dllstat);
  647. if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
  648. pr_warn("HS400 strobe DLL status REF not lock!\n");
  649. if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
  650. pr_warn("HS400 strobe DLL status SLV not lock!\n");
  651. }
  652. }
  653. static int esdhc_set_timing(struct mmc *mmc)
  654. {
  655. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  656. struct fsl_esdhc *regs = priv->esdhc_regs;
  657. u32 mixctrl;
  658. mixctrl = readl(&regs->mixctrl);
  659. mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
  660. switch (mmc->selected_mode) {
  661. case MMC_LEGACY:
  662. esdhc_reset_tuning(mmc);
  663. writel(mixctrl, &regs->mixctrl);
  664. break;
  665. case MMC_HS_400:
  666. case MMC_HS_400_ES:
  667. mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
  668. writel(mixctrl, &regs->mixctrl);
  669. esdhc_set_strobe_dll(mmc);
  670. break;
  671. case MMC_HS:
  672. case MMC_HS_52:
  673. case MMC_HS_200:
  674. case SD_HS:
  675. case UHS_SDR12:
  676. case UHS_SDR25:
  677. case UHS_SDR50:
  678. case UHS_SDR104:
  679. writel(mixctrl, &regs->mixctrl);
  680. break;
  681. case UHS_DDR50:
  682. case MMC_DDR_52:
  683. mixctrl |= MIX_CTRL_DDREN;
  684. writel(mixctrl, &regs->mixctrl);
  685. break;
  686. default:
  687. printf("Not supported %d\n", mmc->selected_mode);
  688. return -EINVAL;
  689. }
  690. priv->mode = mmc->selected_mode;
  691. return esdhc_change_pinstate(mmc->dev);
  692. }
  693. static int esdhc_set_voltage(struct mmc *mmc)
  694. {
  695. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  696. struct fsl_esdhc *regs = priv->esdhc_regs;
  697. int ret;
  698. priv->signal_voltage = mmc->signal_voltage;
  699. switch (mmc->signal_voltage) {
  700. case MMC_SIGNAL_VOLTAGE_330:
  701. if (priv->vs18_enable)
  702. return -ENOTSUPP;
  703. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  704. if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
  705. ret = regulator_set_value(priv->vqmmc_dev, 3300000);
  706. if (ret) {
  707. printf("Setting to 3.3V error");
  708. return -EIO;
  709. }
  710. /* Wait for 5ms */
  711. mdelay(5);
  712. }
  713. #endif
  714. esdhc_clrbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  715. if (!(esdhc_read32(&regs->vendorspec) &
  716. ESDHC_VENDORSPEC_VSELECT))
  717. return 0;
  718. return -EAGAIN;
  719. case MMC_SIGNAL_VOLTAGE_180:
  720. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  721. if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
  722. ret = regulator_set_value(priv->vqmmc_dev, 1800000);
  723. if (ret) {
  724. printf("Setting to 1.8V error");
  725. return -EIO;
  726. }
  727. }
  728. #endif
  729. esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  730. if (esdhc_read32(&regs->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
  731. return 0;
  732. return -EAGAIN;
  733. case MMC_SIGNAL_VOLTAGE_120:
  734. return -ENOTSUPP;
  735. default:
  736. return 0;
  737. }
  738. }
  739. static void esdhc_stop_tuning(struct mmc *mmc)
  740. {
  741. struct mmc_cmd cmd;
  742. cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
  743. cmd.cmdarg = 0;
  744. cmd.resp_type = MMC_RSP_R1b;
  745. dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
  746. }
  747. static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
  748. {
  749. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  750. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  751. struct fsl_esdhc *regs = priv->esdhc_regs;
  752. struct mmc *mmc = &plat->mmc;
  753. u32 irqstaten = readl(&regs->irqstaten);
  754. u32 irqsigen = readl(&regs->irqsigen);
  755. int i, ret = -ETIMEDOUT;
  756. u32 val, mixctrl;
  757. /* clock tuning is not needed for upto 52MHz */
  758. if (mmc->clock <= 52000000)
  759. return 0;
  760. /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
  761. if (priv->flags & ESDHC_FLAG_STD_TUNING) {
  762. val = readl(&regs->autoc12err);
  763. mixctrl = readl(&regs->mixctrl);
  764. val &= ~MIX_CTRL_SMPCLK_SEL;
  765. mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
  766. val |= MIX_CTRL_EXE_TUNE;
  767. mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
  768. writel(val, &regs->autoc12err);
  769. writel(mixctrl, &regs->mixctrl);
  770. }
  771. /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
  772. mixctrl = readl(&regs->mixctrl);
  773. mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
  774. writel(mixctrl, &regs->mixctrl);
  775. writel(IRQSTATEN_BRR, &regs->irqstaten);
  776. writel(IRQSTATEN_BRR, &regs->irqsigen);
  777. /*
  778. * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
  779. * of loops reaches 40 times.
  780. */
  781. for (i = 0; i < MAX_TUNING_LOOP; i++) {
  782. u32 ctrl;
  783. if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
  784. if (mmc->bus_width == 8)
  785. writel(0x7080, &regs->blkattr);
  786. else if (mmc->bus_width == 4)
  787. writel(0x7040, &regs->blkattr);
  788. } else {
  789. writel(0x7040, &regs->blkattr);
  790. }
  791. /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
  792. val = readl(&regs->mixctrl);
  793. val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
  794. writel(val, &regs->mixctrl);
  795. /* We are using STD tuning, no need to check return value */
  796. mmc_send_tuning(mmc, opcode, NULL);
  797. ctrl = readl(&regs->autoc12err);
  798. if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
  799. (ctrl & MIX_CTRL_SMPCLK_SEL)) {
  800. ret = 0;
  801. break;
  802. }
  803. }
  804. writel(irqstaten, &regs->irqstaten);
  805. writel(irqsigen, &regs->irqsigen);
  806. esdhc_stop_tuning(mmc);
  807. return ret;
  808. }
  809. #endif
  810. static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  811. {
  812. struct fsl_esdhc *regs = priv->esdhc_regs;
  813. int ret __maybe_unused;
  814. u32 clock;
  815. /* Set the clock speed */
  816. clock = mmc->clock;
  817. if (clock < mmc->cfg->f_min)
  818. clock = mmc->cfg->f_min;
  819. if (priv->clock != clock)
  820. set_sysctl(priv, mmc, clock);
  821. #ifdef MMC_SUPPORTS_TUNING
  822. if (mmc->clk_disable) {
  823. #ifdef CONFIG_FSL_USDHC
  824. esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
  825. #else
  826. esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
  827. #endif
  828. } else {
  829. #ifdef CONFIG_FSL_USDHC
  830. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
  831. VENDORSPEC_CKEN);
  832. #else
  833. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
  834. #endif
  835. }
  836. if (priv->mode != mmc->selected_mode) {
  837. ret = esdhc_set_timing(mmc);
  838. if (ret) {
  839. printf("esdhc_set_timing error %d\n", ret);
  840. return ret;
  841. }
  842. }
  843. if (priv->signal_voltage != mmc->signal_voltage) {
  844. ret = esdhc_set_voltage(mmc);
  845. if (ret) {
  846. if (ret != -ENOTSUPP)
  847. printf("esdhc_set_voltage error %d\n", ret);
  848. return ret;
  849. }
  850. }
  851. #endif
  852. /* Set the bus width */
  853. esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
  854. if (mmc->bus_width == 4)
  855. esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
  856. else if (mmc->bus_width == 8)
  857. esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
  858. return 0;
  859. }
  860. static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  861. {
  862. struct fsl_esdhc *regs = priv->esdhc_regs;
  863. ulong start;
  864. /* Reset the entire host controller */
  865. esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
  866. /* Wait until the controller is available */
  867. start = get_timer(0);
  868. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
  869. if (get_timer(start) > 1000)
  870. return -ETIMEDOUT;
  871. }
  872. #if defined(CONFIG_FSL_USDHC)
  873. /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
  874. esdhc_write32(&regs->mmcboot, 0x0);
  875. /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
  876. esdhc_write32(&regs->mixctrl, 0x0);
  877. esdhc_write32(&regs->clktunectrlstatus, 0x0);
  878. /* Put VEND_SPEC to default value */
  879. if (priv->vs18_enable)
  880. esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT |
  881. ESDHC_VENDORSPEC_VSELECT));
  882. else
  883. esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
  884. /* Disable DLL_CTRL delay line */
  885. esdhc_write32(&regs->dllctrl, 0x0);
  886. #endif
  887. #ifndef ARCH_MXC
  888. /* Enable cache snooping */
  889. esdhc_write32(&regs->scr, 0x00000040);
  890. #endif
  891. #ifndef CONFIG_FSL_USDHC
  892. esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
  893. #else
  894. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
  895. #endif
  896. /* Set the initial clock speed */
  897. mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
  898. /* Disable the BRR and BWR bits in IRQSTAT */
  899. esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
  900. #ifdef CONFIG_MCF5441x
  901. esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
  902. #else
  903. /* Put the PROCTL reg back to the default */
  904. esdhc_write32(&regs->proctl, PROCTL_INIT);
  905. #endif
  906. /* Set timout to the maximum value */
  907. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
  908. return 0;
  909. }
  910. static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
  911. {
  912. struct fsl_esdhc *regs = priv->esdhc_regs;
  913. int timeout = 1000;
  914. #ifdef CONFIG_ESDHC_DETECT_QUIRK
  915. if (CONFIG_ESDHC_DETECT_QUIRK)
  916. return 1;
  917. #endif
  918. #if CONFIG_IS_ENABLED(DM_MMC)
  919. if (priv->non_removable)
  920. return 1;
  921. if (priv->broken_cd)
  922. return 1;
  923. #if CONFIG_IS_ENABLED(DM_GPIO)
  924. if (dm_gpio_is_valid(&priv->cd_gpio))
  925. return dm_gpio_get_value(&priv->cd_gpio);
  926. #endif
  927. #endif
  928. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
  929. udelay(1000);
  930. return timeout > 0;
  931. }
  932. static int esdhc_reset(struct fsl_esdhc *regs)
  933. {
  934. ulong start;
  935. /* reset the controller */
  936. esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
  937. /* hardware clears the bit when it is done */
  938. start = get_timer(0);
  939. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
  940. if (get_timer(start) > 100) {
  941. printf("MMC/SD: Reset never completed.\n");
  942. return -ETIMEDOUT;
  943. }
  944. }
  945. return 0;
  946. }
  947. #if !CONFIG_IS_ENABLED(DM_MMC)
  948. static int esdhc_getcd(struct mmc *mmc)
  949. {
  950. struct fsl_esdhc_priv *priv = mmc->priv;
  951. return esdhc_getcd_common(priv);
  952. }
  953. static int esdhc_init(struct mmc *mmc)
  954. {
  955. struct fsl_esdhc_priv *priv = mmc->priv;
  956. return esdhc_init_common(priv, mmc);
  957. }
  958. static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  959. struct mmc_data *data)
  960. {
  961. struct fsl_esdhc_priv *priv = mmc->priv;
  962. return esdhc_send_cmd_common(priv, mmc, cmd, data);
  963. }
  964. static int esdhc_set_ios(struct mmc *mmc)
  965. {
  966. struct fsl_esdhc_priv *priv = mmc->priv;
  967. return esdhc_set_ios_common(priv, mmc);
  968. }
  969. static const struct mmc_ops esdhc_ops = {
  970. .getcd = esdhc_getcd,
  971. .init = esdhc_init,
  972. .send_cmd = esdhc_send_cmd,
  973. .set_ios = esdhc_set_ios,
  974. };
  975. #endif
  976. static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
  977. struct fsl_esdhc_plat *plat)
  978. {
  979. struct mmc_config *cfg;
  980. struct fsl_esdhc *regs;
  981. u32 caps, voltage_caps;
  982. int ret;
  983. if (!priv)
  984. return -EINVAL;
  985. regs = priv->esdhc_regs;
  986. /* First reset the eSDHC controller */
  987. ret = esdhc_reset(regs);
  988. if (ret)
  989. return ret;
  990. #ifdef CONFIG_MCF5441x
  991. /* ColdFire, using SDHC_DATA[3] for card detection */
  992. esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
  993. #endif
  994. #ifndef CONFIG_FSL_USDHC
  995. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
  996. | SYSCTL_IPGEN | SYSCTL_CKEN);
  997. /* Clearing tuning bits in case ROM has set it already */
  998. esdhc_write32(&regs->mixctrl, 0);
  999. esdhc_write32(&regs->autoc12err, 0);
  1000. esdhc_write32(&regs->clktunectrlstatus, 0);
  1001. #else
  1002. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
  1003. VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
  1004. #endif
  1005. if (priv->vs18_enable)
  1006. esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  1007. writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
  1008. cfg = &plat->cfg;
  1009. #ifndef CONFIG_DM_MMC
  1010. memset(cfg, '\0', sizeof(*cfg));
  1011. #endif
  1012. voltage_caps = 0;
  1013. caps = esdhc_read32(&regs->hostcapblt);
  1014. #ifdef CONFIG_MCF5441x
  1015. /*
  1016. * MCF5441x RM declares in more points that sdhc clock speed must
  1017. * never exceed 25 Mhz. From this, the HS bit needs to be disabled
  1018. * from host capabilities.
  1019. */
  1020. caps &= ~ESDHC_HOSTCAPBLT_HSS;
  1021. #endif
  1022. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
  1023. caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
  1024. ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
  1025. #endif
  1026. /* T4240 host controller capabilities register should have VS33 bit */
  1027. #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  1028. caps = caps | ESDHC_HOSTCAPBLT_VS33;
  1029. #endif
  1030. if (caps & ESDHC_HOSTCAPBLT_VS18)
  1031. voltage_caps |= MMC_VDD_165_195;
  1032. if (caps & ESDHC_HOSTCAPBLT_VS30)
  1033. voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
  1034. if (caps & ESDHC_HOSTCAPBLT_VS33)
  1035. voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
  1036. cfg->name = "FSL_SDHC";
  1037. #if !CONFIG_IS_ENABLED(DM_MMC)
  1038. cfg->ops = &esdhc_ops;
  1039. #endif
  1040. #ifdef CONFIG_SYS_SD_VOLTAGE
  1041. cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
  1042. #else
  1043. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  1044. #endif
  1045. if ((cfg->voltages & voltage_caps) == 0) {
  1046. printf("voltage not supported by controller\n");
  1047. return -1;
  1048. }
  1049. if (priv->bus_width == 8)
  1050. cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
  1051. else if (priv->bus_width == 4)
  1052. cfg->host_caps = MMC_MODE_4BIT;
  1053. cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
  1054. #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
  1055. cfg->host_caps |= MMC_MODE_DDR_52MHz;
  1056. #endif
  1057. if (priv->bus_width > 0) {
  1058. if (priv->bus_width < 8)
  1059. cfg->host_caps &= ~MMC_MODE_8BIT;
  1060. if (priv->bus_width < 4)
  1061. cfg->host_caps &= ~MMC_MODE_4BIT;
  1062. }
  1063. if (caps & ESDHC_HOSTCAPBLT_HSS)
  1064. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  1065. #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
  1066. if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
  1067. cfg->host_caps &= ~MMC_MODE_8BIT;
  1068. #endif
  1069. cfg->host_caps |= priv->caps;
  1070. cfg->f_min = 400000;
  1071. cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
  1072. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  1073. writel(0, &regs->dllctrl);
  1074. if (priv->flags & ESDHC_FLAG_USDHC) {
  1075. if (priv->flags & ESDHC_FLAG_STD_TUNING) {
  1076. u32 val = readl(&regs->tuning_ctrl);
  1077. val |= ESDHC_STD_TUNING_EN;
  1078. val &= ~ESDHC_TUNING_START_TAP_MASK;
  1079. val |= priv->tuning_start_tap;
  1080. val &= ~ESDHC_TUNING_STEP_MASK;
  1081. val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
  1082. /* Disable the CMD CRC check for tuning, if not, need to
  1083. * add some delay after every tuning command, because
  1084. * hardware standard tuning logic will directly go to next
  1085. * step once it detect the CMD CRC error, will not wait for
  1086. * the card side to finally send out the tuning data, trigger
  1087. * the buffer read ready interrupt immediately. If usdhc send
  1088. * the next tuning command some eMMC card will stuck, can't
  1089. * response, block the tuning procedure or the first command
  1090. * after the whole tuning procedure always can't get any response.
  1091. */
  1092. val |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
  1093. writel(val, &regs->tuning_ctrl);
  1094. }
  1095. }
  1096. return 0;
  1097. }
  1098. #if !CONFIG_IS_ENABLED(DM_MMC)
  1099. static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
  1100. struct fsl_esdhc_priv *priv)
  1101. {
  1102. if (!cfg || !priv)
  1103. return -EINVAL;
  1104. priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
  1105. priv->bus_width = cfg->max_bus_width;
  1106. priv->sdhc_clk = cfg->sdhc_clk;
  1107. priv->wp_enable = cfg->wp_enable;
  1108. priv->vs18_enable = cfg->vs18_enable;
  1109. return 0;
  1110. };
  1111. int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
  1112. {
  1113. struct fsl_esdhc_plat *plat;
  1114. struct fsl_esdhc_priv *priv;
  1115. struct mmc *mmc;
  1116. int ret;
  1117. if (!cfg)
  1118. return -EINVAL;
  1119. priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
  1120. if (!priv)
  1121. return -ENOMEM;
  1122. plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
  1123. if (!plat) {
  1124. free(priv);
  1125. return -ENOMEM;
  1126. }
  1127. ret = fsl_esdhc_cfg_to_priv(cfg, priv);
  1128. if (ret) {
  1129. debug("%s xlate failure\n", __func__);
  1130. free(plat);
  1131. free(priv);
  1132. return ret;
  1133. }
  1134. ret = fsl_esdhc_init(priv, plat);
  1135. if (ret) {
  1136. debug("%s init failure\n", __func__);
  1137. free(plat);
  1138. free(priv);
  1139. return ret;
  1140. }
  1141. mmc = mmc_create(&plat->cfg, priv);
  1142. if (!mmc)
  1143. return -EIO;
  1144. priv->mmc = mmc;
  1145. return 0;
  1146. }
  1147. int fsl_esdhc_mmc_init(bd_t *bis)
  1148. {
  1149. struct fsl_esdhc_cfg *cfg;
  1150. cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
  1151. cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
  1152. cfg->sdhc_clk = gd->arch.sdhc_clk;
  1153. return fsl_esdhc_initialize(bis, cfg);
  1154. }
  1155. #endif
  1156. #ifdef CONFIG_OF_LIBFDT
  1157. __weak int esdhc_status_fixup(void *blob, const char *compat)
  1158. {
  1159. #ifdef CONFIG_FSL_ESDHC_PIN_MUX
  1160. if (!hwconfig("esdhc")) {
  1161. do_fixup_by_compat(blob, compat, "status", "disabled",
  1162. sizeof("disabled"), 1);
  1163. return 1;
  1164. }
  1165. #endif
  1166. return 0;
  1167. }
  1168. void fdt_fixup_esdhc(void *blob, bd_t *bd)
  1169. {
  1170. const char *compat = "fsl,esdhc";
  1171. if (esdhc_status_fixup(blob, compat))
  1172. return;
  1173. do_fixup_by_compat_u32(blob, compat, "clock-frequency",
  1174. gd->arch.sdhc_clk, 1);
  1175. }
  1176. #endif
  1177. #if CONFIG_IS_ENABLED(DM_MMC)
  1178. #include <asm/arch/clock.h>
  1179. __weak void init_clk_usdhc(u32 index)
  1180. {
  1181. }
  1182. static int fsl_esdhc_probe(struct udevice *dev)
  1183. {
  1184. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  1185. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1186. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1187. const void *fdt = gd->fdt_blob;
  1188. int node = dev_of_offset(dev);
  1189. struct esdhc_soc_data *data =
  1190. (struct esdhc_soc_data *)dev_get_driver_data(dev);
  1191. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  1192. struct udevice *vqmmc_dev;
  1193. #endif
  1194. fdt_addr_t addr;
  1195. unsigned int val;
  1196. struct mmc *mmc;
  1197. #if !CONFIG_IS_ENABLED(BLK)
  1198. struct blk_desc *bdesc;
  1199. #endif
  1200. int ret;
  1201. addr = dev_read_addr(dev);
  1202. if (addr == FDT_ADDR_T_NONE)
  1203. return -EINVAL;
  1204. priv->esdhc_regs = (struct fsl_esdhc *)addr;
  1205. priv->dev = dev;
  1206. priv->mode = -1;
  1207. if (data)
  1208. priv->flags = data->flags;
  1209. val = dev_read_u32_default(dev, "bus-width", -1);
  1210. if (val == 8)
  1211. priv->bus_width = 8;
  1212. else if (val == 4)
  1213. priv->bus_width = 4;
  1214. else
  1215. priv->bus_width = 1;
  1216. val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
  1217. priv->tuning_step = val;
  1218. val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
  1219. ESDHC_TUNING_START_TAP_DEFAULT);
  1220. priv->tuning_start_tap = val;
  1221. val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
  1222. ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
  1223. priv->strobe_dll_delay_target = val;
  1224. if (dev_read_bool(dev, "broken-cd"))
  1225. priv->broken_cd = 1;
  1226. if (dev_read_bool(dev, "non-removable")) {
  1227. priv->non_removable = 1;
  1228. } else {
  1229. priv->non_removable = 0;
  1230. #if CONFIG_IS_ENABLED(DM_GPIO)
  1231. gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
  1232. GPIOD_IS_IN);
  1233. #endif
  1234. }
  1235. if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
  1236. priv->wp_enable = 1;
  1237. } else {
  1238. priv->wp_enable = 0;
  1239. #if CONFIG_IS_ENABLED(DM_GPIO)
  1240. gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
  1241. GPIOD_IS_IN);
  1242. #endif
  1243. }
  1244. priv->vs18_enable = 0;
  1245. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  1246. /*
  1247. * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
  1248. * otherwise, emmc will work abnormally.
  1249. */
  1250. ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
  1251. if (ret) {
  1252. dev_dbg(dev, "no vqmmc-supply\n");
  1253. } else {
  1254. priv->vqmmc_dev = vqmmc_dev;
  1255. ret = regulator_set_enable(vqmmc_dev, true);
  1256. if (ret) {
  1257. dev_err(dev, "fail to enable vqmmc-supply\n");
  1258. return ret;
  1259. }
  1260. if (regulator_get_value(vqmmc_dev) == 1800000)
  1261. priv->vs18_enable = 1;
  1262. }
  1263. #endif
  1264. /*
  1265. * TODO:
  1266. * Because lack of clk driver, if SDHC clk is not enabled,
  1267. * need to enable it first before this driver is invoked.
  1268. *
  1269. * we use MXC_ESDHC_CLK to get clk freq.
  1270. * If one would like to make this function work,
  1271. * the aliases should be provided in dts as this:
  1272. *
  1273. * aliases {
  1274. * mmc0 = &usdhc1;
  1275. * mmc1 = &usdhc2;
  1276. * mmc2 = &usdhc3;
  1277. * mmc3 = &usdhc4;
  1278. * };
  1279. * Then if your board only supports mmc2 and mmc3, but we can
  1280. * correctly get the seq as 2 and 3, then let mxc_get_clock
  1281. * work as expected.
  1282. */
  1283. init_clk_usdhc(dev->seq);
  1284. #if CONFIG_IS_ENABLED(CLK)
  1285. /* Assigned clock already set clock */
  1286. ret = clk_get_by_name(dev, "per", &priv->per_clk);
  1287. if (ret) {
  1288. printf("Failed to get per_clk\n");
  1289. return ret;
  1290. }
  1291. ret = clk_enable(&priv->per_clk);
  1292. if (ret) {
  1293. printf("Failed to enable per_clk\n");
  1294. return ret;
  1295. }
  1296. priv->sdhc_clk = clk_get_rate(&priv->per_clk);
  1297. #else
  1298. priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
  1299. if (priv->sdhc_clk <= 0) {
  1300. dev_err(dev, "Unable to get clk for %s\n", dev->name);
  1301. return -EINVAL;
  1302. }
  1303. #endif
  1304. ret = fsl_esdhc_init(priv, plat);
  1305. if (ret) {
  1306. dev_err(dev, "fsl_esdhc_init failure\n");
  1307. return ret;
  1308. }
  1309. ret = mmc_of_parse(dev, &plat->cfg);
  1310. if (ret)
  1311. return ret;
  1312. mmc = &plat->mmc;
  1313. mmc->cfg = &plat->cfg;
  1314. mmc->dev = dev;
  1315. #if !CONFIG_IS_ENABLED(BLK)
  1316. mmc->priv = priv;
  1317. /* Setup dsr related values */
  1318. mmc->dsr_imp = 0;
  1319. mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
  1320. /* Setup the universal parts of the block interface just once */
  1321. bdesc = mmc_get_blk_desc(mmc);
  1322. bdesc->if_type = IF_TYPE_MMC;
  1323. bdesc->removable = 1;
  1324. bdesc->devnum = mmc_get_next_devnum();
  1325. bdesc->block_read = mmc_bread;
  1326. bdesc->block_write = mmc_bwrite;
  1327. bdesc->block_erase = mmc_berase;
  1328. /* setup initial part type */
  1329. bdesc->part_type = mmc->cfg->part_type;
  1330. mmc_list_add(mmc);
  1331. #endif
  1332. upriv->mmc = mmc;
  1333. return esdhc_init_common(priv, mmc);
  1334. }
  1335. #if CONFIG_IS_ENABLED(DM_MMC)
  1336. static int fsl_esdhc_get_cd(struct udevice *dev)
  1337. {
  1338. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1339. return esdhc_getcd_common(priv);
  1340. }
  1341. static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  1342. struct mmc_data *data)
  1343. {
  1344. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1345. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1346. return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
  1347. }
  1348. static int fsl_esdhc_set_ios(struct udevice *dev)
  1349. {
  1350. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1351. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1352. return esdhc_set_ios_common(priv, &plat->mmc);
  1353. }
  1354. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  1355. static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
  1356. {
  1357. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1358. struct fsl_esdhc *regs = priv->esdhc_regs;
  1359. u32 m;
  1360. m = readl(&regs->mixctrl);
  1361. m |= MIX_CTRL_HS400_ES;
  1362. writel(m, &regs->mixctrl);
  1363. return 0;
  1364. }
  1365. #endif
  1366. static const struct dm_mmc_ops fsl_esdhc_ops = {
  1367. .get_cd = fsl_esdhc_get_cd,
  1368. .send_cmd = fsl_esdhc_send_cmd,
  1369. .set_ios = fsl_esdhc_set_ios,
  1370. #ifdef MMC_SUPPORTS_TUNING
  1371. .execute_tuning = fsl_esdhc_execute_tuning,
  1372. #endif
  1373. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  1374. .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
  1375. #endif
  1376. };
  1377. #endif
  1378. static struct esdhc_soc_data usdhc_imx7d_data = {
  1379. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
  1380. | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
  1381. | ESDHC_FLAG_HS400,
  1382. };
  1383. static struct esdhc_soc_data usdhc_imx8qm_data = {
  1384. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
  1385. ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
  1386. ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
  1387. };
  1388. static const struct udevice_id fsl_esdhc_ids[] = {
  1389. { .compatible = "fsl,imx53-esdhc", },
  1390. { .compatible = "fsl,imx6ul-usdhc", },
  1391. { .compatible = "fsl,imx6sx-usdhc", },
  1392. { .compatible = "fsl,imx6sl-usdhc", },
  1393. { .compatible = "fsl,imx6q-usdhc", },
  1394. { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
  1395. { .compatible = "fsl,imx7ulp-usdhc", },
  1396. { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1397. { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1398. { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1399. { .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1400. { .compatible = "fsl,imxrt-usdhc", },
  1401. { .compatible = "fsl,esdhc", },
  1402. { /* sentinel */ }
  1403. };
  1404. #if CONFIG_IS_ENABLED(BLK)
  1405. static int fsl_esdhc_bind(struct udevice *dev)
  1406. {
  1407. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1408. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  1409. }
  1410. #endif
  1411. U_BOOT_DRIVER(fsl_esdhc) = {
  1412. .name = "fsl-esdhc-mmc",
  1413. .id = UCLASS_MMC,
  1414. .of_match = fsl_esdhc_ids,
  1415. .ops = &fsl_esdhc_ops,
  1416. #if CONFIG_IS_ENABLED(BLK)
  1417. .bind = fsl_esdhc_bind,
  1418. #endif
  1419. .probe = fsl_esdhc_probe,
  1420. .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
  1421. .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
  1422. };
  1423. #endif