da850evm.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  4. *
  5. * Based on da830evm.c. Original Copyrights follow:
  6. *
  7. * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
  8. * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
  9. */
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <env.h>
  13. #include <i2c.h>
  14. #include <init.h>
  15. #include <net.h>
  16. #include <spi.h>
  17. #include <spi_flash.h>
  18. #include <asm/arch/hardware.h>
  19. #include <asm/ti-common/davinci_nand.h>
  20. #include <asm/arch/emac_defs.h>
  21. #include <asm/arch/pinmux_defs.h>
  22. #include <asm/io.h>
  23. #include <asm/arch/davinci_misc.h>
  24. #include <linux/errno.h>
  25. #include <hwconfig.h>
  26. #include <asm/mach-types.h>
  27. #include <asm/gpio.h>
  28. #ifdef CONFIG_MMC_DAVINCI
  29. #include <mmc.h>
  30. #include <asm/arch/sdmmc_defs.h>
  31. #endif
  32. DECLARE_GLOBAL_DATA_PTR;
  33. #ifdef CONFIG_DRIVER_TI_EMAC
  34. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  35. #define HAS_RMII 1
  36. #else
  37. #define HAS_RMII 0
  38. #endif
  39. #endif /* CONFIG_DRIVER_TI_EMAC */
  40. #define CFG_MAC_ADDR_SPI_BUS 0
  41. #define CFG_MAC_ADDR_SPI_CS 0
  42. #define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  43. #define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3
  44. #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K)
  45. #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
  46. static int get_mac_addr(u8 *addr)
  47. {
  48. struct spi_flash *flash;
  49. int ret;
  50. flash = spi_flash_probe(CFG_MAC_ADDR_SPI_BUS, CFG_MAC_ADDR_SPI_CS,
  51. CFG_MAC_ADDR_SPI_MAX_HZ, CFG_MAC_ADDR_SPI_MODE);
  52. if (!flash) {
  53. printf("Error - unable to probe SPI flash.\n");
  54. return -1;
  55. }
  56. ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET), 6, addr);
  57. if (ret) {
  58. printf("Error - unable to read MAC address from SPI flash.\n");
  59. return -1;
  60. }
  61. return ret;
  62. }
  63. #endif
  64. void dsp_lpsc_on(unsigned domain, unsigned int id)
  65. {
  66. dv_reg_p mdstat, mdctl, ptstat, ptcmd;
  67. struct davinci_psc_regs *psc_regs;
  68. psc_regs = davinci_psc0_regs;
  69. mdstat = &psc_regs->psc0.mdstat[id];
  70. mdctl = &psc_regs->psc0.mdctl[id];
  71. ptstat = &psc_regs->ptstat;
  72. ptcmd = &psc_regs->ptcmd;
  73. while (*ptstat & (0x1 << domain))
  74. ;
  75. if ((*mdstat & 0x1f) == 0x03)
  76. return; /* Already on and enabled */
  77. *mdctl |= 0x03;
  78. *ptcmd = 0x1 << domain;
  79. while (*ptstat & (0x1 << domain))
  80. ;
  81. while ((*mdstat & 0x1f) != 0x03)
  82. ; /* Probably an overkill... */
  83. }
  84. static void dspwake(void)
  85. {
  86. unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
  87. u32 val;
  88. /* if the device is ARM only, return */
  89. if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
  90. return;
  91. if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
  92. return;
  93. *resetvect++ = 0x1E000; /* DSP Idle */
  94. /* clear out the next 10 words as NOP */
  95. memset(resetvect, 0, sizeof(unsigned) *10);
  96. /* setup the DSP reset vector */
  97. writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
  98. dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
  99. val = readl(PSC0_MDCTL + (15 * 4));
  100. val |= 0x100;
  101. writel(val, (PSC0_MDCTL + (15 * 4)));
  102. }
  103. int misc_init_r(void)
  104. {
  105. dspwake();
  106. #if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) || defined(CONFIG_MAC_ADDR_IN_EEPROM)
  107. uchar env_enetaddr[6];
  108. int enetaddr_found;
  109. enetaddr_found = eth_env_get_enetaddr("ethaddr", env_enetaddr);
  110. #endif
  111. #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
  112. int spi_mac_read;
  113. uchar buff[6];
  114. spi_mac_read = get_mac_addr(buff);
  115. buff[0] = 0;
  116. /*
  117. * MAC address not present in the environment
  118. * try and read the MAC address from SPI flash
  119. * and set it.
  120. */
  121. if (!enetaddr_found) {
  122. if (!spi_mac_read) {
  123. if (is_valid_ethaddr(buff)) {
  124. if (eth_env_set_enetaddr("ethaddr", buff)) {
  125. printf("Warning: Failed to "
  126. "set MAC address from SPI flash\n");
  127. }
  128. } else {
  129. printf("Warning: Invalid "
  130. "MAC address read from SPI flash\n");
  131. }
  132. }
  133. } else {
  134. /*
  135. * MAC address present in environment compare it with
  136. * the MAC address in SPI flash and warn on mismatch
  137. */
  138. if (!spi_mac_read && is_valid_ethaddr(buff) &&
  139. memcmp(env_enetaddr, buff, 6))
  140. printf("Warning: MAC address in SPI flash don't match "
  141. "with the MAC address in the environment\n");
  142. printf("Default using MAC address from environment\n");
  143. }
  144. #elif defined(CONFIG_MAC_ADDR_IN_EEPROM)
  145. uint8_t enetaddr[8];
  146. int eeprom_mac_read;
  147. /* Read Ethernet MAC address from EEPROM */
  148. eeprom_mac_read = dvevm_read_mac_address(enetaddr);
  149. /*
  150. * MAC address not present in the environment
  151. * try and read the MAC address from EEPROM flash
  152. * and set it.
  153. */
  154. if (!enetaddr_found) {
  155. if (eeprom_mac_read)
  156. /* Set Ethernet MAC address from EEPROM */
  157. davinci_sync_env_enetaddr(enetaddr);
  158. } else {
  159. /*
  160. * MAC address present in environment compare it with
  161. * the MAC address in EEPROM and warn on mismatch
  162. */
  163. if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))
  164. printf("Warning: MAC address in EEPROM don't match "
  165. "with the MAC address in the environment\n");
  166. printf("Default using MAC address from environment\n");
  167. }
  168. #endif
  169. return 0;
  170. }
  171. static const struct pinmux_config gpio_pins[] = {
  172. #ifdef CONFIG_MTD_NOR_FLASH
  173. /* GP0[11] is required for NOR to work on Rev 3 EVMs */
  174. { pinmux(0), 8, 4 }, /* GP0[11] */
  175. #endif
  176. #ifdef CONFIG_MMC_DAVINCI
  177. /* GP0[11] is required for SD to work on Rev 3 EVMs */
  178. { pinmux(0), 8, 4 }, /* GP0[11] */
  179. #endif
  180. };
  181. const struct pinmux_resource pinmuxes[] = {
  182. #ifdef CONFIG_DRIVER_TI_EMAC
  183. PINMUX_ITEM(emac_pins_mdio),
  184. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  185. PINMUX_ITEM(emac_pins_rmii),
  186. #else
  187. PINMUX_ITEM(emac_pins_mii),
  188. #endif
  189. #endif
  190. #ifdef CONFIG_SPI_FLASH
  191. PINMUX_ITEM(spi1_pins_base),
  192. PINMUX_ITEM(spi1_pins_scs0),
  193. #endif
  194. PINMUX_ITEM(uart2_pins_txrx),
  195. PINMUX_ITEM(uart2_pins_rtscts),
  196. PINMUX_ITEM(i2c0_pins),
  197. #ifdef CONFIG_NAND_DAVINCI
  198. PINMUX_ITEM(emifa_pins_cs3),
  199. PINMUX_ITEM(emifa_pins_cs4),
  200. PINMUX_ITEM(emifa_pins_nand),
  201. #elif defined(CONFIG_MTD_NOR_FLASH)
  202. PINMUX_ITEM(emifa_pins_cs2),
  203. PINMUX_ITEM(emifa_pins_nor),
  204. #endif
  205. PINMUX_ITEM(gpio_pins),
  206. #ifdef CONFIG_MMC_DAVINCI
  207. PINMUX_ITEM(mmc0_pins),
  208. #endif
  209. };
  210. const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
  211. const struct lpsc_resource lpsc[] = {
  212. { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
  213. { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
  214. { DAVINCI_LPSC_EMAC }, /* image download */
  215. { DAVINCI_LPSC_UART2 }, /* console */
  216. { DAVINCI_LPSC_GPIO },
  217. #ifdef CONFIG_MMC_DAVINCI
  218. { DAVINCI_LPSC_MMC_SD },
  219. #endif
  220. };
  221. const int lpsc_size = ARRAY_SIZE(lpsc);
  222. #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
  223. #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000
  224. #endif
  225. #define REV_AM18X_EVM 0x100
  226. /*
  227. * get_board_rev() - setup to pass kernel board revision information
  228. * Returns:
  229. * bit[0-3] Maximum cpu clock rate supported by onboard SoC
  230. * 0000b - 300 MHz
  231. * 0001b - 372 MHz
  232. * 0010b - 408 MHz
  233. * 0011b - 456 MHz
  234. */
  235. u32 get_board_rev(void)
  236. {
  237. char *s;
  238. u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
  239. u32 rev = 0;
  240. s = env_get("maxcpuclk");
  241. if (s)
  242. maxcpuclk = simple_strtoul(s, NULL, 10);
  243. if (maxcpuclk >= 456000000)
  244. rev = 3;
  245. else if (maxcpuclk >= 408000000)
  246. rev = 2;
  247. else if (maxcpuclk >= 372000000)
  248. rev = 1;
  249. return rev;
  250. }
  251. int board_early_init_f(void)
  252. {
  253. /*
  254. * Power on required peripherals
  255. * ARM does not have access by default to PSC0 and PSC1
  256. * assuming here that the DSP bootloader has set the IOPU
  257. * such that PSC access is available to ARM
  258. */
  259. if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
  260. return 1;
  261. return 0;
  262. }
  263. int board_init(void)
  264. {
  265. irq_init();
  266. #ifdef CONFIG_NAND_DAVINCI
  267. /*
  268. * NAND CS setup - cycle counts based on da850evm NAND timings in the
  269. * Linux kernel @ 25MHz EMIFA
  270. */
  271. writel((DAVINCI_ABCR_WSETUP(2) |
  272. DAVINCI_ABCR_WSTROBE(2) |
  273. DAVINCI_ABCR_WHOLD(1) |
  274. DAVINCI_ABCR_RSETUP(1) |
  275. DAVINCI_ABCR_RSTROBE(4) |
  276. DAVINCI_ABCR_RHOLD(0) |
  277. DAVINCI_ABCR_TA(1) |
  278. DAVINCI_ABCR_ASIZE_8BIT),
  279. &davinci_emif_regs->ab2cr); /* CS3 */
  280. #endif
  281. /* arch number of the board */
  282. gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
  283. /* address of boot parameters */
  284. gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
  285. /* setup the SUSPSRC for ARM to control emulation suspend */
  286. writel(readl(&davinci_syscfg_regs->suspsrc) &
  287. ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
  288. DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
  289. DAVINCI_SYSCFG_SUSPSRC_UART2),
  290. &davinci_syscfg_regs->suspsrc);
  291. #ifdef CONFIG_MTD_NOR_FLASH
  292. /* Set the GPIO direction as output */
  293. clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
  294. /* Set the output as low */
  295. writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR);
  296. #endif
  297. #ifdef CONFIG_MMC_DAVINCI
  298. /* Set the GPIO direction as output */
  299. clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
  300. /* Set the output as high */
  301. writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR);
  302. #endif
  303. #ifdef CONFIG_DRIVER_TI_EMAC
  304. davinci_emac_mii_mode_sel(HAS_RMII);
  305. #endif /* CONFIG_DRIVER_TI_EMAC */
  306. return 0;
  307. }
  308. #ifdef CONFIG_DRIVER_TI_EMAC
  309. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  310. /**
  311. * rmii_hw_init
  312. *
  313. * DA850/OMAP-L138 EVM can interface to a daughter card for
  314. * additional features. This card has an I2C GPIO Expander TCA6416
  315. * to select the required functions like camera, RMII Ethernet,
  316. * character LCD, video.
  317. *
  318. * Initialization of the expander involves configuring the
  319. * polarity and direction of the ports. P07-P05 are used here.
  320. * These ports are connected to a Mux chip which enables only one
  321. * functionality at a time.
  322. *
  323. * For RMII phy to respond, the MII MDIO clock has to be disabled
  324. * since both the PHY devices have address as zero. The MII MDIO
  325. * clock is controlled via GPIO2[6].
  326. *
  327. * This code is valid for Beta version of the hardware
  328. */
  329. int rmii_hw_init(void)
  330. {
  331. const struct pinmux_config gpio_pins[] = {
  332. { pinmux(6), 8, 1 }
  333. };
  334. u_int8_t buf[2];
  335. unsigned int temp;
  336. int ret;
  337. /* PinMux for GPIO */
  338. if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
  339. return 1;
  340. /* I2C Exapnder configuration */
  341. /* Set polarity to non-inverted */
  342. buf[0] = 0x0;
  343. buf[1] = 0x0;
  344. ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
  345. if (ret) {
  346. printf("\nExpander @ 0x%02x write FAILED!!!\n",
  347. CONFIG_SYS_I2C_EXPANDER_ADDR);
  348. return ret;
  349. }
  350. /* Configure P07-P05 as outputs */
  351. buf[0] = 0x1f;
  352. buf[1] = 0xff;
  353. ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
  354. if (ret) {
  355. printf("\nExpander @ 0x%02x write FAILED!!!\n",
  356. CONFIG_SYS_I2C_EXPANDER_ADDR);
  357. }
  358. /* For Ethernet RMII selection
  359. * P07(SelA)=0
  360. * P06(SelB)=1
  361. * P05(SelC)=1
  362. */
  363. if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
  364. printf("\nExpander @ 0x%02x read FAILED!!!\n",
  365. CONFIG_SYS_I2C_EXPANDER_ADDR);
  366. }
  367. buf[0] &= 0x1f;
  368. buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
  369. if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
  370. printf("\nExpander @ 0x%02x write FAILED!!!\n",
  371. CONFIG_SYS_I2C_EXPANDER_ADDR);
  372. }
  373. /* Set the output as high */
  374. temp = REG(GPIO_BANK2_REG_SET_ADDR);
  375. temp |= (0x01 << 6);
  376. REG(GPIO_BANK2_REG_SET_ADDR) = temp;
  377. /* Set the GPIO direction as output */
  378. temp = REG(GPIO_BANK2_REG_DIR_ADDR);
  379. temp &= ~(0x01 << 6);
  380. REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
  381. return 0;
  382. }
  383. #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
  384. /*
  385. * Initializes on-board ethernet controllers.
  386. */
  387. int board_eth_init(bd_t *bis)
  388. {
  389. #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
  390. /* Select RMII fucntion through the expander */
  391. if (rmii_hw_init())
  392. printf("RMII hardware init failed!!!\n");
  393. #endif
  394. return 0;
  395. }
  396. #endif /* CONFIG_DRIVER_TI_EMAC */