common.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * K3: Common Architecture initialization
  4. *
  5. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  6. * Lokesh Vutla <lokeshvutla@ti.com>
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <image.h>
  11. #include <init.h>
  12. #include <log.h>
  13. #include <spl.h>
  14. #include "common.h"
  15. #include <dm.h>
  16. #include <remoteproc.h>
  17. #include <asm/cache.h>
  18. #include <linux/soc/ti/ti_sci_protocol.h>
  19. #include <fdt_support.h>
  20. #include <asm/arch/sys_proto.h>
  21. #include <asm/hardware.h>
  22. #include <asm/io.h>
  23. #include <fs_loader.h>
  24. #include <fs.h>
  25. #include <env.h>
  26. #include <elf.h>
  27. struct ti_sci_handle *get_ti_sci_handle(void)
  28. {
  29. struct udevice *dev;
  30. int ret;
  31. ret = uclass_get_device_by_driver(UCLASS_FIRMWARE,
  32. DM_GET_DRIVER(ti_sci), &dev);
  33. if (ret)
  34. panic("Failed to get SYSFW (%d)\n", ret);
  35. return (struct ti_sci_handle *)ti_sci_get_handle_from_sysfw(dev);
  36. }
  37. void k3_sysfw_print_ver(void)
  38. {
  39. struct ti_sci_handle *ti_sci = get_ti_sci_handle();
  40. char fw_desc[sizeof(ti_sci->version.firmware_description) + 1];
  41. /*
  42. * Output System Firmware version info. Note that since the
  43. * 'firmware_description' field is not guaranteed to be zero-
  44. * terminated we manually add a \0 terminator if needed. Further
  45. * note that we intentionally no longer rely on the extended
  46. * printf() formatter '%.*s' to not having to require a more
  47. * full-featured printf() implementation.
  48. */
  49. strncpy(fw_desc, ti_sci->version.firmware_description,
  50. sizeof(ti_sci->version.firmware_description));
  51. fw_desc[sizeof(fw_desc) - 1] = '\0';
  52. printf("SYSFW ABI: %d.%d (firmware rev 0x%04x '%s')\n",
  53. ti_sci->version.abi_major, ti_sci->version.abi_minor,
  54. ti_sci->version.firmware_revision, fw_desc);
  55. }
  56. DECLARE_GLOBAL_DATA_PTR;
  57. #ifdef CONFIG_K3_EARLY_CONS
  58. int early_console_init(void)
  59. {
  60. struct udevice *dev;
  61. int ret;
  62. gd->baudrate = CONFIG_BAUDRATE;
  63. ret = uclass_get_device_by_seq(UCLASS_SERIAL, CONFIG_K3_EARLY_CONS_IDX,
  64. &dev);
  65. if (ret) {
  66. printf("Error getting serial dev for early console! (%d)\n",
  67. ret);
  68. return ret;
  69. }
  70. gd->cur_serial_dev = dev;
  71. gd->flags |= GD_FLG_SERIAL_READY;
  72. gd->have_console = 1;
  73. return 0;
  74. }
  75. #endif
  76. #ifdef CONFIG_SYS_K3_SPL_ATF
  77. void init_env(void)
  78. {
  79. #ifdef CONFIG_SPL_ENV_SUPPORT
  80. char *part;
  81. env_init();
  82. env_relocate();
  83. switch (spl_boot_device()) {
  84. case BOOT_DEVICE_MMC2:
  85. part = env_get("bootpart");
  86. env_set("storage_interface", "mmc");
  87. env_set("fw_dev_part", part);
  88. break;
  89. case BOOT_DEVICE_SPI:
  90. env_set("storage_interface", "ubi");
  91. env_set("fw_ubi_mtdpart", "UBI");
  92. env_set("fw_ubi_volume", "UBI0");
  93. break;
  94. default:
  95. printf("%s from device %u not supported!\n",
  96. __func__, spl_boot_device());
  97. return;
  98. }
  99. #endif
  100. }
  101. #ifdef CONFIG_FS_LOADER
  102. int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
  103. {
  104. struct udevice *fsdev;
  105. char *name = NULL;
  106. int size = 0;
  107. *loadaddr = 0;
  108. #ifdef CONFIG_SPL_ENV_SUPPORT
  109. switch (spl_boot_device()) {
  110. case BOOT_DEVICE_MMC2:
  111. name = env_get(name_fw);
  112. *loadaddr = env_get_hex(name_loadaddr, *loadaddr);
  113. break;
  114. default:
  115. printf("Loading rproc fw image from device %u not supported!\n",
  116. spl_boot_device());
  117. return 0;
  118. }
  119. #endif
  120. if (!*loadaddr)
  121. return 0;
  122. if (!uclass_get_device(UCLASS_FS_FIRMWARE_LOADER, 0, &fsdev)) {
  123. size = request_firmware_into_buf(fsdev, name, (void *)*loadaddr,
  124. 0, 0);
  125. }
  126. return size;
  127. }
  128. #else
  129. int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
  130. {
  131. return 0;
  132. }
  133. #endif
  134. __weak void start_non_linux_remote_cores(void)
  135. {
  136. }
  137. void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
  138. {
  139. typedef void __noreturn (*image_entry_noargs_t)(void);
  140. struct ti_sci_handle *ti_sci = get_ti_sci_handle();
  141. u32 loadaddr = 0;
  142. int ret, size;
  143. /* Release all the exclusive devices held by SPL before starting ATF */
  144. ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
  145. ret = rproc_init();
  146. if (ret)
  147. panic("rproc failed to be initialized (%d)\n", ret);
  148. init_env();
  149. start_non_linux_remote_cores();
  150. size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
  151. &loadaddr);
  152. /*
  153. * It is assumed that remoteproc device 1 is the corresponding
  154. * Cortex-A core which runs ATF. Make sure DT reflects the same.
  155. */
  156. ret = rproc_load(1, spl_image->entry_point, 0x200);
  157. if (ret)
  158. panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
  159. /* Add an extra newline to differentiate the ATF logs from SPL */
  160. printf("Starting ATF on ARM64 core...\n\n");
  161. ret = rproc_start(1);
  162. if (ret)
  163. panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
  164. if (!(size > 0 && valid_elf_image(loadaddr))) {
  165. debug("Shutting down...\n");
  166. release_resources_for_core_shutdown();
  167. while (1)
  168. asm volatile("wfe");
  169. }
  170. image_entry_noargs_t image_entry =
  171. (image_entry_noargs_t)load_elf_image_phdr(loadaddr);
  172. image_entry();
  173. }
  174. #endif
  175. #if defined(CONFIG_OF_LIBFDT)
  176. int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
  177. {
  178. u64 msmc_start = 0, msmc_end = 0, msmc_size, reg[2];
  179. struct ti_sci_handle *ti_sci = get_ti_sci_handle();
  180. int ret, node, subnode, len, prev_node;
  181. u32 range[4], addr, size;
  182. const fdt32_t *sub_reg;
  183. ti_sci->ops.core_ops.query_msmc(ti_sci, &msmc_start, &msmc_end);
  184. msmc_size = msmc_end - msmc_start + 1;
  185. debug("%s: msmc_start = 0x%llx, msmc_size = 0x%llx\n", __func__,
  186. msmc_start, msmc_size);
  187. /* find or create "msmc_sram node */
  188. ret = fdt_path_offset(blob, parent_path);
  189. if (ret < 0)
  190. return ret;
  191. node = fdt_find_or_add_subnode(blob, ret, node_name);
  192. if (node < 0)
  193. return node;
  194. ret = fdt_setprop_string(blob, node, "compatible", "mmio-sram");
  195. if (ret < 0)
  196. return ret;
  197. reg[0] = cpu_to_fdt64(msmc_start);
  198. reg[1] = cpu_to_fdt64(msmc_size);
  199. ret = fdt_setprop(blob, node, "reg", reg, sizeof(reg));
  200. if (ret < 0)
  201. return ret;
  202. fdt_setprop_cell(blob, node, "#address-cells", 1);
  203. fdt_setprop_cell(blob, node, "#size-cells", 1);
  204. range[0] = 0;
  205. range[1] = cpu_to_fdt32(msmc_start >> 32);
  206. range[2] = cpu_to_fdt32(msmc_start & 0xffffffff);
  207. range[3] = cpu_to_fdt32(msmc_size);
  208. ret = fdt_setprop(blob, node, "ranges", range, sizeof(range));
  209. if (ret < 0)
  210. return ret;
  211. subnode = fdt_first_subnode(blob, node);
  212. prev_node = 0;
  213. /* Look for invalid subnodes and delete them */
  214. while (subnode >= 0) {
  215. sub_reg = fdt_getprop(blob, subnode, "reg", &len);
  216. addr = fdt_read_number(sub_reg, 1);
  217. sub_reg++;
  218. size = fdt_read_number(sub_reg, 1);
  219. debug("%s: subnode = %d, addr = 0x%x. size = 0x%x\n", __func__,
  220. subnode, addr, size);
  221. if (addr + size > msmc_size ||
  222. !strncmp(fdt_get_name(blob, subnode, &len), "sysfw", 5) ||
  223. !strncmp(fdt_get_name(blob, subnode, &len), "l3cache", 7)) {
  224. fdt_del_node(blob, subnode);
  225. debug("%s: deleting subnode %d\n", __func__, subnode);
  226. if (!prev_node)
  227. subnode = fdt_first_subnode(blob, node);
  228. else
  229. subnode = fdt_next_subnode(blob, prev_node);
  230. } else {
  231. prev_node = subnode;
  232. subnode = fdt_next_subnode(blob, prev_node);
  233. }
  234. }
  235. return 0;
  236. }
  237. int fdt_disable_node(void *blob, char *node_path)
  238. {
  239. int offs;
  240. int ret;
  241. offs = fdt_path_offset(blob, node_path);
  242. if (offs < 0) {
  243. printf("Node %s not found.\n", node_path);
  244. return offs;
  245. }
  246. ret = fdt_setprop_string(blob, offs, "status", "disabled");
  247. if (ret < 0) {
  248. printf("Could not add status property to node %s: %s\n",
  249. node_path, fdt_strerror(ret));
  250. return ret;
  251. }
  252. return 0;
  253. }
  254. #endif
  255. #ifndef CONFIG_SYSRESET
  256. void reset_cpu(ulong ignored)
  257. {
  258. }
  259. #endif
  260. #if defined(CONFIG_DISPLAY_CPUINFO)
  261. int print_cpuinfo(void)
  262. {
  263. u32 soc, rev;
  264. char *name;
  265. soc = (readl(CTRLMMR_WKUP_JTAG_ID) &
  266. JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT;
  267. rev = (readl(CTRLMMR_WKUP_JTAG_ID) &
  268. JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT;
  269. printf("SoC: ");
  270. switch (soc) {
  271. case AM65X:
  272. name = "AM65x";
  273. break;
  274. case J721E:
  275. name = "J721E";
  276. break;
  277. default:
  278. name = "Unknown Silicon";
  279. };
  280. printf("%s SR ", name);
  281. switch (rev) {
  282. case REV_PG1_0:
  283. name = "1.0";
  284. break;
  285. case REV_PG2_0:
  286. name = "2.0";
  287. break;
  288. default:
  289. name = "Unknown Revision";
  290. };
  291. printf("%s\n", name);
  292. return 0;
  293. }
  294. #endif
  295. #ifdef CONFIG_ARM64
  296. void board_prep_linux(bootm_headers_t *images)
  297. {
  298. debug("Linux kernel Image start = 0x%lx end = 0x%lx\n",
  299. images->os.start, images->os.end);
  300. __asm_flush_dcache_range(images->os.start,
  301. ROUND(images->os.end,
  302. CONFIG_SYS_CACHELINE_SIZE));
  303. }
  304. #endif
  305. #ifdef CONFIG_CPU_V7R
  306. void disable_linefill_optimization(void)
  307. {
  308. u32 actlr;
  309. /*
  310. * On K3 devices there are 2 conditions where R5F can deadlock:
  311. * 1.When software is performing series of store operations to
  312. * cacheable write back/write allocate memory region and later
  313. * on software execute barrier operation (DSB or DMB). R5F may
  314. * hang at the barrier instruction.
  315. * 2.When software is performing a mix of load and store operations
  316. * within a tight loop and store operations are all writing to
  317. * cacheable write back/write allocates memory regions, R5F may
  318. * hang at one of the load instruction.
  319. *
  320. * To avoid the above two conditions disable linefill optimization
  321. * inside Cortex R5F.
  322. */
  323. asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
  324. actlr |= (1 << 13); /* Set DLFO bit */
  325. asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
  326. }
  327. #endif
  328. void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
  329. {
  330. struct ti_sci_msg_fwl_region region;
  331. struct ti_sci_fwl_ops *fwl_ops;
  332. struct ti_sci_handle *ti_sci;
  333. size_t i, j;
  334. ti_sci = get_ti_sci_handle();
  335. fwl_ops = &ti_sci->ops.fwl_ops;
  336. for (i = 0; i < fwl_data_size; i++) {
  337. for (j = 0; j < fwl_data[i].regions; j++) {
  338. region.fwl_id = fwl_data[i].fwl_id;
  339. region.region = j;
  340. region.n_permission_regs = 3;
  341. fwl_ops->get_fwl_region(ti_sci, &region);
  342. if (region.control != 0) {
  343. pr_debug("Attempting to disable firewall %5d (%25s)\n",
  344. region.fwl_id, fwl_data[i].name);
  345. region.control = 0;
  346. if (fwl_ops->set_fwl_region(ti_sci, &region))
  347. pr_err("Could not disable firewall %5d (%25s)\n",
  348. region.fwl_id, fwl_data[i].name);
  349. }
  350. }
  351. }
  352. }
  353. void spl_enable_dcache(void)
  354. {
  355. #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  356. phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
  357. dram_init_banksize();
  358. /* reserve TLB table */
  359. gd->arch.tlb_size = PGTABLE_SIZE;
  360. ram_top += get_effective_memsize();
  361. /* keep ram_top in the 32-bit address space */
  362. if (ram_top >= 0x100000000)
  363. ram_top = (phys_addr_t) 0x100000000;
  364. gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
  365. debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
  366. gd->arch.tlb_addr + gd->arch.tlb_size);
  367. dcache_enable();
  368. #endif
  369. }
  370. #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  371. void spl_board_prepare_for_boot(void)
  372. {
  373. dcache_disable();
  374. }
  375. void spl_board_prepare_for_linux(void)
  376. {
  377. dcache_disable();
  378. }
  379. #endif