k3-j721e-mcu-wakeup.dtsi 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
  4. *
  5. * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
  6. */
  7. &cbass_mcu_wakeup {
  8. dmsc: dmsc@44083000 {
  9. compatible = "ti,k2g-sci";
  10. ti,host-id = <12>;
  11. mbox-names = "rx", "tx";
  12. mboxes= <&secure_proxy_main 11>,
  13. <&secure_proxy_main 13>;
  14. reg-names = "debug_messages";
  15. reg = <0x00 0x44083000 0x0 0x1000>;
  16. k3_pds: power-controller {
  17. compatible = "ti,sci-pm-domain";
  18. #power-domain-cells = <2>;
  19. };
  20. k3_clks: clocks {
  21. compatible = "ti,k2g-sci-clk";
  22. #clock-cells = <2>;
  23. ti,scan-clocks-from-dt;
  24. };
  25. k3_reset: reset-controller {
  26. compatible = "ti,sci-reset";
  27. #reset-cells = <2>;
  28. };
  29. };
  30. mcu_conf: syscon@40f00000 {
  31. compatible = "syscon", "simple-mfd";
  32. reg = <0x0 0x40f00000 0x0 0x20000>;
  33. #address-cells = <1>;
  34. #size-cells = <1>;
  35. ranges = <0x0 0x0 0x40f00000 0x20000>;
  36. phy_gmii_sel: phy@4040 {
  37. compatible = "ti,am654-phy-gmii-sel";
  38. reg = <0x4040 0x4>;
  39. #phy-cells = <1>;
  40. };
  41. };
  42. wkup_pmx0: pinmux@4301c000 {
  43. compatible = "pinctrl-single";
  44. /* Proxy 0 addressing */
  45. reg = <0x00 0x4301c000 0x00 0x178>;
  46. #pinctrl-cells = <1>;
  47. pinctrl-single,register-width = <32>;
  48. pinctrl-single,function-mask = <0xffffffff>;
  49. };
  50. wkup_uart0: serial@42300000 {
  51. compatible = "ti,j721e-uart", "ti,am654-uart";
  52. reg = <0x00 0x42300000 0x00 0x100>;
  53. reg-shift = <2>;
  54. reg-io-width = <4>;
  55. interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
  56. clock-frequency = <48000000>;
  57. current-speed = <115200>;
  58. power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
  59. clocks = <&k3_clks 287 0>;
  60. clock-names = "fclk";
  61. };
  62. wkup_i2c0: i2c@42120000 {
  63. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  64. reg = <0x0 0x42120000 0x0 0x100>;
  65. interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
  66. #address-cells = <1>;
  67. #size-cells = <0>;
  68. clock-names = "fck";
  69. clocks = <&k3_clks 197 0>;
  70. power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
  71. };
  72. mcu_uart0: serial@40a00000 {
  73. compatible = "ti,j721e-uart", "ti,am654-uart";
  74. reg = <0x00 0x40a00000 0x00 0x100>;
  75. reg-shift = <2>;
  76. reg-io-width = <4>;
  77. interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
  78. clock-frequency = <96000000>;
  79. current-speed = <115200>;
  80. power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
  81. clocks = <&k3_clks 149 0>;
  82. clock-names = "fclk";
  83. };
  84. mcu_r5fss0: r5fss@41000000 {
  85. compatible = "ti,j721e-r5fss";
  86. lockstep-mode = <1>;
  87. #address-cells = <1>;
  88. #size-cells = <1>;
  89. ranges = <0x41000000 0x00 0x41000000 0x20000>,
  90. <0x41400000 0x00 0x41400000 0x20000>;
  91. power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
  92. mcu_r5fss0_core0: r5f@41000000 {
  93. compatible = "ti,j721e-r5f";
  94. reg = <0x41000000 0x00008000>,
  95. <0x41010000 0x00008000>;
  96. reg-names = "atcm", "btcm";
  97. ti,sci = <&dmsc>;
  98. ti,sci-dev-id = <250>;
  99. ti,sci-proc-ids = <0x01 0xFF>;
  100. resets = <&k3_reset 250 1>;
  101. atcm-enable = <1>;
  102. btcm-enable = <1>;
  103. loczrama = <1>;
  104. };
  105. mcu_r5fss0_core1: r5f@41400000 {
  106. compatible = "ti,j721e-r5f";
  107. reg = <0x41400000 0x00008000>,
  108. <0x41410000 0x00008000>;
  109. reg-names = "atcm", "btcm";
  110. ti,sci = <&dmsc>;
  111. ti,sci-dev-id = <251>;
  112. ti,sci-proc-ids = <0x02 0xFF>;
  113. resets = <&k3_reset 251 1>;
  114. atcm-enable = <1>;
  115. btcm-enable = <1>;
  116. loczrama = <1>;
  117. };
  118. };
  119. fss: fss@47000000 {
  120. compatible = "syscon", "simple-mfd";
  121. reg = <0x0 0x47000000 0x0 0x100>;
  122. #address-cells = <2>;
  123. #size-cells = <2>;
  124. ranges;
  125. hbmc_mux: hbmc-mux {
  126. compatible = "mmio-mux";
  127. #mux-control-cells = <1>;
  128. mux-reg-masks = <0x4 0x2>; /* HBMC select */
  129. };
  130. hbmc: hyperbus@47034000 {
  131. compatible = "ti,j721e-hbmc", "ti,am654-hbmc";
  132. reg = <0x0 0x47034000 0x0 0x100>,
  133. <0x5 0x00000000 0x1 0x0000000>;
  134. power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
  135. #address-cells = <2>;
  136. #size-cells = <1>;
  137. mux-controls = <&hbmc_mux 0>;
  138. assigned-clocks = <&k3_clks 102 0>;
  139. assigned-clock-rates = <250000000>;
  140. };
  141. ospi0: spi@47040000 {
  142. compatible = "ti,am654-ospi";
  143. reg = <0x0 0x47040000 0x0 0x100>,
  144. <0x5 0x00000000 0x1 0x0000000>;
  145. interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
  146. cdns,fifo-depth = <256>;
  147. cdns,fifo-width = <4>;
  148. cdns,trigger-address = <0x0>;
  149. clocks = <&k3_clks 103 0>;
  150. assigned-clocks = <&k3_clks 103 0>;
  151. assigned-clock-parents = <&k3_clks 103 2>;
  152. assigned-clock-rates = <166666666>;
  153. power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
  154. #address-cells = <1>;
  155. #size-cells = <0>;
  156. };
  157. ospi1: spi@47050000 {
  158. compatible = "ti,am654-ospi";
  159. reg = <0x0 0x47050000 0x0 0x100>,
  160. <0x7 0x00000000 0x1 0x00000000>;
  161. interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
  162. cdns,fifo-depth = <256>;
  163. cdns,fifo-width = <4>;
  164. cdns,trigger-address = <0x0>;
  165. clocks = <&k3_clks 104 0>;
  166. assigned-clocks = <&k3_clks 104 0>;
  167. assigned-clock-rates = <133333333>;
  168. power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
  169. #address-cells = <1>;
  170. #size-cells = <0>;
  171. };
  172. };
  173. mcu_i2c0: i2c@40b00000 {
  174. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  175. reg = <0x0 0x40b00000 0x0 0x100>;
  176. interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
  177. #address-cells = <1>;
  178. #size-cells = <0>;
  179. clock-names = "fck";
  180. clocks = <&k3_clks 194 0>;
  181. power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
  182. };
  183. mcu_i2c1: i2c@40b10000 {
  184. compatible = "ti,j721e-i2c", "ti,omap4-i2c";
  185. reg = <0x0 0x40b10000 0x0 0x100>;
  186. interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
  187. #address-cells = <1>;
  188. #size-cells = <0>;
  189. clock-names = "fck";
  190. clocks = <&k3_clks 195 0>;
  191. power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
  192. };
  193. mcu_navss {
  194. compatible = "simple-mfd";
  195. #address-cells = <2>;
  196. #size-cells = <2>;
  197. ranges;
  198. dma-coherent;
  199. dma-ranges;
  200. ti,sci-dev-id = <232>;
  201. mcu_ringacc: ringacc@2b800000 {
  202. compatible = "ti,am654-navss-ringacc";
  203. reg = <0x0 0x2b800000 0x0 0x400000>,
  204. <0x0 0x2b000000 0x0 0x400000>,
  205. <0x0 0x28590000 0x0 0x100>,
  206. <0x0 0x2a500000 0x0 0x40000>;
  207. reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
  208. ti,num-rings = <286>;
  209. ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
  210. ti,sci = <&dmsc>;
  211. ti,sci-dev-id = <235>;
  212. };
  213. mcu_udmap: dma-controller@285c0000 {
  214. compatible = "ti,j721e-navss-mcu-udmap";
  215. reg = <0x0 0x285c0000 0x0 0x100>,
  216. <0x0 0x2a800000 0x0 0x40000>,
  217. <0x0 0x2aa00000 0x0 0x40000>;
  218. reg-names = "gcfg", "rchanrt", "tchanrt";
  219. #dma-cells = <1>;
  220. ti,sci = <&dmsc>;
  221. ti,sci-dev-id = <236>;
  222. ti,ringacc = <&mcu_ringacc>;
  223. ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
  224. <0x0f>; /* TX_HCHAN */
  225. ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
  226. <0x0b>; /* RX_HCHAN */
  227. ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
  228. };
  229. };
  230. mcu_cpsw: ethernet@46000000 {
  231. compatible = "ti,j721e-cpsw-nuss";
  232. #address-cells = <2>;
  233. #size-cells = <2>;
  234. reg = <0x0 0x46000000 0x0 0x200000>;
  235. reg-names = "cpsw_nuss";
  236. ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
  237. dma-coherent;
  238. clocks = <&k3_clks 18 22>;
  239. clock-names = "fck";
  240. power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
  241. dmas = <&mcu_udmap 0xf000>,
  242. <&mcu_udmap 0xf001>,
  243. <&mcu_udmap 0xf002>,
  244. <&mcu_udmap 0xf003>,
  245. <&mcu_udmap 0xf004>,
  246. <&mcu_udmap 0xf005>,
  247. <&mcu_udmap 0xf006>,
  248. <&mcu_udmap 0xf007>,
  249. <&mcu_udmap 0x7000>;
  250. dma-names = "tx0", "tx1", "tx2", "tx3",
  251. "tx4", "tx5", "tx6", "tx7",
  252. "rx";
  253. ethernet-ports {
  254. #address-cells = <1>;
  255. #size-cells = <0>;
  256. cpsw_port1: port@1 {
  257. reg = <1>;
  258. ti,mac-only;
  259. label = "port1";
  260. ti,syscon-efuse = <&mcu_conf 0x200>;
  261. phys = <&phy_gmii_sel 1>;
  262. };
  263. };
  264. davinci_mdio: mdio@f00 {
  265. compatible = "ti,cpsw-mdio","ti,davinci_mdio";
  266. reg = <0x0 0xf00 0x0 0x100>;
  267. #address-cells = <1>;
  268. #size-cells = <0>;
  269. clocks = <&k3_clks 18 22>;
  270. clock-names = "fck";
  271. bus_freq = <1000000>;
  272. };
  273. cpts@3d000 {
  274. compatible = "ti,am65-cpts";
  275. reg = <0x0 0x3d000 0x0 0x400>;
  276. clocks = <&k3_clks 18 2>;
  277. clock-names = "cpts";
  278. interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
  279. interrupt-names = "cpts";
  280. ti,cpts-ext-ts-inputs = <4>;
  281. ti,cpts-periodic-outputs = <2>;
  282. };
  283. };
  284. };