k3-am654-base-board-u-boot.dtsi 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  4. */
  5. #include <dt-bindings/pinctrl/k3.h>
  6. #include <dt-bindings/net/ti-dp83867.h>
  7. / {
  8. chosen {
  9. stdout-path = "serial2:115200n8";
  10. };
  11. aliases {
  12. serial2 = &main_uart0;
  13. ethernet0 = &cpsw_port1;
  14. };
  15. };
  16. &cbass_main{
  17. u-boot,dm-spl;
  18. sdhci1: sdhci@04FA0000 {
  19. compatible = "ti,am654-sdhci-5.1";
  20. reg = <0x0 0x4FA0000 0x0 0x1000>,
  21. <0x0 0x4FB0000 0x0 0x400>;
  22. clocks =<&k3_clks 48 0>, <&k3_clks 48 1>;
  23. clock-names = "clk_ahb", "clk_xin";
  24. power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
  25. max-frequency = <25000000>;
  26. ti,otap-del-sel-legacy = <0x0>;
  27. ti,otap-del-sel-mmc-hs = <0x0>;
  28. ti,otap-del-sel-sd-hs = <0x0>;
  29. ti,otap-del-sel-sdr12 = <0x0>;
  30. ti,otap-del-sel-sdr25 = <0x0>;
  31. ti,otap-del-sel-sdr50 = <0x8>;
  32. ti,otap-del-sel-sdr104 = <0x7>;
  33. ti,otap-del-sel-ddr50 = <0x4>;
  34. ti,otap-del-sel-ddr52 = <0x4>;
  35. ti,otap-del-sel-hs200 = <0x7>;
  36. ti,trm-icp = <0x8>;
  37. };
  38. };
  39. &cbass_mcu {
  40. u-boot,dm-spl;
  41. mcu_navss {
  42. u-boot,dm-spl;
  43. ringacc@2b800000 {
  44. u-boot,dm-spl;
  45. };
  46. dma-controller@285c0000 {
  47. u-boot,dm-spl;
  48. };
  49. };
  50. };
  51. &cbass_wakeup {
  52. u-boot,dm-spl;
  53. };
  54. &secure_proxy_main {
  55. u-boot,dm-spl;
  56. };
  57. &dmsc {
  58. u-boot,dm-spl;
  59. k3_sysreset: sysreset-controller {
  60. compatible = "ti,sci-sysreset";
  61. u-boot,dm-spl;
  62. };
  63. };
  64. &k3_pds {
  65. u-boot,dm-spl;
  66. };
  67. &k3_clks {
  68. u-boot,dm-spl;
  69. };
  70. &k3_reset {
  71. u-boot,dm-spl;
  72. };
  73. &wkup_pmx0 {
  74. u-boot,dm-spl;
  75. wkup_i2c0_pins_default {
  76. u-boot,dm-spl;
  77. };
  78. };
  79. &main_pmx0 {
  80. u-boot,dm-spl;
  81. main_uart0_pins_default: main_uart0_pins_default {
  82. pinctrl-single,pins = <
  83. AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
  84. AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
  85. AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
  86. AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
  87. >;
  88. u-boot,dm-spl;
  89. };
  90. main_mmc0_pins_default: main_mmc0_pins_default {
  91. pinctrl-single,pins = <
  92. AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
  93. AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
  94. AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
  95. AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
  96. AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
  97. AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
  98. AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
  99. AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
  100. AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
  101. AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
  102. AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
  103. AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
  104. >;
  105. u-boot,dm-spl;
  106. };
  107. main_mmc1_pins_default: main_mmc1_pins_default {
  108. pinctrl-single,pins = <
  109. AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
  110. AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
  111. AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
  112. AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
  113. AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
  114. AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
  115. AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
  116. AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
  117. >;
  118. u-boot,dm-spl;
  119. };
  120. };
  121. &main_pmx1 {
  122. u-boot,dm-spl;
  123. };
  124. &wkup_pmx0 {
  125. mcu_cpsw_pins_default: mcu_cpsw_pins_default {
  126. pinctrl-single,pins = <
  127. AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
  128. AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
  129. AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
  130. AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
  131. AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
  132. AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
  133. AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
  134. AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
  135. AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
  136. AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
  137. AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
  138. AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
  139. >;
  140. };
  141. mcu_mdio_pins_default: mcu_mdio1_pins_default {
  142. pinctrl-single,pins = <
  143. AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
  144. AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
  145. >;
  146. };
  147. mcu-fss0-ospi0-pins-default {
  148. u-boot,dm-spl;
  149. };
  150. };
  151. &main_uart0 {
  152. u-boot,dm-spl;
  153. pinctrl-names = "default";
  154. pinctrl-0 = <&main_uart0_pins_default>;
  155. status = "okay";
  156. };
  157. &sdhci0 {
  158. u-boot,dm-spl;
  159. };
  160. &sdhci1 {
  161. u-boot,dm-spl;
  162. status = "okay";
  163. pinctrl-names = "default";
  164. pinctrl-0 = <&main_mmc1_pins_default>;
  165. sdhci-caps-mask = <0x7 0x0>;
  166. ti,driver-strength-ohm = <50>;
  167. };
  168. &mcu_cpsw {
  169. pinctrl-names = "default";
  170. pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
  171. };
  172. &davinci_mdio {
  173. phy0: ethernet-phy@0 {
  174. reg = <0>;
  175. /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
  176. ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  177. ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  178. };
  179. };
  180. &cpsw_port1 {
  181. phy-mode = "rgmii-rxid";
  182. phy-handle = <&phy0>;
  183. };
  184. &mcu_cpsw {
  185. reg = <0x0 0x46000000 0x0 0x200000>,
  186. <0x0 0x40f00200 0x0 0x2>;
  187. reg-names = "cpsw_nuss", "mac_efuse";
  188. /delete-property/ ranges;
  189. cpsw-phy-sel@40f04040 {
  190. compatible = "ti,am654-cpsw-phy-sel";
  191. reg= <0x0 0x40f04040 0x0 0x4>;
  192. reg-names = "gmii-sel";
  193. };
  194. };
  195. &wkup_i2c0 {
  196. u-boot,dm-spl;
  197. };
  198. &usb1 {
  199. dr_mode = "peripheral";
  200. };
  201. &fss {
  202. u-boot,dm-spl;
  203. };
  204. &ospi0 {
  205. u-boot,dm-spl;
  206. flash@0{
  207. u-boot,dm-spl;
  208. };
  209. };