k3-am65-mcu.dtsi 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Device Tree Source for AM6 SoC Family MCU Domain peripherals
  4. *
  5. * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
  6. */
  7. &cbass_mcu {
  8. mcu_conf: scm_conf@40f00000 {
  9. compatible = "syscon", "simple-mfd";
  10. reg = <0x0 0x40f00000 0x0 0x20000>;
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. ranges = <0x0 0x0 0x40f00000 0x20000>;
  14. phy_gmii_sel: phy@4040 {
  15. compatible = "ti,am654-phy-gmii-sel";
  16. reg = <0x4040 0x4>;
  17. #phy-cells = <1>;
  18. };
  19. };
  20. mcu_uart0: serial@40a00000 {
  21. compatible = "ti,am654-uart";
  22. reg = <0x00 0x40a00000 0x00 0x100>;
  23. reg-shift = <2>;
  24. reg-io-width = <4>;
  25. interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
  26. clock-frequency = <96000000>;
  27. current-speed = <115200>;
  28. };
  29. mcu_i2c0: i2c@40b00000 {
  30. compatible = "ti,am654-i2c", "ti,omap4-i2c";
  31. reg = <0x0 0x40b00000 0x0 0x100>;
  32. interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
  33. #address-cells = <1>;
  34. #size-cells = <0>;
  35. clock-names = "fck";
  36. clocks = <&k3_clks 114 1>;
  37. power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
  38. };
  39. mcu_r5fss0: r5fss@41000000 {
  40. compatible = "ti,am654-r5fss";
  41. lockstep-mode = <0>;
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. ranges = <0x41000000 0x00 0x41000000 0x20000>,
  45. <0x41400000 0x00 0x41400000 0x20000>;
  46. power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
  47. mcu_r5fss0_core0: r5f@41000000 {
  48. compatible = "ti,am654-r5f";
  49. reg = <0x41000000 0x00008000>,
  50. <0x41010000 0x00008000>;
  51. reg-names = "atcm", "btcm";
  52. ti,sci = <&dmsc>;
  53. ti,sci-dev-id = <159>;
  54. ti,sci-proc-ids = <0x01 0xFF>;
  55. resets = <&k3_reset 159 1>;
  56. atcm-enable = <1>;
  57. btcm-enable = <1>;
  58. loczrama = <1>;
  59. };
  60. mcu_r5fss0_core1: r5f@41400000 {
  61. compatible = "ti,am654-r5f";
  62. reg = <0x41400000 0x00008000>,
  63. <0x41410000 0x00008000>;
  64. reg-names = "atcm", "btcm";
  65. ti,sci = <&dmsc>;
  66. ti,sci-dev-id = <245>;
  67. ti,sci-proc-ids = <0x02 0xFF>;
  68. resets = <&k3_reset 245 1>;
  69. atcm-enable = <1>;
  70. btcm-enable = <1>;
  71. loczrama = <1>;
  72. };
  73. };
  74. fss: fss@47000000 {
  75. compatible = "simple-bus";
  76. #address-cells = <2>;
  77. #size-cells = <2>;
  78. ranges;
  79. ospi0: spi@47040000 {
  80. compatible = "ti,am654-ospi", "cdns,qspi-nor";
  81. reg = <0x0 0x47040000 0x0 0x100>,
  82. <0x5 0x00000000 0x1 0x0000000>;
  83. interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>;
  84. cdns,fifo-depth = <256>;
  85. cdns,fifo-width = <4>;
  86. cdns,trigger-address = <0x0>;
  87. clocks = <&k3_clks 248 0>;
  88. assigned-clocks = <&k3_clks 248 0>;
  89. assigned-clock-parents = <&k3_clks 248 2>;
  90. assigned-clock-rates = <166666666>;
  91. power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>;
  92. #address-cells = <1>;
  93. #size-cells = <0>;
  94. };
  95. ospi1: spi@47050000 {
  96. compatible = "ti,am654-ospi", "cdns,qspi-nor";
  97. reg = <0x0 0x47050000 0x0 0x100>,
  98. <0x7 0x00000000 0x1 0x00000000>;
  99. interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>;
  100. cdns,fifo-depth = <256>;
  101. cdns,fifo-width = <4>;
  102. cdns,trigger-address = <0x0>;
  103. clocks = <&k3_clks 249 6>;
  104. power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
  105. #address-cells = <1>;
  106. #size-cells = <0>;
  107. };
  108. };
  109. mcu_navss {
  110. compatible = "simple-mfd";
  111. #address-cells = <2>;
  112. #size-cells = <2>;
  113. ranges;
  114. dma-coherent;
  115. dma-ranges;
  116. ti,sci-dev-id = <119>;
  117. mcu_ringacc: ringacc@2b800000 {
  118. compatible = "ti,am654-navss-ringacc";
  119. reg = <0x0 0x2b800000 0x0 0x400000>,
  120. <0x0 0x2b000000 0x0 0x400000>,
  121. <0x0 0x28590000 0x0 0x100>,
  122. <0x0 0x2a500000 0x0 0x40000>;
  123. reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
  124. ti,num-rings = <286>;
  125. ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
  126. ti,dma-ring-reset-quirk;
  127. ti,sci = <&dmsc>;
  128. ti,sci-dev-id = <195>;
  129. };
  130. mcu_udmap: dma-controller@285c0000 {
  131. compatible = "ti,am654-navss-mcu-udmap";
  132. reg = <0x0 0x285c0000 0x0 0x100>,
  133. <0x0 0x2a800000 0x0 0x40000>,
  134. <0x0 0x2aa00000 0x0 0x40000>;
  135. reg-names = "gcfg", "rchanrt", "tchanrt";
  136. #dma-cells = <1>;
  137. ti,sci = <&dmsc>;
  138. ti,sci-dev-id = <194>;
  139. ti,ringacc = <&mcu_ringacc>;
  140. ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
  141. <0x2>; /* TX_CHAN */
  142. ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */
  143. <0x4>; /* RX_CHAN */
  144. ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */
  145. };
  146. };
  147. mcu_cpsw: ethernet@46000000 {
  148. compatible = "ti,am654-cpsw-nuss";
  149. #address-cells = <2>;
  150. #size-cells = <2>;
  151. reg = <0x0 0x46000000 0x0 0x200000>;
  152. reg-names = "cpsw_nuss";
  153. ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
  154. dma-coherent;
  155. clocks = <&k3_clks 5 10>;
  156. clock-names = "fck";
  157. power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
  158. dmas = <&mcu_udmap 0xf000>,
  159. <&mcu_udmap 0xf001>,
  160. <&mcu_udmap 0xf002>,
  161. <&mcu_udmap 0xf003>,
  162. <&mcu_udmap 0xf004>,
  163. <&mcu_udmap 0xf005>,
  164. <&mcu_udmap 0xf006>,
  165. <&mcu_udmap 0xf007>,
  166. <&mcu_udmap 0x7000>;
  167. dma-names = "tx0", "tx1", "tx2", "tx3",
  168. "tx4", "tx5", "tx6", "tx7",
  169. "rx";
  170. ethernet-ports {
  171. #address-cells = <1>;
  172. #size-cells = <0>;
  173. cpsw_port1: port@1 {
  174. reg = <1>;
  175. ti,mac-only;
  176. label = "port1";
  177. ti,syscon-efuse = <&mcu_conf 0x200>;
  178. phys = <&phy_gmii_sel 1>;
  179. };
  180. };
  181. davinci_mdio: mdio@f00 {
  182. compatible = "ti,cpsw-mdio","ti,davinci_mdio";
  183. reg = <0x0 0xf00 0x0 0x100>;
  184. #address-cells = <1>;
  185. #size-cells = <0>;
  186. clocks = <&k3_clks 5 10>;
  187. clock-names = "fck";
  188. bus_freq = <1000000>;
  189. };
  190. cpts@3d000 {
  191. compatible = "ti,am65-cpts";
  192. reg = <0x0 0x3d000 0x0 0x400>;
  193. clocks = <&mcu_cpsw_cpts_mux>;
  194. clock-names = "cpts";
  195. interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
  196. interrupt-names = "cpts";
  197. ti,cpts-ext-ts-inputs = <4>;
  198. ti,cpts-periodic-outputs = <2>;
  199. mcu_cpsw_cpts_mux: refclk-mux {
  200. #clock-cells = <0>;
  201. clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
  202. <&k3_clks 118 6>, <&k3_clks 118 3>,
  203. <&k3_clks 118 8>, <&k3_clks 118 14>,
  204. <&k3_clks 120 3>, <&k3_clks 121 3>;
  205. assigned-clocks = <&mcu_cpsw_cpts_mux>;
  206. assigned-clock-parents = <&k3_clks 118 5>;
  207. };
  208. };
  209. };
  210. };