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- /* SPDX-License-Identifier: GPL-2.0 */
- /*
- * Xilinx Zynq MPSoC Firmware driver
- *
- * Copyright (C) 2018-2019 Xilinx, Inc.
- */
- #ifndef _ZYNQMP_FIRMWARE_H_
- #define _ZYNQMP_FIRMWARE_H_
- enum pm_api_id {
- PM_GET_API_VERSION = 1,
- PM_SET_CONFIGURATION = 2,
- PM_GET_NODE_STATUS = 3,
- PM_GET_OPERATING_CHARACTERISTIC = 4,
- PM_REGISTER_NOTIFIER = 5,
- /* API for suspending */
- PM_REQUEST_SUSPEND = 6,
- PM_SELF_SUSPEND = 7,
- PM_FORCE_POWERDOWN = 8,
- PM_ABORT_SUSPEND = 9,
- PM_REQUEST_WAKEUP = 10,
- PM_SET_WAKEUP_SOURCE = 11,
- PM_SYSTEM_SHUTDOWN = 12,
- PM_REQUEST_NODE = 13,
- PM_RELEASE_NODE = 14,
- PM_SET_REQUIREMENT = 15,
- PM_SET_MAX_LATENCY = 16,
- /* Direct control API functions: */
- PM_RESET_ASSERT = 17,
- PM_RESET_GET_STATUS = 18,
- PM_MMIO_WRITE = 19,
- PM_MMIO_READ = 20,
- PM_PM_INIT_FINALIZE = 21,
- PM_FPGA_LOAD = 22,
- PM_FPGA_GET_STATUS = 23,
- PM_GET_CHIPID = 24,
- /* ID 25 is been used by U-boot to process secure boot images */
- /* Secure library generic API functions */
- PM_SECURE_SHA = 26,
- PM_SECURE_RSA = 27,
- PM_PINCTRL_REQUEST = 28,
- PM_PINCTRL_RELEASE = 29,
- PM_PINCTRL_GET_FUNCTION = 30,
- PM_PINCTRL_SET_FUNCTION = 31,
- PM_PINCTRL_CONFIG_PARAM_GET = 32,
- PM_PINCTRL_CONFIG_PARAM_SET = 33,
- PM_IOCTL = 34,
- PM_QUERY_DATA = 35,
- PM_CLOCK_ENABLE = 36,
- PM_CLOCK_DISABLE = 37,
- PM_CLOCK_GETSTATE = 38,
- PM_CLOCK_SETDIVIDER = 39,
- PM_CLOCK_GETDIVIDER = 40,
- PM_CLOCK_SETRATE = 41,
- PM_CLOCK_GETRATE = 42,
- PM_CLOCK_SETPARENT = 43,
- PM_CLOCK_GETPARENT = 44,
- PM_SECURE_IMAGE = 45,
- PM_FPGA_READ = 46,
- PM_SECURE_AES = 47,
- PM_CLOCK_PLL_GETPARAM = 49,
- /* PM_REGISTER_ACCESS API */
- PM_REGISTER_ACCESS = 52,
- PM_EFUSE_ACCESS = 53,
- PM_FEATURE_CHECK = 63,
- PM_API_MAX,
- };
- enum pm_query_id {
- PM_QID_INVALID = 0,
- PM_QID_CLOCK_GET_NAME = 1,
- PM_QID_CLOCK_GET_TOPOLOGY = 2,
- PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
- PM_QID_CLOCK_GET_PARENTS = 4,
- PM_QID_CLOCK_GET_ATTRIBUTES = 5,
- PM_QID_PINCTRL_GET_NUM_PINS = 6,
- PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
- PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
- PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
- PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
- PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
- PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
- PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
- };
- enum zynqmp_pm_reset_action {
- PM_RESET_ACTION_RELEASE = 0,
- PM_RESET_ACTION_ASSERT = 1,
- PM_RESET_ACTION_PULSE = 2,
- };
- enum zynqmp_pm_reset {
- ZYNQMP_PM_RESET_START = 1000,
- ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
- ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
- ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
- ZYNQMP_PM_RESET_DP = 1003,
- ZYNQMP_PM_RESET_SWDT_CRF = 1004,
- ZYNQMP_PM_RESET_AFI_FM5 = 1005,
- ZYNQMP_PM_RESET_AFI_FM4 = 1006,
- ZYNQMP_PM_RESET_AFI_FM3 = 1007,
- ZYNQMP_PM_RESET_AFI_FM2 = 1008,
- ZYNQMP_PM_RESET_AFI_FM1 = 1009,
- ZYNQMP_PM_RESET_AFI_FM0 = 1010,
- ZYNQMP_PM_RESET_GDMA = 1011,
- ZYNQMP_PM_RESET_GPU_PP1 = 1012,
- ZYNQMP_PM_RESET_GPU_PP0 = 1013,
- ZYNQMP_PM_RESET_GPU = 1014,
- ZYNQMP_PM_RESET_GT = 1015,
- ZYNQMP_PM_RESET_SATA = 1016,
- ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
- ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
- ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
- ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
- ZYNQMP_PM_RESET_APU_L2 = 1021,
- ZYNQMP_PM_RESET_ACPU3 = 1022,
- ZYNQMP_PM_RESET_ACPU2 = 1023,
- ZYNQMP_PM_RESET_ACPU1 = 1024,
- ZYNQMP_PM_RESET_ACPU0 = 1025,
- ZYNQMP_PM_RESET_DDR = 1026,
- ZYNQMP_PM_RESET_APM_FPD = 1027,
- ZYNQMP_PM_RESET_SOFT = 1028,
- ZYNQMP_PM_RESET_GEM0 = 1029,
- ZYNQMP_PM_RESET_GEM1 = 1030,
- ZYNQMP_PM_RESET_GEM2 = 1031,
- ZYNQMP_PM_RESET_GEM3 = 1032,
- ZYNQMP_PM_RESET_QSPI = 1033,
- ZYNQMP_PM_RESET_UART0 = 1034,
- ZYNQMP_PM_RESET_UART1 = 1035,
- ZYNQMP_PM_RESET_SPI0 = 1036,
- ZYNQMP_PM_RESET_SPI1 = 1037,
- ZYNQMP_PM_RESET_SDIO0 = 1038,
- ZYNQMP_PM_RESET_SDIO1 = 1039,
- ZYNQMP_PM_RESET_CAN0 = 1040,
- ZYNQMP_PM_RESET_CAN1 = 1041,
- ZYNQMP_PM_RESET_I2C0 = 1042,
- ZYNQMP_PM_RESET_I2C1 = 1043,
- ZYNQMP_PM_RESET_TTC0 = 1044,
- ZYNQMP_PM_RESET_TTC1 = 1045,
- ZYNQMP_PM_RESET_TTC2 = 1046,
- ZYNQMP_PM_RESET_TTC3 = 1047,
- ZYNQMP_PM_RESET_SWDT_CRL = 1048,
- ZYNQMP_PM_RESET_NAND = 1049,
- ZYNQMP_PM_RESET_ADMA = 1050,
- ZYNQMP_PM_RESET_GPIO = 1051,
- ZYNQMP_PM_RESET_IOU_CC = 1052,
- ZYNQMP_PM_RESET_TIMESTAMP = 1053,
- ZYNQMP_PM_RESET_RPU_R50 = 1054,
- ZYNQMP_PM_RESET_RPU_R51 = 1055,
- ZYNQMP_PM_RESET_RPU_AMBA = 1056,
- ZYNQMP_PM_RESET_OCM = 1057,
- ZYNQMP_PM_RESET_RPU_PGE = 1058,
- ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
- ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
- ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
- ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
- ZYNQMP_PM_RESET_USB0_APB = 1063,
- ZYNQMP_PM_RESET_USB1_APB = 1064,
- ZYNQMP_PM_RESET_IPI = 1065,
- ZYNQMP_PM_RESET_APM_LPD = 1066,
- ZYNQMP_PM_RESET_RTC = 1067,
- ZYNQMP_PM_RESET_SYSMON = 1068,
- ZYNQMP_PM_RESET_AFI_FM6 = 1069,
- ZYNQMP_PM_RESET_LPD_SWDT = 1070,
- ZYNQMP_PM_RESET_FPD = 1071,
- ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
- ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
- ZYNQMP_PM_RESET_DBG_LPD = 1074,
- ZYNQMP_PM_RESET_DBG_FPD = 1075,
- ZYNQMP_PM_RESET_APLL = 1076,
- ZYNQMP_PM_RESET_DPLL = 1077,
- ZYNQMP_PM_RESET_VPLL = 1078,
- ZYNQMP_PM_RESET_IOPLL = 1079,
- ZYNQMP_PM_RESET_RPLL = 1080,
- ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
- ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
- ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
- ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
- ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
- ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
- ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
- ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
- ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
- ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
- ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
- ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
- ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
- ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
- ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
- ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
- ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
- ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
- ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
- ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
- ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
- ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
- ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
- ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
- ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
- ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
- ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
- ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
- ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
- ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
- ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
- ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
- ZYNQMP_PM_RESET_RPU_LS = 1113,
- ZYNQMP_PM_RESET_PS_ONLY = 1114,
- ZYNQMP_PM_RESET_PL = 1115,
- ZYNQMP_PM_RESET_PS_PL0 = 1116,
- ZYNQMP_PM_RESET_PS_PL1 = 1117,
- ZYNQMP_PM_RESET_PS_PL2 = 1118,
- ZYNQMP_PM_RESET_PS_PL3 = 1119,
- ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
- };
- #define PM_SIP_SVC 0xc2000000
- #define ZYNQMP_PM_VERSION_MAJOR 1
- #define ZYNQMP_PM_VERSION_MINOR 0
- #define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
- #define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
- #define ZYNQMP_PM_VERSION \
- ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
- ZYNQMP_PM_VERSION_MINOR)
- #define ZYNQMP_PM_VERSION_INVALID ~0
- #define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
- /*
- * Return payload size
- * Not every firmware call expects the same amount of return bytes, however the
- * firmware driver always copies 5 bytes from RX buffer to the ret_payload
- * buffer. Therefore allocating with this defined value is recommended to avoid
- * overflows.
- */
- #define PAYLOAD_ARG_CNT 5U
- unsigned int zynqmp_firmware_version(void);
- void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
- int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
- u32 arg3, u32 *ret_payload);
- #endif /* _ZYNQMP_FIRMWARE_H_ */
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