zynqmp_firmware.h 7.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Xilinx Zynq MPSoC Firmware driver
  4. *
  5. * Copyright (C) 2018-2019 Xilinx, Inc.
  6. */
  7. #ifndef _ZYNQMP_FIRMWARE_H_
  8. #define _ZYNQMP_FIRMWARE_H_
  9. enum pm_api_id {
  10. PM_GET_API_VERSION = 1,
  11. PM_SET_CONFIGURATION = 2,
  12. PM_GET_NODE_STATUS = 3,
  13. PM_GET_OPERATING_CHARACTERISTIC = 4,
  14. PM_REGISTER_NOTIFIER = 5,
  15. /* API for suspending */
  16. PM_REQUEST_SUSPEND = 6,
  17. PM_SELF_SUSPEND = 7,
  18. PM_FORCE_POWERDOWN = 8,
  19. PM_ABORT_SUSPEND = 9,
  20. PM_REQUEST_WAKEUP = 10,
  21. PM_SET_WAKEUP_SOURCE = 11,
  22. PM_SYSTEM_SHUTDOWN = 12,
  23. PM_REQUEST_NODE = 13,
  24. PM_RELEASE_NODE = 14,
  25. PM_SET_REQUIREMENT = 15,
  26. PM_SET_MAX_LATENCY = 16,
  27. /* Direct control API functions: */
  28. PM_RESET_ASSERT = 17,
  29. PM_RESET_GET_STATUS = 18,
  30. PM_MMIO_WRITE = 19,
  31. PM_MMIO_READ = 20,
  32. PM_PM_INIT_FINALIZE = 21,
  33. PM_FPGA_LOAD = 22,
  34. PM_FPGA_GET_STATUS = 23,
  35. PM_GET_CHIPID = 24,
  36. /* ID 25 is been used by U-boot to process secure boot images */
  37. /* Secure library generic API functions */
  38. PM_SECURE_SHA = 26,
  39. PM_SECURE_RSA = 27,
  40. PM_PINCTRL_REQUEST = 28,
  41. PM_PINCTRL_RELEASE = 29,
  42. PM_PINCTRL_GET_FUNCTION = 30,
  43. PM_PINCTRL_SET_FUNCTION = 31,
  44. PM_PINCTRL_CONFIG_PARAM_GET = 32,
  45. PM_PINCTRL_CONFIG_PARAM_SET = 33,
  46. PM_IOCTL = 34,
  47. PM_QUERY_DATA = 35,
  48. PM_CLOCK_ENABLE = 36,
  49. PM_CLOCK_DISABLE = 37,
  50. PM_CLOCK_GETSTATE = 38,
  51. PM_CLOCK_SETDIVIDER = 39,
  52. PM_CLOCK_GETDIVIDER = 40,
  53. PM_CLOCK_SETRATE = 41,
  54. PM_CLOCK_GETRATE = 42,
  55. PM_CLOCK_SETPARENT = 43,
  56. PM_CLOCK_GETPARENT = 44,
  57. PM_SECURE_IMAGE = 45,
  58. PM_FPGA_READ = 46,
  59. PM_SECURE_AES = 47,
  60. PM_CLOCK_PLL_GETPARAM = 49,
  61. /* PM_REGISTER_ACCESS API */
  62. PM_REGISTER_ACCESS = 52,
  63. PM_EFUSE_ACCESS = 53,
  64. PM_FEATURE_CHECK = 63,
  65. PM_API_MAX,
  66. };
  67. enum pm_query_id {
  68. PM_QID_INVALID = 0,
  69. PM_QID_CLOCK_GET_NAME = 1,
  70. PM_QID_CLOCK_GET_TOPOLOGY = 2,
  71. PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3,
  72. PM_QID_CLOCK_GET_PARENTS = 4,
  73. PM_QID_CLOCK_GET_ATTRIBUTES = 5,
  74. PM_QID_PINCTRL_GET_NUM_PINS = 6,
  75. PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7,
  76. PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8,
  77. PM_QID_PINCTRL_GET_FUNCTION_NAME = 9,
  78. PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10,
  79. PM_QID_PINCTRL_GET_PIN_GROUPS = 11,
  80. PM_QID_CLOCK_GET_NUM_CLOCKS = 12,
  81. PM_QID_CLOCK_GET_MAX_DIVISOR = 13,
  82. };
  83. enum zynqmp_pm_reset_action {
  84. PM_RESET_ACTION_RELEASE = 0,
  85. PM_RESET_ACTION_ASSERT = 1,
  86. PM_RESET_ACTION_PULSE = 2,
  87. };
  88. enum zynqmp_pm_reset {
  89. ZYNQMP_PM_RESET_START = 1000,
  90. ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START,
  91. ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001,
  92. ZYNQMP_PM_RESET_PCIE_CTRL = 1002,
  93. ZYNQMP_PM_RESET_DP = 1003,
  94. ZYNQMP_PM_RESET_SWDT_CRF = 1004,
  95. ZYNQMP_PM_RESET_AFI_FM5 = 1005,
  96. ZYNQMP_PM_RESET_AFI_FM4 = 1006,
  97. ZYNQMP_PM_RESET_AFI_FM3 = 1007,
  98. ZYNQMP_PM_RESET_AFI_FM2 = 1008,
  99. ZYNQMP_PM_RESET_AFI_FM1 = 1009,
  100. ZYNQMP_PM_RESET_AFI_FM0 = 1010,
  101. ZYNQMP_PM_RESET_GDMA = 1011,
  102. ZYNQMP_PM_RESET_GPU_PP1 = 1012,
  103. ZYNQMP_PM_RESET_GPU_PP0 = 1013,
  104. ZYNQMP_PM_RESET_GPU = 1014,
  105. ZYNQMP_PM_RESET_GT = 1015,
  106. ZYNQMP_PM_RESET_SATA = 1016,
  107. ZYNQMP_PM_RESET_ACPU3_PWRON = 1017,
  108. ZYNQMP_PM_RESET_ACPU2_PWRON = 1018,
  109. ZYNQMP_PM_RESET_ACPU1_PWRON = 1019,
  110. ZYNQMP_PM_RESET_ACPU0_PWRON = 1020,
  111. ZYNQMP_PM_RESET_APU_L2 = 1021,
  112. ZYNQMP_PM_RESET_ACPU3 = 1022,
  113. ZYNQMP_PM_RESET_ACPU2 = 1023,
  114. ZYNQMP_PM_RESET_ACPU1 = 1024,
  115. ZYNQMP_PM_RESET_ACPU0 = 1025,
  116. ZYNQMP_PM_RESET_DDR = 1026,
  117. ZYNQMP_PM_RESET_APM_FPD = 1027,
  118. ZYNQMP_PM_RESET_SOFT = 1028,
  119. ZYNQMP_PM_RESET_GEM0 = 1029,
  120. ZYNQMP_PM_RESET_GEM1 = 1030,
  121. ZYNQMP_PM_RESET_GEM2 = 1031,
  122. ZYNQMP_PM_RESET_GEM3 = 1032,
  123. ZYNQMP_PM_RESET_QSPI = 1033,
  124. ZYNQMP_PM_RESET_UART0 = 1034,
  125. ZYNQMP_PM_RESET_UART1 = 1035,
  126. ZYNQMP_PM_RESET_SPI0 = 1036,
  127. ZYNQMP_PM_RESET_SPI1 = 1037,
  128. ZYNQMP_PM_RESET_SDIO0 = 1038,
  129. ZYNQMP_PM_RESET_SDIO1 = 1039,
  130. ZYNQMP_PM_RESET_CAN0 = 1040,
  131. ZYNQMP_PM_RESET_CAN1 = 1041,
  132. ZYNQMP_PM_RESET_I2C0 = 1042,
  133. ZYNQMP_PM_RESET_I2C1 = 1043,
  134. ZYNQMP_PM_RESET_TTC0 = 1044,
  135. ZYNQMP_PM_RESET_TTC1 = 1045,
  136. ZYNQMP_PM_RESET_TTC2 = 1046,
  137. ZYNQMP_PM_RESET_TTC3 = 1047,
  138. ZYNQMP_PM_RESET_SWDT_CRL = 1048,
  139. ZYNQMP_PM_RESET_NAND = 1049,
  140. ZYNQMP_PM_RESET_ADMA = 1050,
  141. ZYNQMP_PM_RESET_GPIO = 1051,
  142. ZYNQMP_PM_RESET_IOU_CC = 1052,
  143. ZYNQMP_PM_RESET_TIMESTAMP = 1053,
  144. ZYNQMP_PM_RESET_RPU_R50 = 1054,
  145. ZYNQMP_PM_RESET_RPU_R51 = 1055,
  146. ZYNQMP_PM_RESET_RPU_AMBA = 1056,
  147. ZYNQMP_PM_RESET_OCM = 1057,
  148. ZYNQMP_PM_RESET_RPU_PGE = 1058,
  149. ZYNQMP_PM_RESET_USB0_CORERESET = 1059,
  150. ZYNQMP_PM_RESET_USB1_CORERESET = 1060,
  151. ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061,
  152. ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062,
  153. ZYNQMP_PM_RESET_USB0_APB = 1063,
  154. ZYNQMP_PM_RESET_USB1_APB = 1064,
  155. ZYNQMP_PM_RESET_IPI = 1065,
  156. ZYNQMP_PM_RESET_APM_LPD = 1066,
  157. ZYNQMP_PM_RESET_RTC = 1067,
  158. ZYNQMP_PM_RESET_SYSMON = 1068,
  159. ZYNQMP_PM_RESET_AFI_FM6 = 1069,
  160. ZYNQMP_PM_RESET_LPD_SWDT = 1070,
  161. ZYNQMP_PM_RESET_FPD = 1071,
  162. ZYNQMP_PM_RESET_RPU_DBG1 = 1072,
  163. ZYNQMP_PM_RESET_RPU_DBG0 = 1073,
  164. ZYNQMP_PM_RESET_DBG_LPD = 1074,
  165. ZYNQMP_PM_RESET_DBG_FPD = 1075,
  166. ZYNQMP_PM_RESET_APLL = 1076,
  167. ZYNQMP_PM_RESET_DPLL = 1077,
  168. ZYNQMP_PM_RESET_VPLL = 1078,
  169. ZYNQMP_PM_RESET_IOPLL = 1079,
  170. ZYNQMP_PM_RESET_RPLL = 1080,
  171. ZYNQMP_PM_RESET_GPO3_PL_0 = 1081,
  172. ZYNQMP_PM_RESET_GPO3_PL_1 = 1082,
  173. ZYNQMP_PM_RESET_GPO3_PL_2 = 1083,
  174. ZYNQMP_PM_RESET_GPO3_PL_3 = 1084,
  175. ZYNQMP_PM_RESET_GPO3_PL_4 = 1085,
  176. ZYNQMP_PM_RESET_GPO3_PL_5 = 1086,
  177. ZYNQMP_PM_RESET_GPO3_PL_6 = 1087,
  178. ZYNQMP_PM_RESET_GPO3_PL_7 = 1088,
  179. ZYNQMP_PM_RESET_GPO3_PL_8 = 1089,
  180. ZYNQMP_PM_RESET_GPO3_PL_9 = 1090,
  181. ZYNQMP_PM_RESET_GPO3_PL_10 = 1091,
  182. ZYNQMP_PM_RESET_GPO3_PL_11 = 1092,
  183. ZYNQMP_PM_RESET_GPO3_PL_12 = 1093,
  184. ZYNQMP_PM_RESET_GPO3_PL_13 = 1094,
  185. ZYNQMP_PM_RESET_GPO3_PL_14 = 1095,
  186. ZYNQMP_PM_RESET_GPO3_PL_15 = 1096,
  187. ZYNQMP_PM_RESET_GPO3_PL_16 = 1097,
  188. ZYNQMP_PM_RESET_GPO3_PL_17 = 1098,
  189. ZYNQMP_PM_RESET_GPO3_PL_18 = 1099,
  190. ZYNQMP_PM_RESET_GPO3_PL_19 = 1100,
  191. ZYNQMP_PM_RESET_GPO3_PL_20 = 1101,
  192. ZYNQMP_PM_RESET_GPO3_PL_21 = 1102,
  193. ZYNQMP_PM_RESET_GPO3_PL_22 = 1103,
  194. ZYNQMP_PM_RESET_GPO3_PL_23 = 1104,
  195. ZYNQMP_PM_RESET_GPO3_PL_24 = 1105,
  196. ZYNQMP_PM_RESET_GPO3_PL_25 = 1106,
  197. ZYNQMP_PM_RESET_GPO3_PL_26 = 1107,
  198. ZYNQMP_PM_RESET_GPO3_PL_27 = 1108,
  199. ZYNQMP_PM_RESET_GPO3_PL_28 = 1109,
  200. ZYNQMP_PM_RESET_GPO3_PL_29 = 1110,
  201. ZYNQMP_PM_RESET_GPO3_PL_30 = 1111,
  202. ZYNQMP_PM_RESET_GPO3_PL_31 = 1112,
  203. ZYNQMP_PM_RESET_RPU_LS = 1113,
  204. ZYNQMP_PM_RESET_PS_ONLY = 1114,
  205. ZYNQMP_PM_RESET_PL = 1115,
  206. ZYNQMP_PM_RESET_PS_PL0 = 1116,
  207. ZYNQMP_PM_RESET_PS_PL1 = 1117,
  208. ZYNQMP_PM_RESET_PS_PL2 = 1118,
  209. ZYNQMP_PM_RESET_PS_PL3 = 1119,
  210. ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3
  211. };
  212. #define PM_SIP_SVC 0xc2000000
  213. #define ZYNQMP_PM_VERSION_MAJOR 1
  214. #define ZYNQMP_PM_VERSION_MINOR 0
  215. #define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
  216. #define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
  217. #define ZYNQMP_PM_VERSION \
  218. ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
  219. ZYNQMP_PM_VERSION_MINOR)
  220. #define ZYNQMP_PM_VERSION_INVALID ~0
  221. #define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
  222. /*
  223. * Return payload size
  224. * Not every firmware call expects the same amount of return bytes, however the
  225. * firmware driver always copies 5 bytes from RX buffer to the ret_payload
  226. * buffer. Therefore allocating with this defined value is recommended to avoid
  227. * overflows.
  228. */
  229. #define PAYLOAD_ARG_CNT 5U
  230. unsigned int zynqmp_firmware_version(void);
  231. void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
  232. int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
  233. u32 arg3, u32 *ret_payload);
  234. #endif /* _ZYNQMP_FIRMWARE_H_ */