innokom.h 15 KB

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  1. /*
  2. * (C) Copyright 2000, 2001, 2002
  3. * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
  4. *
  5. * Configuration for the Auerswald Innokom CPU board.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. /*
  26. * include/configs/innokom.h - configuration options, board specific
  27. */
  28. #ifndef __CONFIG_H
  29. #define __CONFIG_H
  30. #define DEBUG 1
  31. /*
  32. * If we are developing, we might want to start U-Boot from ram
  33. * so we MUST NOT initialize critical regs like mem-timing ...
  34. */
  35. #define CONFIG_INIT_CRITICAL /* undef for developing */
  36. /*
  37. * High Level Configuration Options
  38. * (easy to change)
  39. */
  40. #define CONFIG_PXA250 1 /* This is an PXA250 CPU */
  41. #define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */
  42. #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
  43. /* for timer/console/ethernet */
  44. /*
  45. * Hardware drivers
  46. */
  47. /*
  48. * select serial console configuration
  49. */
  50. #define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
  51. /* allow to overwrite serial and ethaddr */
  52. #define CONFIG_ENV_OVERWRITE
  53. #define CONFIG_BAUDRATE 19200
  54. #define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */
  55. #define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_I2C|CFG_CMD_DHCP)
  56. /* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */
  57. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  58. #include <cmd_confdefs.h>
  59. #define CONFIG_BOOTDELAY 3
  60. /* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
  61. #define CONFIG_BOOTARGS "console=ttyS0,19200"
  62. #define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
  63. #define CONFIG_NETMASK 255.255.255.0
  64. #define CONFIG_IPADDR 192.168.1.56
  65. #define CONFIG_SERVERIP 192.168.1.2
  66. #define CONFIG_BOOTCOMMAND "bootm 0x40000"
  67. #define CONFIG_SHOW_BOOT_PROGRESS
  68. #define CONFIG_CMDLINE_TAG 1
  69. /*
  70. * Miscellaneous configurable options
  71. */
  72. /*
  73. * Size of malloc() pool; this lives below the uppermost 128 KiB which are
  74. * used for the RAM copy of the uboot code
  75. *
  76. */
  77. #define CFG_MALLOC_LEN (256*1024)
  78. #define CFG_LONGHELP /* undef to save memory */
  79. #define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
  80. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  81. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  82. #define CFG_MAXARGS 16 /* max number of command args */
  83. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  84. #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
  85. #define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
  86. #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
  87. #define CFG_LOAD_ADDR 0xa3000000 /* load kernel to this address */
  88. #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
  89. /* RS: the oscillator is actually 3680130?? */
  90. #define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
  91. /* 0101000001 */
  92. /* ^^^^^ Memory Speed 99.53 MHz */
  93. /* ^^ Run Mode Speed = 2x Mem Speed */
  94. /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
  95. #define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
  96. /* valid baudrates */
  97. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  98. /*
  99. * I2C bus
  100. */
  101. #define CONFIG_HARD_I2C 1
  102. #define CFG_I2C_SPEED 50000
  103. #define CFG_I2C_SLAVE 0xfe
  104. #define CFG_ENV_IS_IN_EEPROM 1
  105. #define CFG_ENV_OFFSET 0x00 /* environment starts here */
  106. #define CFG_ENV_SIZE 1024 /* 1 KiB */
  107. #define CFG_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */
  108. #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
  109. #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 15 /* between stop and start */
  110. #define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of address */
  111. #define CFG_EEPROM_SIZE 4096 /* size in bytes */
  112. #define CFG_I2C_INIT_BOARD 1 /* board has it's own init */
  113. /*
  114. * SMSC91C111 Network Card
  115. */
  116. #define CONFIG_DRIVER_SMC91111 1
  117. #define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */
  118. #undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */
  119. #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */
  120. #undef CONFIG_SHOW_ACTIVITY
  121. #define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
  122. /*
  123. * Stack sizes
  124. *
  125. * The stack sizes are set up in start.S using the settings below
  126. */
  127. #define CONFIG_STACKSIZE (128*1024) /* regular stack */
  128. #ifdef CONFIG_USE_IRQ
  129. #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
  130. #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
  131. #endif
  132. /*
  133. * Physical Memory Map
  134. */
  135. #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
  136. #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
  137. #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
  138. #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
  139. #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
  140. #define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */
  141. #define CFG_DRAM_SIZE 0x04000000
  142. #define CFG_FLASH_BASE PHYS_FLASH_1
  143. /*
  144. * JFFS2 Partitions
  145. */
  146. #define CFG_JFFS_CUSTOM_PART 1 /* see board/innokom/flash.c */
  147. #define CONFIG_MTD_INNOKOM_16MB 1 /* development flash */
  148. #undef CONFIG_MTD_INNOKOM_64MB /* production flash */
  149. /*
  150. * GPIO settings
  151. *
  152. * GP15 == nCS1 is 1
  153. * GP24 == SFRM is 1
  154. * GP25 == TXD is 1
  155. * GP33 == nCS5 is 1
  156. * GP39 == FFTXD is 1
  157. * GP41 == RTS is 1
  158. * GP47 == TXD is 1
  159. * GP49 == nPWE is 1
  160. * GP62 == LED_B is 1
  161. * GP63 == TDM_OE is 1
  162. * GP78 == nCS2 is 1
  163. * GP79 == nCS3 is 1
  164. * GP80 == nCS4 is 1
  165. */
  166. #define CFG_GPSR0_VAL 0x03008000
  167. #define CFG_GPSR1_VAL 0xC0028282
  168. #define CFG_GPSR2_VAL 0x0001C000
  169. /* GP02 == DON_RST is 0
  170. * GP23 == SCLK is 0
  171. * GP45 == USB_ACT is 0
  172. * GP60 == PLLEN is 0
  173. * GP61 == LED_A is 0
  174. * GP73 == SWUPD_LED is 0
  175. */
  176. #define CFG_GPCR0_VAL 0x00800004
  177. #define CFG_GPCR1_VAL 0x30002000
  178. #define CFG_GPCR2_VAL 0x00000100
  179. /* GP00 == DON_READY is input
  180. * GP01 == DON_OK is input
  181. * GP02 == DON_RST is output
  182. * GP03 == RESET_IND is input
  183. * GP07 == RES11 is input
  184. * GP09 == RES12 is input
  185. * GP11 == SWUPDATE is input
  186. * GP14 == nPOWEROK is input
  187. * GP15 == nCS1 is output
  188. * GP17 == RES22 is input
  189. * GP18 == RDY is input
  190. * GP23 == SCLK is output
  191. * GP24 == SFRM is output
  192. * GP25 == TXD is output
  193. * GP26 == RXD is input
  194. * GP32 == RES21 is input
  195. * GP33 == nCS5 is output
  196. * GP34 == FFRXD is input
  197. * GP35 == CTS is input
  198. * GP39 == FFTXD is output
  199. * GP41 == RTS is output
  200. * GP42 == USB_OK is input
  201. * GP45 == USB_ACT is output
  202. * GP46 == RXD is input
  203. * GP47 == TXD is output
  204. * GP49 == nPWE is output
  205. * GP58 == nCPUBUSINT is input
  206. * GP59 == LANINT is input
  207. * GP60 == PLLEN is output
  208. * GP61 == LED_A is output
  209. * GP62 == LED_B is output
  210. * GP63 == TDM_OE is output
  211. * GP64 == nDSPINT is input
  212. * GP65 == STRAP0 is input
  213. * GP67 == STRAP1 is input
  214. * GP69 == STRAP2 is input
  215. * GP70 == STRAP3 is input
  216. * GP71 == STRAP4 is input
  217. * GP73 == SWUPD_LED is output
  218. * GP78 == nCS2 is output
  219. * GP79 == nCS3 is output
  220. * GP80 == nCS4 is output
  221. */
  222. #define CFG_GPDR0_VAL 0x03808004
  223. #define CFG_GPDR1_VAL 0xF002A282
  224. #define CFG_GPDR2_VAL 0x0001C200
  225. /* GP15 == nCS1 is AF10
  226. * GP18 == RDY is AF01
  227. * GP23 == SCLK is AF10
  228. * GP24 == SFRM is AF10
  229. * GP25 == TXD is AF10
  230. * GP26 == RXD is AF01
  231. * GP33 == nCS5 is AF10
  232. * GP34 == FFRXD is AF01
  233. * GP35 == CTS is AF01
  234. * GP39 == FFTXD is AF10
  235. * GP41 == RTS is AF10
  236. * GP46 == RXD is AF10
  237. * GP47 == TXD is AF01
  238. * GP49 == nPWE is AF10
  239. * GP78 == nCS2 is AF10
  240. * GP79 == nCS3 is AF10
  241. * GP80 == nCS4 is AF10
  242. */
  243. #define CFG_GAFR0_L_VAL 0x80000000
  244. #define CFG_GAFR0_U_VAL 0x001A8010
  245. #define CFG_GAFR1_L_VAL 0x60088058
  246. #define CFG_GAFR1_U_VAL 0x00000008
  247. #define CFG_GAFR2_L_VAL 0xA0000000
  248. #define CFG_GAFR2_U_VAL 0x00000002
  249. /* FIXME: set GPIO_RER/FER */
  250. /* RDH = 1
  251. * PH = 1
  252. * VFS = 1
  253. * BFS = 1
  254. * SSS = 1
  255. */
  256. #define CFG_PSSR_VAL 0x37
  257. /*
  258. * Memory settings
  259. *
  260. * This is the configuration for nCS0/1 -> flash banks
  261. * configuration for nCS1:
  262. * [31] 0 - Slower Device
  263. * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
  264. * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
  265. * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
  266. * [19] 1 - 16 Bit bus width
  267. * [18:16] 000 - nonburst RAM or FLASH
  268. * configuration for nCS0:
  269. * [15] 0 - Slower Device
  270. * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
  271. * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
  272. * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
  273. * [03] 1 - 16 Bit bus width
  274. * [02:00] 000 - nonburst RAM or FLASH
  275. */
  276. #define CFG_MSC0_VAL 0x25b825b8 /* flash banks */
  277. /* This is the configuration for nCS2/3 -> TDM-Switch, DSP
  278. * configuration for nCS3: DSP
  279. * [31] 0 - Slower Device
  280. * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
  281. * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
  282. * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
  283. * [19] 1 - 16 Bit bus width
  284. * [18:16] 100 - variable latency I/O
  285. * configuration for nCS2: TDM-Switch
  286. * [15] 0 - Slower Device
  287. * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
  288. * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
  289. * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
  290. * [03] 1 - 16 Bit bus width
  291. * [02:00] 100 - variable latency I/O
  292. */
  293. #define CFG_MSC1_VAL 0x123C593C /* TDM switch, DSP */
  294. /* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
  295. *
  296. * configuration for nCS5: LAN Controller
  297. * [31] 0 - Slower Device
  298. * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
  299. * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
  300. * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
  301. * [19] 1 - 16 Bit bus width
  302. * [18:16] 100 - variable latency I/O
  303. * configuration for nCS4: ExtBus
  304. * [15] 0 - Slower Device
  305. * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
  306. * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
  307. * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
  308. * [03] 1 - 16 Bit bus width
  309. * [02:00] 100 - variable latency I/O
  310. */
  311. #define CFG_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */
  312. /* MDCNFG: SDRAM Configuration Register
  313. *
  314. * [31:29] 000 - reserved
  315. * [28] 0 - no SA1111 compatiblity mode
  316. * [27] 0 - latch return data with return clock
  317. * [26] 0 - alternate addressing for pair 2/3
  318. * [25:24] 00 - timings
  319. * [23] 0 - internal banks in lower partition 2/3 (not used)
  320. * [22:21] 00 - row address bits for partition 2/3 (not used)
  321. * [20:19] 00 - column address bits for partition 2/3 (not used)
  322. * [18] 0 - SDRAM partition 2/3 width is 32 bit
  323. * [17] 0 - SDRAM partition 3 disabled
  324. * [16] 0 - SDRAM partition 2 disabled
  325. * [15:13] 000 - reserved
  326. * [12] 1 - SA1111 compatiblity mode
  327. * [11] 1 - latch return data with return clock
  328. * [10] 0 - no alternate addressing for pair 0/1
  329. * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
  330. * [7] 1 - 4 internal banks in lower partition pair
  331. * [06:05] 10 - 13 row address bits for partition 0/1
  332. * [04:03] 01 - 9 column address bits for partition 0/1
  333. * [02] 0 - SDRAM partition 0/1 width is 32 bit
  334. * [01] 0 - disable SDRAM partition 1
  335. * [00] 1 - enable SDRAM partition 0
  336. */
  337. /* use the configuration above but disable partition 0 */
  338. #define CFG_MDCNFG_VAL 0x000019c8
  339. /* MDREFR: SDRAM Refresh Control Register
  340. *
  341. * [32:26] 0 - reserved
  342. * [25] 0 - K2FREE: not free running
  343. * [24] 0 - K1FREE: not free running
  344. * [23] 1 - K0FREE: not free running
  345. * [22] 0 - SLFRSH: self refresh disabled
  346. * [21] 0 - reserved
  347. * [20] 0 - APD: no auto power down
  348. * [19] 0 - K2DB2: SDCLK2 is MemClk
  349. * [18] 0 - K2RUN: disable SDCLK2
  350. * [17] 0 - K1DB2: SDCLK1 is MemClk
  351. * [16] 1 - K1RUN: enable SDCLK1
  352. * [15] 1 - E1PIN: SDRAM clock enable
  353. * [14] 1 - K0DB2: SDCLK0 is MemClk
  354. * [13] 0 - K0RUN: disable SDCLK0
  355. * [12] 1 - E0PIN: disable SDCKE0
  356. * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
  357. */
  358. #define CFG_MDREFR_VAL 0x0081D018
  359. /* MDMRS: Mode Register Set Configuration Register
  360. *
  361. * [31] 0 - reserved
  362. * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
  363. * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
  364. * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
  365. * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
  366. * [15] 0 - reserved
  367. * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
  368. * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
  369. * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
  370. * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
  371. */
  372. #define CFG_MDMRS_VAL 0x00020022
  373. /*
  374. * PCMCIA and CF Interfaces
  375. */
  376. #define CFG_MECR_VAL 0x00000000
  377. #define CFG_MCMEM0_VAL 0x00000000
  378. #define CFG_MCMEM1_VAL 0x00000000
  379. #define CFG_MCATT0_VAL 0x00000000
  380. #define CFG_MCATT1_VAL 0x00000000
  381. #define CFG_MCIO0_VAL 0x00000000
  382. #define CFG_MCIO1_VAL 0x00000000
  383. /*
  384. #define CSB226_USER_LED0 0x00000008
  385. #define CSB226_USER_LED1 0x00000010
  386. #define CSB226_USER_LED2 0x00000020
  387. */
  388. /*
  389. * FLASH and environment organization
  390. */
  391. #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  392. #define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
  393. /* timeout values are in ticks */
  394. #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
  395. #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
  396. #endif /* __CONFIG_H */