flash.c 7.9 KB

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  1. /*
  2. * Copyright (C) 2003 ETC s.r.o.
  3. *
  4. * This code was inspired by Marius Groeger and Kyle Harris code
  5. * available in other board ports for U-Boot
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. *
  25. * Written by Peter Figuli <peposh@etc.sk>, 2003.
  26. *
  27. */
  28. #include <common.h>
  29. #include "intel.h"
  30. /*
  31. * This code should handle CFI FLASH memory device. This code is very
  32. * minimalistic approach without many essential error handling code as well.
  33. * Because U-Boot actually is missing smart handling of FLASH device,
  34. * we just set flash_id to anything else to FLASH_UNKNOW, so common code
  35. * can call us without any restrictions.
  36. * TODO: Add CFI Query, to be able to determine FLASH device.
  37. * TODO: Add error handling code
  38. * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but
  39. * hopefully may work with other configurations.
  40. */
  41. #if ( WEP_FLASH_BUS_WIDTH == 1 )
  42. # define FLASH_BUS vu_char
  43. # if ( WEP_FLASH_INTERLEAVE == 1 )
  44. # define FLASH_CMD( x ) x
  45. # else
  46. # error "With 8bit bus only one chip is allowed"
  47. # endif
  48. #elif ( WEP_FLASH_BUS_WIDTH == 2 )
  49. # define FLASH_BUS vu_short
  50. # if ( WEP_FLASH_INTERLEAVE == 1 )
  51. # define FLASH_CMD( x ) x
  52. # elif ( WEP_FLASH_INTERLEAVE == 2 )
  53. # define FLASH_CMD( x ) (( x << 8 )| x )
  54. # else
  55. # error "With 16bit bus only 1 or 2 chip(s) are allowed"
  56. # endif
  57. #elif ( WEP_FLASH_BUS_WIDTH == 4 )
  58. # define FLASH_BUS vu_long
  59. # if ( WEP_FLASH_INTERLEAVE == 1 )
  60. # define FLASH_CMD( x ) x
  61. # elif ( WEP_FLASH_INTERLEAVE == 2 )
  62. # define FLASH_CMD( x ) (( x << 16 )| x )
  63. # elif ( WEP_FLASH_INTERLEAVE == 4 )
  64. # define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x )
  65. # else
  66. # error "With 32bit bus only 1,2 or 4 chip(s) are allowed"
  67. # endif
  68. #else
  69. # error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration"
  70. #endif
  71. flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
  72. static FLASH_BUS flash_status_reg (void)
  73. {
  74. FLASH_BUS *addr = (FLASH_BUS *) 0;
  75. *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
  76. return *addr;
  77. }
  78. static int flash_ready (ulong timeout)
  79. {
  80. int ok = 1;
  81. reset_timer_masked ();
  82. while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
  83. FLASH_CMD (CFI_INTEL_SR_READY)) {
  84. if (get_timer_masked () > timeout && timeout != 0) {
  85. ok = 0;
  86. break;
  87. }
  88. }
  89. return ok;
  90. }
  91. #if ( CFG_MAX_FLASH_BANKS != 1 )
  92. # error "WEP platform has only one flash bank!"
  93. #endif
  94. ulong flash_init (void)
  95. {
  96. int i;
  97. FLASH_BUS address = WEP_FLASH_BASE;
  98. flash_info[0].size = WEP_FLASH_BANK_SIZE;
  99. flash_info[0].sector_count = CFG_MAX_FLASH_SECT;
  100. flash_info[0].flash_id = INTEL_MANUFACT;
  101. memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT);
  102. for (i = 0; i < CFG_MAX_FLASH_SECT; i++) {
  103. flash_info[0].start[i] = address;
  104. #ifdef WEP_FLASH_UNLOCK
  105. /* Some devices are hw locked after start. */
  106. *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP);
  107. *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK);
  108. flash_ready (0);
  109. *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
  110. #endif
  111. address += WEP_FLASH_SECT_SIZE;
  112. }
  113. flash_protect (FLAG_PROTECT_SET,
  114. CFG_FLASH_BASE,
  115. CFG_FLASH_BASE + _armboot_end_data - _armboot_start,
  116. &flash_info[0]);
  117. flash_protect (FLAG_PROTECT_SET,
  118. CFG_ENV_ADDR,
  119. CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
  120. return WEP_FLASH_BANK_SIZE;
  121. }
  122. void flash_print_info (flash_info_t * info)
  123. {
  124. int i;
  125. printf (" Intel vendor\n");
  126. printf (" Size: %ld MB in %d Sectors\n",
  127. info->size >> 20, info->sector_count);
  128. printf (" Sector Start Addresses:");
  129. for (i = 0; i < info->sector_count; i++) {
  130. if (!(i % 5)) {
  131. printf ("\n");
  132. }
  133. printf (" %08lX%s", info->start[i],
  134. info->protect[i] ? " (RO)" : " ");
  135. }
  136. printf ("\n");
  137. }
  138. int flash_erase (flash_info_t * info, int s_first, int s_last)
  139. {
  140. int flag, non_protected = 0, sector;
  141. int rc = ERR_OK;
  142. FLASH_BUS *address;
  143. for (sector = s_first; sector <= s_last; sector++) {
  144. if (!info->protect[sector]) {
  145. non_protected++;
  146. }
  147. }
  148. if (!non_protected) {
  149. return ERR_PROTECTED;
  150. }
  151. /*
  152. * Disable interrupts which might cause a timeout
  153. * here. Remember that our exception vectors are
  154. * at address 0 in the flash, and we don't want a
  155. * (ticker) exception to happen while the flash
  156. * chip is in programming mode.
  157. */
  158. flag = disable_interrupts ();
  159. /* Start erase on unprotected sectors */
  160. for (sector = s_first; sector <= s_last && !ctrlc (); sector++) {
  161. if (info->protect[sector]) {
  162. printf ("Protected sector %2d skipping...\n", sector);
  163. continue;
  164. } else {
  165. printf ("Erasing sector %2d ... ", sector);
  166. }
  167. address = (FLASH_BUS *) (info->start[sector]);
  168. *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
  169. *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
  170. if (flash_ready (CFG_FLASH_ERASE_TOUT)) {
  171. *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
  172. printf ("ok.\n");
  173. } else {
  174. *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
  175. rc = ERR_TIMOUT;
  176. printf ("timeout! Aborting...\n");
  177. break;
  178. }
  179. *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
  180. }
  181. if (ctrlc ())
  182. printf ("User Interrupt!\n");
  183. /* allow flash to settle - wait 10 ms */
  184. udelay_masked (10000);
  185. if (flag) {
  186. enable_interrupts ();
  187. }
  188. return rc;
  189. }
  190. static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data)
  191. {
  192. FLASH_BUS *address = (FLASH_BUS *) dest;
  193. int rc = ERR_OK;
  194. int flag;
  195. /* Check if Flash is (sufficiently) erased */
  196. if ((*address & data) != data) {
  197. return ERR_NOT_ERASED;
  198. }
  199. /*
  200. * Disable interrupts which might cause a timeout
  201. * here. Remember that our exception vectors are
  202. * at address 0 in the flash, and we don't want a
  203. * (ticker) exception to happen while the flash
  204. * chip is in programming mode.
  205. */
  206. flag = disable_interrupts ();
  207. *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
  208. *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
  209. *address = data;
  210. if (!flash_ready (CFG_FLASH_WRITE_TOUT)) {
  211. *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
  212. rc = ERR_TIMOUT;
  213. printf ("timeout! Aborting...\n");
  214. }
  215. *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
  216. if (flag) {
  217. enable_interrupts ();
  218. }
  219. return rc;
  220. }
  221. int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
  222. {
  223. ulong read_addr, write_addr;
  224. FLASH_BUS data;
  225. int i, result = ERR_OK;
  226. read_addr = addr & ~(sizeof (FLASH_BUS) - 1);
  227. write_addr = read_addr;
  228. if (read_addr != addr) {
  229. data = 0;
  230. for (i = 0; i < sizeof (FLASH_BUS); i++) {
  231. if (read_addr < addr || cnt == 0) {
  232. data |= *((uchar *) read_addr) << i * 8;
  233. } else {
  234. data |= (*src++) << i * 8;
  235. cnt--;
  236. }
  237. read_addr++;
  238. }
  239. if ((result = write_data (info, write_addr, data)) != ERR_OK) {
  240. return result;
  241. }
  242. write_addr += sizeof (FLASH_BUS);
  243. }
  244. for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) {
  245. if ((result = write_data (info, write_addr,
  246. *((FLASH_BUS *) src))) != ERR_OK) {
  247. return result;
  248. }
  249. write_addr += sizeof (FLASH_BUS);
  250. src += sizeof (FLASH_BUS);
  251. }
  252. if (cnt > 0) {
  253. read_addr = write_addr;
  254. data = 0;
  255. for (i = 0; i < sizeof (FLASH_BUS); i++) {
  256. if (cnt > 0) {
  257. data |= (*src++) << i * 8;
  258. cnt--;
  259. } else {
  260. data |= *((uchar *) read_addr) << i * 8;
  261. }
  262. read_addr++;
  263. }
  264. if ((result = write_data (info, write_addr, data)) != 0) {
  265. return result;
  266. }
  267. }
  268. return ERR_OK;
  269. }