mip405.c 19 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. *
  24. * TODO: clean-up
  25. */
  26. /*
  27. * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM?
  28. *
  29. * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being
  30. * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum
  31. * parameters from the datasheet are:
  32. * Tclk = 7.5ns (CL = 2)
  33. * Trp = 15ns
  34. * Trc = 60ns
  35. * Trcd = 15ns
  36. * Trfc = 66ns
  37. *
  38. * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock
  39. * period is 10ns and the parameters needed for the Timing Register are:
  40. * CASL = CL = 2 clock cycles
  41. * PTA = Trp = 15ns / 10ns = 2 clock cycles
  42. * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles
  43. * LDF = 2 clock cycles (but can be extended to meet board-level timing)
  44. * RFTA = Trfc = 66ns / 10ns= 7 clock cycles
  45. * RCD = Trcd = 15ns / 10ns= 2 clock cycles
  46. *
  47. * The actual bit settings in the register would be:
  48. *
  49. * CASL = 0b01
  50. * PTA = 0b01
  51. * CTP = 0b10
  52. * LDF = 0b01
  53. * RFTA = 0b011
  54. * RCD = 0b01
  55. *
  56. * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc
  57. * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay
  58. * defined as Trc rather than Trfc.
  59. * When using DIMM modules, most but not all of the required timing parameters can be read
  60. * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc
  61. * are not available from the EEPROM
  62. */
  63. #include <common.h>
  64. #include "mip405.h"
  65. #include <asm/processor.h>
  66. #include <405gp_i2c.h>
  67. #include <miiphy.h>
  68. #include "../common/common_util.h"
  69. #include <i2c.h>
  70. extern block_dev_desc_t * scsi_get_dev(int dev);
  71. extern block_dev_desc_t * ide_get_dev(int dev);
  72. #undef SDRAM_DEBUG
  73. #define FALSE 0
  74. #define TRUE 1
  75. /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
  76. #ifndef __ldiv_t_defined
  77. typedef struct {
  78. long int quot; /* Quotient */
  79. long int rem; /* Remainder */
  80. } ldiv_t;
  81. extern ldiv_t ldiv (long int __numer, long int __denom);
  82. # define __ldiv_t_defined 1
  83. #endif
  84. #define PLD_PART_REG PER_PLD_ADDR + 0
  85. #define PLD_VERS_REG PER_PLD_ADDR + 1
  86. #define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2
  87. #define PLD_IRQ_REG PER_PLD_ADDR + 3
  88. #define PLD_COM_MODE_REG PER_PLD_ADDR + 4
  89. #define PLD_EXT_CONF_REG PER_PLD_ADDR + 5
  90. #define MEGA_BYTE (1024*1024)
  91. typedef struct {
  92. unsigned char boardtype; /* Board revision and Population Options */
  93. unsigned char cal; /* cas Latency (will be programmend as cal-1) */
  94. unsigned char trp; /* datain27 in clocks */
  95. unsigned char trcd; /* datain29 in clocks */
  96. unsigned char tras; /* datain30 in clocks */
  97. unsigned char tctp; /* tras - trcd in clocks */
  98. unsigned char am; /* Address Mod (will be programmed as am-1) */
  99. unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
  100. unsigned char ecc; /* if true, ecc is enabled */
  101. } sdram_t;
  102. const sdram_t sdram_table[] = {
  103. { 0x0f, /* Rev A, 128MByte -1 Board */
  104. 3, /* Case Latenty = 3 */
  105. 3, /* trp 20ns / 7.5 ns datain[27] */
  106. 3, /* trcd 20ns /7.5 ns (datain[29]) */
  107. 6, /* tras 44ns /7.5 ns (datain[30]) */
  108. 4, /* tcpt 44 - 20ns = 24ns */
  109. 3, /* Address Mode = 3 */
  110. 5, /* size value */
  111. 1}, /* ECC enabled */
  112. { 0x07, /* Rev A, 64MByte -2 Board */
  113. 3, /* Case Latenty = 3 */
  114. 3, /* trp 20ns / 7.5 ns datain[27] */
  115. 3, /* trcd 20ns /7.5 ns (datain[29]) */
  116. 6, /* tras 44ns /7.5 ns (datain[30]) */
  117. 4, /* tcpt 44 - 20ns = 24ns */
  118. 2, /* Address Mode = 2 */
  119. 4, /* size value */
  120. 1}, /* ECC enabled */
  121. { 0x03, /* Rev A, 128MByte -4 Board */
  122. 3, /* Case Latenty = 3 */
  123. 3, /* trp 20ns / 7.5 ns datain[27] */
  124. 3, /* trcd 20ns /7.5 ns (datain[29]) */
  125. 6, /* tras 44ns /7.5 ns (datain[30]) */
  126. 4, /* tcpt 44 - 20ns = 24ns */
  127. 3, /* Address Mode = 3 */
  128. 5, /* size value */
  129. 1}, /* ECC enabled */
  130. { 0xff, /* terminator */
  131. 0xff,
  132. 0xff,
  133. 0xff,
  134. 0xff,
  135. 0xff,
  136. 0xff,
  137. 0xff }
  138. };
  139. void SDRAM_err (const char *s)
  140. {
  141. #ifndef SDRAM_DEBUG
  142. DECLARE_GLOBAL_DATA_PTR;
  143. (void) get_clocks ();
  144. gd->baudrate = 9600;
  145. serial_init ();
  146. #endif
  147. serial_puts ("\n");
  148. serial_puts (s);
  149. serial_puts ("\n enable SDRAM_DEBUG for more info\n");
  150. for (;;);
  151. }
  152. unsigned char get_board_revcfg (void)
  153. {
  154. out8 (PER_BOARD_ADDR, 0);
  155. return (in8 (PER_BOARD_ADDR));
  156. }
  157. #ifdef SDRAM_DEBUG
  158. void write_hex (unsigned char i)
  159. {
  160. char cc;
  161. cc = i >> 4;
  162. cc &= 0xf;
  163. if (cc > 9)
  164. serial_putc (cc + 55);
  165. else
  166. serial_putc (cc + 48);
  167. cc = i & 0xf;
  168. if (cc > 9)
  169. serial_putc (cc + 55);
  170. else
  171. serial_putc (cc + 48);
  172. }
  173. void write_4hex (unsigned long val)
  174. {
  175. write_hex ((unsigned char) (val >> 24));
  176. write_hex ((unsigned char) (val >> 16));
  177. write_hex ((unsigned char) (val >> 8));
  178. write_hex ((unsigned char) val);
  179. }
  180. #endif
  181. int init_sdram (void)
  182. {
  183. DECLARE_GLOBAL_DATA_PTR;
  184. unsigned long tmp, baseaddr;
  185. unsigned short i;
  186. unsigned char trp_clocks,
  187. trcd_clocks,
  188. tras_clocks,
  189. trc_clocks,
  190. tctp_clocks;
  191. unsigned char cal_val;
  192. unsigned char bc;
  193. unsigned long pbcr, sdram_tim, sdram_bank;
  194. unsigned long *p;
  195. i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
  196. (void) get_clocks ();
  197. gd->baudrate = 9600;
  198. serial_init ();
  199. serial_puts ("\nInitializing SDRAM, Please stand by");
  200. mtdcr (ebccfga, pb0cr); /* get cs0 config reg */
  201. pbcr = mfdcr (ebccfgd);
  202. if ((pbcr & 0x00002000) == 0) {
  203. /* MPS Boot, set up the flash */
  204. mtdcr (ebccfga, pb1ap);
  205. mtdcr (ebccfgd, FLASH_AP);
  206. mtdcr (ebccfga, pb1cr);
  207. mtdcr (ebccfgd, FLASH_CR);
  208. } else {
  209. /* Flash boot, set up the MPS */
  210. mtdcr (ebccfga, pb1ap);
  211. mtdcr (ebccfgd, MPS_AP);
  212. mtdcr (ebccfga, pb1cr);
  213. mtdcr (ebccfgd, MPS_CR);
  214. }
  215. /* set up UART0 (CS2) and UART1 (CS3) */
  216. mtdcr (ebccfga, pb2ap);
  217. mtdcr (ebccfgd, UART0_AP);
  218. mtdcr (ebccfga, pb2cr);
  219. mtdcr (ebccfgd, UART0_CR);
  220. mtdcr (ebccfga, pb3ap);
  221. mtdcr (ebccfgd, UART1_AP);
  222. mtdcr (ebccfga, pb3cr);
  223. mtdcr (ebccfgd, UART1_CR);
  224. /* set up the pld */
  225. mtdcr (ebccfga, pb7ap);
  226. mtdcr (ebccfgd, PLD_AP);
  227. mtdcr (ebccfga, pb7cr);
  228. mtdcr (ebccfgd, PLD_CR);
  229. /* set up the board rev reg */
  230. mtdcr (ebccfga, pb5ap);
  231. mtdcr (ebccfgd, BOARD_AP);
  232. mtdcr (ebccfga, pb5cr);
  233. mtdcr (ebccfgd, BOARD_CR);
  234. #ifdef SDRAM_DEBUG
  235. out8 (PER_BOARD_ADDR, 0);
  236. bc = in8 (PER_BOARD_ADDR);
  237. serial_puts ("\nBoard Rev: ");
  238. write_hex (bc);
  239. serial_puts (" (PLD=");
  240. bc = in8 (PLD_BOARD_CFG_REG);
  241. write_hex (bc);
  242. serial_puts (")\n");
  243. #endif
  244. bc = get_board_revcfg ();
  245. #ifdef SDRAM_DEBUG
  246. serial_puts ("\nstart SDRAM Setup\n");
  247. serial_puts ("\nBoard Rev: ");
  248. write_hex (bc);
  249. serial_puts ("\n");
  250. #endif
  251. i = 0;
  252. baseaddr = CFG_SDRAM_BASE;
  253. while (sdram_table[i].sz != 0xff) {
  254. if (sdram_table[i].boardtype == bc)
  255. break;
  256. i++;
  257. }
  258. if (sdram_table[i].boardtype != bc)
  259. SDRAM_err ("No SDRAM table found for this board!!!\n");
  260. #ifdef SDRAM_DEBUG
  261. serial_puts (" found table ");
  262. write_hex (i);
  263. serial_puts (" \n");
  264. #endif
  265. cal_val = sdram_table[i].cal - 1; /* Cas Latency */
  266. trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */
  267. trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */
  268. tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */
  269. /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
  270. tctp_clocks = sdram_table[i].tctp; /* 44 - 20ns = 24ns */
  271. /* trc_clocks is sum of trp_clocks + tras_clocks */
  272. trc_clocks = trp_clocks + tras_clocks;
  273. /* get SDRAM timing register */
  274. mtdcr (memcfga, mem_sdtr1);
  275. sdram_tim = mfdcr (memcfgd) & ~0x018FC01F;
  276. /* insert CASL value */
  277. sdram_tim |= ((unsigned long) (cal_val)) << 23;
  278. /* insert PTA value */
  279. sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18;
  280. /* insert CTP value */
  281. sdram_tim |=
  282. ((unsigned long) (trc_clocks - trp_clocks -
  283. trcd_clocks)) << 16;
  284. /* insert LDF (always 01) */
  285. sdram_tim |= ((unsigned long) 0x01) << 14;
  286. /* insert RFTA value */
  287. sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2;
  288. /* insert RCD value */
  289. sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0;
  290. tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */
  291. /* insert SZ value; */
  292. tmp |= ((unsigned long) sdram_table[i].sz << 17);
  293. /* get SDRAM bank 0 register */
  294. mtdcr (memcfga, mem_mb0cf);
  295. sdram_bank = mfdcr (memcfgd) & ~0xFFCEE001;
  296. sdram_bank |= (baseaddr | tmp | 0x01);
  297. #ifdef SDRAM_DEBUG
  298. serial_puts ("sdtr: ");
  299. write_4hex (sdram_tim);
  300. serial_puts ("\n");
  301. #endif
  302. /* write SDRAM timing register */
  303. mtdcr (memcfga, mem_sdtr1);
  304. mtdcr (memcfgd, sdram_tim);
  305. #ifdef SDRAM_DEBUG
  306. serial_puts ("mb0cf: ");
  307. write_4hex (sdram_bank);
  308. serial_puts ("\n");
  309. #endif
  310. /* write SDRAM bank 0 register */
  311. mtdcr (memcfga, mem_mb0cf);
  312. mtdcr (memcfgd, sdram_bank);
  313. if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */
  314. /* get SDRAM refresh interval register */
  315. mtdcr (memcfga, mem_rtr);
  316. tmp = mfdcr (memcfgd) & ~0x3FF80000;
  317. tmp |= 0x07F00000;
  318. } else {
  319. /* get SDRAM refresh interval register */
  320. mtdcr (memcfga, mem_rtr);
  321. tmp = mfdcr (memcfgd) & ~0x3FF80000;
  322. tmp |= 0x05F00000;
  323. }
  324. /* write SDRAM refresh interval register */
  325. mtdcr (memcfga, mem_rtr);
  326. mtdcr (memcfgd, tmp);
  327. /* enable ECC if used */
  328. #if 1
  329. if (sdram_table[i].ecc) {
  330. /* disable checking for all banks */
  331. #ifdef SDRAM_DEBUG
  332. serial_puts ("disable ECC.. ");
  333. #endif
  334. mtdcr (memcfga, mem_ecccf);
  335. tmp = mfdcr (memcfgd);
  336. tmp &= 0xff0fffff; /* disable all banks */
  337. mtdcr (memcfga, mem_ecccf);
  338. /* set up SDRAM Controller with ECC enabled */
  339. #ifdef SDRAM_DEBUG
  340. serial_puts ("setup SDRAM Controller.. ");
  341. #endif
  342. mtdcr (memcfgd, tmp);
  343. mtdcr (memcfga, mem_mcopt1);
  344. tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000;
  345. mtdcr (memcfga, mem_mcopt1);
  346. mtdcr (memcfgd, tmp);
  347. udelay (600);
  348. #ifdef SDRAM_DEBUG
  349. serial_puts ("fill the memory..\n");
  350. #endif
  351. serial_puts (".");
  352. /* now, fill all the memory */
  353. tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);
  354. p = (unsigned long) 0;
  355. while ((unsigned long) p < tmp) {
  356. *p++ = 0L;
  357. if (!((unsigned long) p % 0x00800000)) /* every 8MByte */
  358. serial_puts (".");
  359. }
  360. /* enable bank 0 */
  361. serial_puts (".");
  362. #ifdef SDRAM_DEBUG
  363. serial_puts ("enable ECC\n");
  364. #endif
  365. udelay (400);
  366. mtdcr (memcfga, mem_ecccf);
  367. tmp = mfdcr (memcfgd);
  368. tmp |= 0x00800000; /* enable bank 0 */
  369. mtdcr (memcfgd, tmp);
  370. udelay (400);
  371. } else
  372. #endif
  373. {
  374. /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
  375. mtdcr (memcfga, mem_mcopt1);
  376. tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000;
  377. mtdcr (memcfga, mem_mcopt1);
  378. mtdcr (memcfgd, tmp);
  379. udelay (400);
  380. }
  381. serial_puts ("\n");
  382. return (0);
  383. }
  384. int board_pre_init (void)
  385. {
  386. init_sdram ();
  387. /*-------------------------------------------------------------------------+
  388. | Interrupt controller setup for the PIP405 board.
  389. | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
  390. | IRQ 16 405GP internally generated; active low; level sensitive
  391. | IRQ 17-24 RESERVED
  392. | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
  393. | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
  394. | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
  395. | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
  396. | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
  397. | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
  398. | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
  399. | Note for MIP405 board:
  400. | An interrupt taken for the SouthBridge (IRQ 25) indicates that
  401. | the Interrupt Controller in the South Bridge has caused the
  402. | interrupt. The IC must be read to determine which device
  403. | caused the interrupt.
  404. |
  405. +-------------------------------------------------------------------------*/
  406. mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
  407. mtdcr (uicer, 0x00000000); /* disable all ints */
  408. mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */
  409. mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */
  410. mtdcr (uictr, 0x10000000); /* set int trigger levels */
  411. mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
  412. mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
  413. return 0;
  414. }
  415. /*
  416. * Get some PLD Registers
  417. */
  418. unsigned short get_pld_parvers (void)
  419. {
  420. unsigned short result;
  421. unsigned char rc;
  422. rc = in8 (PLD_PART_REG);
  423. result = (unsigned short) rc << 8;
  424. rc = in8 (PLD_VERS_REG);
  425. result |= rc;
  426. return result;
  427. }
  428. void user_led0 (unsigned char on)
  429. {
  430. if (on)
  431. out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));
  432. else
  433. out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));
  434. }
  435. void ide_set_reset (int idereset)
  436. {
  437. /* if reset = 1 IDE reset will be asserted */
  438. if (idereset)
  439. out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));
  440. else {
  441. udelay (10000);
  442. out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));
  443. }
  444. }
  445. /* ------------------------------------------------------------------------- */
  446. /*
  447. * Check Board Identity:
  448. */
  449. int checkboard (void)
  450. {
  451. unsigned char s[50];
  452. unsigned char bc, var, rc;
  453. int i;
  454. backup_t *b = (backup_t *) s;
  455. puts ("Board: ");
  456. bc = get_board_revcfg ();
  457. var = ~bc;
  458. var &= 0xf;
  459. rc = 0;
  460. for (i = 0; i < 4; i++) {
  461. rc <<= 1;
  462. rc += (var & 0x1);
  463. var >>= 1;
  464. }
  465. rc++;
  466. i = getenv_r ("serial#", s, 32);
  467. if ((i == 0) || strncmp (s, "MIP405", 6)) {
  468. get_backup_values (b);
  469. if (strncmp (b->signature, "MPL\0", 4) != 0) {
  470. puts ("### No HW ID - assuming MIP405");
  471. printf ("-%d Rev %c", rc, 'A' + ((bc >> 4) & 0xf));
  472. } else {
  473. b->serial_name[6] = 0;
  474. printf ("%s-%d Rev %c SN: %s", b->serial_name, rc,
  475. 'A' + ((bc >> 4) & 0xf), &b->serial_name[7]);
  476. }
  477. } else {
  478. s[6] = 0;
  479. printf ("%s-%d Rev %c SN: %s", s, rc, 'A' + ((bc >> 4) & 0xf),
  480. &s[7]);
  481. }
  482. bc = in8 (PLD_EXT_CONF_REG);
  483. printf (" Boot Config: 0x%x\n", bc);
  484. return (0);
  485. }
  486. /* ------------------------------------------------------------------------- */
  487. /* ------------------------------------------------------------------------- */
  488. /*
  489. initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
  490. the necessary info for SDRAM controller configuration
  491. */
  492. /* ------------------------------------------------------------------------- */
  493. /* ------------------------------------------------------------------------- */
  494. static int test_dram (unsigned long ramsize);
  495. long int initdram (int board_type)
  496. {
  497. unsigned long bank_reg[4], tmp, bank_size;
  498. int i, ds;
  499. unsigned long TotalSize;
  500. ds = 0;
  501. /* since the DRAM controller is allready set up, calculate the size with the
  502. bank registers */
  503. mtdcr (memcfga, mem_mb0cf);
  504. bank_reg[0] = mfdcr (memcfgd);
  505. mtdcr (memcfga, mem_mb1cf);
  506. bank_reg[1] = mfdcr (memcfgd);
  507. mtdcr (memcfga, mem_mb2cf);
  508. bank_reg[2] = mfdcr (memcfgd);
  509. mtdcr (memcfga, mem_mb3cf);
  510. bank_reg[3] = mfdcr (memcfgd);
  511. TotalSize = 0;
  512. for (i = 0; i < 4; i++) {
  513. if ((bank_reg[i] & 0x1) == 0x1) {
  514. tmp = (bank_reg[i] >> 17) & 0x7;
  515. bank_size = 4 << tmp;
  516. TotalSize += bank_size;
  517. } else
  518. ds = 1;
  519. }
  520. mtdcr (memcfga, mem_ecccf);
  521. tmp = mfdcr (memcfgd);
  522. if (!tmp)
  523. printf ("No ");
  524. printf ("ECC ");
  525. test_dram (TotalSize * MEGA_BYTE);
  526. return (TotalSize * MEGA_BYTE);
  527. }
  528. /* ------------------------------------------------------------------------- */
  529. extern int mem_test (unsigned long start, unsigned long ramsize,
  530. int quiet);
  531. static int test_dram (unsigned long ramsize)
  532. {
  533. #ifdef SDRAM_DEBUG
  534. mem_test (0L, ramsize, 1);
  535. #endif
  536. /* not yet implemented */
  537. return (1);
  538. }
  539. int misc_init_r (void)
  540. {
  541. return (0);
  542. }
  543. void print_mip405_rev (void)
  544. {
  545. unsigned char part, vers, cfg, rev;
  546. cfg = get_board_revcfg ();
  547. vers = cfg;
  548. vers &= 0xf;
  549. rev = (((vers & 0x1) ? 0x8 : 0) |
  550. ((vers & 0x2) ? 0x4 : 0) |
  551. ((vers & 0x4) ? 0x2 : 0) | ((vers & 0x8) ? 0x1 : 0));
  552. part = in8 (PLD_PART_REG);
  553. vers = in8 (PLD_VERS_REG);
  554. printf ("Rev: MIP405-%d Rev %c PLD%d Vers %d\n",
  555. (16 - rev), ((cfg >> 4) & 0xf) + 'A', part, vers);
  556. }
  557. int last_stage_init (void)
  558. {
  559. /* write correct LED configuration */
  560. if (miiphy_write (0x1, 0x14, 0x2402) != 0) {
  561. printf ("Error writing to the PHY\n");
  562. }
  563. /* since LED/CFG2 is not connected on the -2,
  564. * write to correct capability information */
  565. if (miiphy_write (0x1, 0x4, 0x01E1) != 0) {
  566. printf ("Error writing to the PHY\n");
  567. }
  568. print_mip405_rev ();
  569. show_stdio_dev ();
  570. check_env ();
  571. return 0;
  572. }
  573. /***************************************************************************
  574. * some helping routines
  575. */
  576. int overwrite_console (void)
  577. {
  578. return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0); /* return TRUE if console should be overwritten */
  579. }
  580. /************************************************************************
  581. * Print MIP405 Info
  582. ************************************************************************/
  583. void print_mip405_info (void)
  584. {
  585. unsigned char part, vers, cfg, irq_reg, com_mode, ext;
  586. part = in8 (PLD_PART_REG);
  587. vers = in8 (PLD_VERS_REG);
  588. cfg = in8 (PLD_BOARD_CFG_REG);
  589. irq_reg = in8 (PLD_IRQ_REG);
  590. com_mode = in8 (PLD_COM_MODE_REG);
  591. ext = in8 (PLD_EXT_CONF_REG);
  592. printf ("PLD Part %d version %d\n", part, vers);
  593. printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');
  594. printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,
  595. (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
  596. printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
  597. printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
  598. printf ("Test ist %x\n", com_mode);
  599. printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
  600. (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
  601. (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
  602. (ext >> 6) & 0x1, (ext >> 7) & 0x1);
  603. printf ("SER1 uses handshakes %s\n",
  604. (ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
  605. printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
  606. printf ("IRQs:\n");
  607. printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
  608. printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
  609. printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
  610. printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active");
  611. printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");
  612. printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active");
  613. }