memsetup.S 14 KB

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  1. /*
  2. * Most of this taken from Redboot hal_platform_setup.h with cleanup
  3. *
  4. * NOTE: I haven't clean this up considerably, just enough to get it
  5. * running. See hal_platform_setup.h for the source. See
  6. * board/cradle/memsetup.S for another PXA250 setup that is
  7. * much cleaner.
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #include <config.h>
  28. #include <version.h>
  29. #include <asm/arch/pxa-regs.h>
  30. DRAM_SIZE: .long CFG_DRAM_SIZE
  31. /* wait for coprocessor write complete */
  32. .macro CPWAIT reg
  33. mrc p15,0,\reg,c2,c0,0
  34. mov \reg,\reg
  35. sub pc,pc,#4
  36. .endm
  37. _TEXT_BASE:
  38. .word TEXT_BASE
  39. /*
  40. * Memory setup
  41. */
  42. .globl memsetup
  43. memsetup:
  44. mov r10, lr
  45. /* Set up GPIO pins first ----------------------------------------- */
  46. ldr r0, =GPSR0
  47. ldr r1, =CFG_GPSR0_VAL
  48. str r1, [r0]
  49. ldr r0, =GPSR1
  50. ldr r1, =CFG_GPSR1_VAL
  51. str r1, [r0]
  52. ldr r0, =GPSR2
  53. ldr r1, =CFG_GPSR2_VAL
  54. str r1, [r0]
  55. ldr r0, =GPCR0
  56. ldr r1, =CFG_GPCR0_VAL
  57. str r1, [r0]
  58. ldr r0, =GPCR1
  59. ldr r1, =CFG_GPCR1_VAL
  60. str r1, [r0]
  61. ldr r0, =GPCR2
  62. ldr r1, =CFG_GPCR2_VAL
  63. str r1, [r0]
  64. ldr r0, =GPDR0
  65. ldr r1, =CFG_GPDR0_VAL
  66. str r1, [r0]
  67. ldr r0, =GPDR1
  68. ldr r1, =CFG_GPDR1_VAL
  69. str r1, [r0]
  70. ldr r0, =GPDR2
  71. ldr r1, =CFG_GPDR2_VAL
  72. str r1, [r0]
  73. ldr r0, =GAFR0_L
  74. ldr r1, =CFG_GAFR0_L_VAL
  75. str r1, [r0]
  76. ldr r0, =GAFR0_U
  77. ldr r1, =CFG_GAFR0_U_VAL
  78. str r1, [r0]
  79. ldr r0, =GAFR1_L
  80. ldr r1, =CFG_GAFR1_L_VAL
  81. str r1, [r0]
  82. ldr r0, =GAFR1_U
  83. ldr r1, =CFG_GAFR1_U_VAL
  84. str r1, [r0]
  85. ldr r0, =GAFR2_L
  86. ldr r1, =CFG_GAFR2_L_VAL
  87. str r1, [r0]
  88. ldr r0, =GAFR2_U
  89. ldr r1, =CFG_GAFR2_U_VAL
  90. str r1, [r0]
  91. ldr r0, =PSSR /* enable GPIO pins */
  92. ldr r1, =CFG_PSSR_VAL
  93. str r1, [r0]
  94. /* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */
  95. /* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */
  96. /* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */
  97. /* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */
  98. /* */
  99. /* ldr r1, =LED_BLANK */
  100. /* mov r0, #0xFF */
  101. /* str r0, [r1] / turn on hex leds */
  102. /* */
  103. /*loop: */
  104. /* */
  105. /* ldr r0, =0xB0070001 */
  106. /* ldr r1, =_LED */
  107. /* str r0, [r1] / hex display */
  108. /* ---------------------------------------------------------------- */
  109. /* Enable memory interface */
  110. /* */
  111. /* The sequence below is based on the recommended init steps */
  112. /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
  113. /* Chapter 10. */
  114. /* ---------------------------------------------------------------- */
  115. /* ---------------------------------------------------------------- */
  116. /* Step 1: Wait for at least 200 microsedonds to allow internal */
  117. /* clocks to settle. Only necessary after hard reset... */
  118. /* FIXME: can be optimized later */
  119. /* ---------------------------------------------------------------- */
  120. ldr r3, =OSCR /* reset the OS Timer Count to zero */
  121. mov r2, #0
  122. str r2, [r3]
  123. ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
  124. /* so 0x300 should be plenty */
  125. 1:
  126. ldr r2, [r3]
  127. cmp r4, r2
  128. bgt 1b
  129. mem_init:
  130. ldr r1, =MEMC_BASE /* get memory controller base addr. */
  131. /* ---------------------------------------------------------------- */
  132. /* Step 2a: Initialize Asynchronous static memory controller */
  133. /* ---------------------------------------------------------------- */
  134. /* MSC registers: timing, bus width, mem type */
  135. /* MSC0: nCS(0,1) */
  136. ldr r2, =CFG_MSC0_VAL
  137. str r2, [r1, #MSC0_OFFSET]
  138. ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
  139. /* that data latches */
  140. /* MSC1: nCS(2,3) */
  141. ldr r2, =CFG_MSC1_VAL
  142. str r2, [r1, #MSC1_OFFSET]
  143. ldr r2, [r1, #MSC1_OFFSET]
  144. /* MSC2: nCS(4,5) */
  145. ldr r2, =CFG_MSC2_VAL
  146. str r2, [r1, #MSC2_OFFSET]
  147. ldr r2, [r1, #MSC2_OFFSET]
  148. /* ---------------------------------------------------------------- */
  149. /* Step 2b: Initialize Card Interface */
  150. /* ---------------------------------------------------------------- */
  151. /* MECR: Memory Expansion Card Register */
  152. ldr r2, =CFG_MECR_VAL
  153. str r2, [r1, #MECR_OFFSET]
  154. ldr r2, [r1, #MECR_OFFSET]
  155. /* MCMEM0: Card Interface slot 0 timing */
  156. ldr r2, =CFG_MCMEM0_VAL
  157. str r2, [r1, #MCMEM0_OFFSET]
  158. ldr r2, [r1, #MCMEM0_OFFSET]
  159. /* MCMEM1: Card Interface slot 1 timing */
  160. ldr r2, =CFG_MCMEM1_VAL
  161. str r2, [r1, #MCMEM1_OFFSET]
  162. ldr r2, [r1, #MCMEM1_OFFSET]
  163. /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
  164. ldr r2, =CFG_MCATT0_VAL
  165. str r2, [r1, #MCATT0_OFFSET]
  166. ldr r2, [r1, #MCATT0_OFFSET]
  167. /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
  168. ldr r2, =CFG_MCATT1_VAL
  169. str r2, [r1, #MCATT1_OFFSET]
  170. ldr r2, [r1, #MCATT1_OFFSET]
  171. /* MCIO0: Card Interface I/O Space Timing, slot 0 */
  172. ldr r2, =CFG_MCIO0_VAL
  173. str r2, [r1, #MCIO0_OFFSET]
  174. ldr r2, [r1, #MCIO0_OFFSET]
  175. /* MCIO1: Card Interface I/O Space Timing, slot 1 */
  176. ldr r2, =CFG_MCIO1_VAL
  177. str r2, [r1, #MCIO1_OFFSET]
  178. ldr r2, [r1, #MCIO1_OFFSET]
  179. /* ---------------------------------------------------------------- */
  180. /* Step 2c: Write FLYCNFG FIXME: what's that??? */
  181. /* ---------------------------------------------------------------- */
  182. /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
  183. adr r3, mem_init /* r0 <- current position of code */
  184. ldr r2, =mem_init
  185. cmp r3, r2 /* skip init if in place */
  186. beq initirqs
  187. /* ---------------------------------------------------------------- */
  188. /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
  189. /* ---------------------------------------------------------------- */
  190. /* Before accessing MDREFR we need a valid DRI field, so we set */
  191. /* this to power on defaults + DRI field. */
  192. ldr r3, =CFG_MDREFR_VAL
  193. ldr r2, =0xFFF
  194. and r3, r3, r2
  195. ldr r4, =0x03ca4000
  196. orr r4, r4, r3
  197. str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
  198. ldr r4, [r1, #MDREFR_OFFSET]
  199. /* ---------------------------------------------------------------- */
  200. /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
  201. /* ---------------------------------------------------------------- */
  202. /* Initialize SXCNFG register. Assert the enable bits */
  203. /* Write SXMRS to cause an MRS command to all enabled banks of */
  204. /* synchronous static memory. Note that SXLCR need not be written */
  205. /* at this time. */
  206. /* FIXME: we use async mode for now */
  207. /* ---------------------------------------------------------------- */
  208. /* Step 4: Initialize SDRAM */
  209. /* ---------------------------------------------------------------- */
  210. /* Step 4a: assert MDREFR:K?RUN and configure */
  211. /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
  212. ldr r4, =CFG_MDREFR_VAL
  213. str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
  214. ldr r4, [r1, #MDREFR_OFFSET]
  215. /* Step 4b: de-assert MDREFR:SLFRSH. */
  216. bic r4, r4, #(MDREFR_SLFRSH)
  217. str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
  218. ldr r4, [r1, #MDREFR_OFFSET]
  219. /* Step 4c: assert MDREFR:E1PIN and E0PIO */
  220. orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
  221. str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
  222. ldr r4, [r1, #MDREFR_OFFSET]
  223. /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
  224. /* configure but not enable each SDRAM partition pair. */
  225. ldr r4, =CFG_MDCNFG_VAL
  226. bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
  227. str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
  228. ldr r4, [r1, #MDCNFG_OFFSET]
  229. /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
  230. /* 100..200 µsec. */
  231. ldr r3, =OSCR /* reset the OS Timer Count to zero */
  232. mov r2, #0
  233. str r2, [r3]
  234. ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
  235. /* so 0x300 should be plenty */
  236. 1:
  237. ldr r2, [r3]
  238. cmp r4, r2
  239. bgt 1b
  240. /* Step 4f: Trigger a number (usually 8) refresh cycles by */
  241. /* attempting non-burst read or write accesses to disabled */
  242. /* SDRAM, as commonly specified in the power up sequence */
  243. /* documented in SDRAM data sheets. The address(es) used */
  244. /* for this purpose must not be cacheable. */
  245. /* There should 9 writes, since the first write doesn't */
  246. /* trigger a refresh cycle on PXA250. See Intel PXA250 and */
  247. /* PXA210 Processors Specification Update, */
  248. /* Jan 2003, Errata #116, page 30. */
  249. ldr r3, =CFG_DRAM_BASE
  250. str r2, [r3]
  251. str r2, [r3]
  252. str r2, [r3]
  253. str r2, [r3]
  254. str r2, [r3]
  255. str r2, [r3]
  256. str r2, [r3]
  257. str r2, [r3]
  258. str r2, [r3]
  259. /* Step 4g: Write MDCNFG with enable bits asserted */
  260. /* (MDCNFG:DEx set to 1). */
  261. ldr r3, [r1, #MDCNFG_OFFSET]
  262. orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
  263. str r3, [r1, #MDCNFG_OFFSET]
  264. /* Step 4h: Write MDMRS. */
  265. ldr r2, =CFG_MDMRS_VAL
  266. str r2, [r1, #MDMRS_OFFSET]
  267. /* We are finished with Intel's memory controller initialisation */
  268. /* ---------------------------------------------------------------- */
  269. /* Disable (mask) all interrupts at interrupt controller */
  270. /* ---------------------------------------------------------------- */
  271. initirqs:
  272. mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
  273. ldr r2, =ICLR
  274. str r1, [r2]
  275. ldr r2, =ICMR /* mask all interrupts at the controller */
  276. str r1, [r2]
  277. /* ---------------------------------------------------------------- */
  278. /* Clock initialisation */
  279. /* ---------------------------------------------------------------- */
  280. initclks:
  281. /* Disable the peripheral clocks, and set the core clock frequency */
  282. /* (hard-coding at 398.12MHz for now). */
  283. /* Turn Off ALL on-chip peripheral clocks for re-configuration */
  284. /* Note: See label 'ENABLECLKS' for the re-enabling */
  285. ldr r1, =CKEN
  286. mov r2, #0
  287. str r2, [r1]
  288. /* default value in case no valid rotary switch setting is found */
  289. ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
  290. /* ... and write the core clock config register */
  291. ldr r1, =CCCR
  292. str r2, [r1]
  293. /* enable the 32Khz oscillator for RTC and PowerManager */
  294. /*
  295. ldr r1, =OSCC
  296. mov r2, #OSCC_OON
  297. str r2, [r1]
  298. */
  299. /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
  300. /* has settled. */
  301. 60:
  302. ldr r2, [r1]
  303. ands r2, r2, #1
  304. beq 60b
  305. /* ---------------------------------------------------------------- */
  306. /* */
  307. /* ---------------------------------------------------------------- */
  308. /* Save SDRAM size */
  309. ldr r1, =DRAM_SIZE
  310. str r8, [r1]
  311. /* Interrupt init: Mask all interrupts */
  312. ldr r0, =ICMR /* enable no sources */
  313. mov r1, #0
  314. str r1, [r0]
  315. /* FIXME */
  316. #ifndef DEBUG
  317. /*Disable software and data breakpoints */
  318. mov r0,#0
  319. mcr p15,0,r0,c14,c8,0 /* ibcr0 */
  320. mcr p15,0,r0,c14,c9,0 /* ibcr1 */
  321. mcr p15,0,r0,c14,c4,0 /* dbcon */
  322. /*Enable all debug functionality */
  323. mov r0,#0x80000000
  324. mcr p14,0,r0,c10,c0,0 /* dcsr */
  325. #endif
  326. /* ---------------------------------------------------------------- */
  327. /* End memsetup */
  328. /* ---------------------------------------------------------------- */
  329. endmemsetup:
  330. mov pc, lr