qe.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
  4. *
  5. * Dave Liu <daveliu@freescale.com>
  6. * based on source code of Shlomi Gridish
  7. */
  8. #include <common.h>
  9. #include <malloc.h>
  10. #include <command.h>
  11. #include <linux/errno.h>
  12. #include <asm/io.h>
  13. #include <linux/immap_qe.h>
  14. #include <fsl_qe.h>
  15. #include <mmc.h>
  16. #include <u-boot/crc.h>
  17. #ifdef CONFIG_ARCH_LS1021A
  18. #include <asm/arch/immap_ls102xa.h>
  19. #endif
  20. #ifdef CONFIG_ARM64
  21. #include <asm/armv8/mmu.h>
  22. #include <asm/arch/cpu.h>
  23. #endif
  24. #define MPC85xx_DEVDISR_QE_DISABLE 0x1
  25. qe_map_t *qe_immr = NULL;
  26. #ifdef CONFIG_QE
  27. static qe_snum_t snums[QE_NUM_OF_SNUM];
  28. #endif
  29. DECLARE_GLOBAL_DATA_PTR;
  30. void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
  31. {
  32. u32 cecr;
  33. if (cmd == QE_RESET) {
  34. out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG));
  35. } else {
  36. out_be32(&qe_immr->cp.cecdr, cmd_data);
  37. out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG |
  38. ((u32) mcn<<QE_CR_PROTOCOL_SHIFT) | cmd));
  39. }
  40. /* Wait for the QE_CR_FLG to clear */
  41. do {
  42. cecr = in_be32(&qe_immr->cp.cecr);
  43. } while (cecr & QE_CR_FLG);
  44. return;
  45. }
  46. #ifdef CONFIG_QE
  47. uint qe_muram_alloc(uint size, uint align)
  48. {
  49. uint retloc;
  50. uint align_mask, off;
  51. uint savebase;
  52. align_mask = align - 1;
  53. savebase = gd->arch.mp_alloc_base;
  54. off = gd->arch.mp_alloc_base & align_mask;
  55. if (off != 0)
  56. gd->arch.mp_alloc_base += (align - off);
  57. if ((off = size & align_mask) != 0)
  58. size += (align - off);
  59. if ((gd->arch.mp_alloc_base + size) >= gd->arch.mp_alloc_top) {
  60. gd->arch.mp_alloc_base = savebase;
  61. printf("%s: ran out of ram.\n", __FUNCTION__);
  62. }
  63. retloc = gd->arch.mp_alloc_base;
  64. gd->arch.mp_alloc_base += size;
  65. memset((void *)&qe_immr->muram[retloc], 0, size);
  66. __asm__ __volatile__("sync");
  67. return retloc;
  68. }
  69. #endif
  70. void *qe_muram_addr(uint offset)
  71. {
  72. return (void *)&qe_immr->muram[offset];
  73. }
  74. #ifdef CONFIG_QE
  75. static void qe_sdma_init(void)
  76. {
  77. volatile sdma_t *p;
  78. uint sdma_buffer_base;
  79. p = (volatile sdma_t *)&qe_immr->sdma;
  80. /* All of DMA transaction in bus 1 */
  81. out_be32(&p->sdaqr, 0);
  82. out_be32(&p->sdaqmr, 0);
  83. /* Allocate 2KB temporary buffer for sdma */
  84. sdma_buffer_base = qe_muram_alloc(2048, 4096);
  85. out_be32(&p->sdwbcr, sdma_buffer_base & QE_SDEBCR_BA_MASK);
  86. /* Clear sdma status */
  87. out_be32(&p->sdsr, 0x03000000);
  88. /* Enable global mode on bus 1, and 2KB buffer size */
  89. out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT));
  90. }
  91. /* This table is a list of the serial numbers of the Threads, taken from the
  92. * "SNUM Table" chart in the QE Reference Manual. The order is not important,
  93. * we just need to know what the SNUMs are for the threads.
  94. */
  95. static u8 thread_snum[] = {
  96. /* Evthreads 16-29 are not supported in MPC8309 */
  97. #if !defined(CONFIG_ARCH_MPC8309)
  98. 0x04, 0x05, 0x0c, 0x0d,
  99. 0x14, 0x15, 0x1c, 0x1d,
  100. 0x24, 0x25, 0x2c, 0x2d,
  101. 0x34, 0x35,
  102. #endif
  103. 0x88, 0x89, 0x98, 0x99,
  104. 0xa8, 0xa9, 0xb8, 0xb9,
  105. 0xc8, 0xc9, 0xd8, 0xd9,
  106. 0xe8, 0xe9, 0x08, 0x09,
  107. 0x18, 0x19, 0x28, 0x29,
  108. 0x38, 0x39, 0x48, 0x49,
  109. 0x58, 0x59, 0x68, 0x69,
  110. 0x78, 0x79, 0x80, 0x81
  111. };
  112. static void qe_snums_init(void)
  113. {
  114. int i;
  115. for (i = 0; i < QE_NUM_OF_SNUM; i++) {
  116. snums[i].state = QE_SNUM_STATE_FREE;
  117. snums[i].num = thread_snum[i];
  118. }
  119. }
  120. int qe_get_snum(void)
  121. {
  122. int snum = -EBUSY;
  123. int i;
  124. for (i = 0; i < QE_NUM_OF_SNUM; i++) {
  125. if (snums[i].state == QE_SNUM_STATE_FREE) {
  126. snums[i].state = QE_SNUM_STATE_USED;
  127. snum = snums[i].num;
  128. break;
  129. }
  130. }
  131. return snum;
  132. }
  133. void qe_put_snum(u8 snum)
  134. {
  135. int i;
  136. for (i = 0; i < QE_NUM_OF_SNUM; i++) {
  137. if (snums[i].num == snum) {
  138. snums[i].state = QE_SNUM_STATE_FREE;
  139. break;
  140. }
  141. }
  142. }
  143. #ifdef CONFIG_TFABOOT
  144. void qe_init(uint qe_base)
  145. {
  146. enum boot_src src = get_boot_src();
  147. /* Init the QE IMMR base */
  148. qe_immr = (qe_map_t *)qe_base;
  149. if (src == BOOT_SOURCE_IFC_NOR) {
  150. /*
  151. * Upload microcode to IRAM for those SOCs
  152. * which do not have ROM in QE.
  153. */
  154. qe_upload_firmware((const void *)(CONFIG_SYS_QE_FW_ADDR +
  155. CONFIG_SYS_FSL_IFC_BASE));
  156. /* enable the microcode in IRAM */
  157. out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
  158. }
  159. gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
  160. gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE;
  161. qe_sdma_init();
  162. qe_snums_init();
  163. }
  164. #else
  165. void qe_init(uint qe_base)
  166. {
  167. /* Init the QE IMMR base */
  168. qe_immr = (qe_map_t *)qe_base;
  169. #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NOR
  170. /*
  171. * Upload microcode to IRAM for those SOCs which do not have ROM in QE.
  172. */
  173. qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
  174. /* enable the microcode in IRAM */
  175. out_be32(&qe_immr->iram.iready,QE_IRAM_READY);
  176. #endif
  177. gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
  178. gd->arch.mp_alloc_top = gd->arch.mp_alloc_base + QE_DATAONLY_SIZE;
  179. qe_sdma_init();
  180. qe_snums_init();
  181. }
  182. #endif
  183. #endif
  184. #ifdef CONFIG_U_QE
  185. #ifdef CONFIG_TFABOOT
  186. void u_qe_init(void)
  187. {
  188. enum boot_src src = get_boot_src();
  189. qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
  190. void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
  191. if (src == BOOT_SOURCE_IFC_NOR)
  192. addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_IFC_BASE);
  193. if (src == BOOT_SOURCE_QSPI_NOR)
  194. addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_QSPI_BASE);
  195. if (src == BOOT_SOURCE_SD_MMC) {
  196. int dev = CONFIG_SYS_MMC_ENV_DEV;
  197. u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
  198. u32 blk = CONFIG_SYS_QE_FW_ADDR / 512;
  199. if (mmc_initialize(gd->bd)) {
  200. printf("%s: mmc_initialize() failed\n", __func__);
  201. return;
  202. }
  203. addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
  204. struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
  205. if (!mmc) {
  206. free(addr);
  207. printf("\nMMC cannot find device for ucode\n");
  208. } else {
  209. printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
  210. dev, blk, cnt);
  211. mmc_init(mmc);
  212. (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
  213. addr);
  214. }
  215. }
  216. if (!u_qe_upload_firmware(addr))
  217. out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
  218. if (src == BOOT_SOURCE_SD_MMC)
  219. free(addr);
  220. }
  221. #else
  222. void u_qe_init(void)
  223. {
  224. qe_immr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
  225. void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
  226. #ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
  227. int dev = CONFIG_SYS_MMC_ENV_DEV;
  228. u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
  229. u32 blk = CONFIG_SYS_QE_FW_ADDR / 512;
  230. if (mmc_initialize(gd->bd)) {
  231. printf("%s: mmc_initialize() failed\n", __func__);
  232. return;
  233. }
  234. addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
  235. struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
  236. if (!mmc) {
  237. free(addr);
  238. printf("\nMMC cannot find device for ucode\n");
  239. } else {
  240. printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
  241. dev, blk, cnt);
  242. mmc_init(mmc);
  243. (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
  244. addr);
  245. }
  246. #endif
  247. if (!u_qe_upload_firmware(addr))
  248. out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
  249. #ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC
  250. free(addr);
  251. #endif
  252. }
  253. #endif
  254. #endif
  255. #ifdef CONFIG_U_QE
  256. void u_qe_resume(void)
  257. {
  258. qe_map_t *qe_immrr;
  259. qe_immrr = (qe_map_t *)(CONFIG_SYS_IMMR + QE_IMMR_OFFSET);
  260. u_qe_firmware_resume((const void *)CONFIG_SYS_QE_FW_ADDR, qe_immrr);
  261. out_be32(&qe_immrr->iram.iready, QE_IRAM_READY);
  262. }
  263. #endif
  264. void qe_reset(void)
  265. {
  266. qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
  267. (u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
  268. }
  269. #ifdef CONFIG_QE
  270. void qe_assign_page(uint snum, uint para_ram_base)
  271. {
  272. u32 cecr;
  273. out_be32(&qe_immr->cp.cecdr, para_ram_base);
  274. out_be32(&qe_immr->cp.cecr, ((u32) snum<<QE_CR_ASSIGN_PAGE_SNUM_SHIFT)
  275. | QE_CR_FLG | QE_ASSIGN_PAGE);
  276. /* Wait for the QE_CR_FLG to clear */
  277. do {
  278. cecr = in_be32(&qe_immr->cp.cecr);
  279. } while (cecr & QE_CR_FLG );
  280. return;
  281. }
  282. #endif
  283. /*
  284. * brg: 0~15 as BRG1~BRG16
  285. rate: baud rate
  286. * BRG input clock comes from the BRGCLK (internal clock generated from
  287. the QE clock, it is one-half of the QE clock), If need the clock source
  288. from CLKn pin, we have te change the function.
  289. */
  290. #define BRG_CLK (gd->arch.brg_clk)
  291. #ifdef CONFIG_QE
  292. int qe_set_brg(uint brg, uint rate)
  293. {
  294. volatile uint *bp;
  295. u32 divisor;
  296. int div16 = 0;
  297. if (brg >= QE_NUM_OF_BRGS)
  298. return -EINVAL;
  299. bp = (uint *)&qe_immr->brg.brgc1;
  300. bp += brg;
  301. divisor = (BRG_CLK / rate);
  302. if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
  303. div16 = 1;
  304. divisor /= 16;
  305. }
  306. *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
  307. __asm__ __volatile__("sync");
  308. if (div16) {
  309. *bp |= QE_BRGC_DIV16;
  310. __asm__ __volatile__("sync");
  311. }
  312. return 0;
  313. }
  314. #endif
  315. /* Set ethernet MII clock master
  316. */
  317. int qe_set_mii_clk_src(int ucc_num)
  318. {
  319. u32 cmxgcr;
  320. /* check if the UCC number is in range. */
  321. if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
  322. printf("%s: ucc num not in ranges\n", __FUNCTION__);
  323. return -EINVAL;
  324. }
  325. cmxgcr = in_be32(&qe_immr->qmx.cmxgcr);
  326. cmxgcr &= ~QE_CMXGCR_MII_ENET_MNG_MASK;
  327. cmxgcr |= (ucc_num <<QE_CMXGCR_MII_ENET_MNG_SHIFT);
  328. out_be32(&qe_immr->qmx.cmxgcr, cmxgcr);
  329. return 0;
  330. }
  331. /* Firmware information stored here for qe_get_firmware_info() */
  332. static struct qe_firmware_info qe_firmware_info;
  333. /*
  334. * Set to 1 if QE firmware has been uploaded, and therefore
  335. * qe_firmware_info contains valid data.
  336. */
  337. static int qe_firmware_uploaded;
  338. /*
  339. * Upload a QE microcode
  340. *
  341. * This function is a worker function for qe_upload_firmware(). It does
  342. * the actual uploading of the microcode.
  343. */
  344. static void qe_upload_microcode(const void *base,
  345. const struct qe_microcode *ucode)
  346. {
  347. const u32 *code = base + be32_to_cpu(ucode->code_offset);
  348. unsigned int i;
  349. if (ucode->major || ucode->minor || ucode->revision)
  350. printf("QE: uploading microcode '%s' version %u.%u.%u\n",
  351. (char *)ucode->id, (u16)ucode->major, (u16)ucode->minor,
  352. (u16)ucode->revision);
  353. else
  354. printf("QE: uploading microcode '%s'\n", (char *)ucode->id);
  355. /* Use auto-increment */
  356. out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
  357. QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
  358. for (i = 0; i < be32_to_cpu(ucode->count); i++)
  359. out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
  360. }
  361. /*
  362. * Upload a microcode to the I-RAM at a specific address.
  363. *
  364. * See docs/README.qe_firmware for information on QE microcode uploading.
  365. *
  366. * Currently, only version 1 is supported, so the 'version' field must be
  367. * set to 1.
  368. *
  369. * The SOC model and revision are not validated, they are only displayed for
  370. * informational purposes.
  371. *
  372. * 'calc_size' is the calculated size, in bytes, of the firmware structure and
  373. * all of the microcode structures, minus the CRC.
  374. *
  375. * 'length' is the size that the structure says it is, including the CRC.
  376. */
  377. int qe_upload_firmware(const struct qe_firmware *firmware)
  378. {
  379. unsigned int i;
  380. unsigned int j;
  381. u32 crc;
  382. size_t calc_size = sizeof(struct qe_firmware);
  383. size_t length;
  384. const struct qe_header *hdr;
  385. #ifdef CONFIG_DEEP_SLEEP
  386. #ifdef CONFIG_ARCH_LS1021A
  387. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  388. #else
  389. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  390. #endif
  391. #endif
  392. if (!firmware) {
  393. printf("Invalid address\n");
  394. return -EINVAL;
  395. }
  396. hdr = &firmware->header;
  397. length = be32_to_cpu(hdr->length);
  398. /* Check the magic */
  399. if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
  400. (hdr->magic[2] != 'F')) {
  401. printf("QE microcode not found\n");
  402. #ifdef CONFIG_DEEP_SLEEP
  403. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
  404. #endif
  405. return -EPERM;
  406. }
  407. /* Check the version */
  408. if (hdr->version != 1) {
  409. printf("Unsupported version\n");
  410. return -EPERM;
  411. }
  412. /* Validate some of the fields */
  413. if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
  414. printf("Invalid data\n");
  415. return -EINVAL;
  416. }
  417. /* Validate the length and check if there's a CRC */
  418. calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
  419. for (i = 0; i < firmware->count; i++)
  420. /*
  421. * For situations where the second RISC uses the same microcode
  422. * as the first, the 'code_offset' and 'count' fields will be
  423. * zero, so it's okay to add those.
  424. */
  425. calc_size += sizeof(u32) *
  426. be32_to_cpu(firmware->microcode[i].count);
  427. /* Validate the length */
  428. if (length != calc_size + sizeof(u32)) {
  429. printf("Invalid length\n");
  430. return -EPERM;
  431. }
  432. /*
  433. * Validate the CRC. We would normally call crc32_no_comp(), but that
  434. * function isn't available unless you turn on JFFS support.
  435. */
  436. crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
  437. if (crc != (crc32(-1, (const void *) firmware, calc_size) ^ -1)) {
  438. printf("Firmware CRC is invalid\n");
  439. return -EIO;
  440. }
  441. /*
  442. * If the microcode calls for it, split the I-RAM.
  443. */
  444. if (!firmware->split) {
  445. out_be16(&qe_immr->cp.cercr,
  446. in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
  447. }
  448. if (firmware->soc.model)
  449. printf("Firmware '%s' for %u V%u.%u\n",
  450. firmware->id, be16_to_cpu(firmware->soc.model),
  451. firmware->soc.major, firmware->soc.minor);
  452. else
  453. printf("Firmware '%s'\n", firmware->id);
  454. /*
  455. * The QE only supports one microcode per RISC, so clear out all the
  456. * saved microcode information and put in the new.
  457. */
  458. memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
  459. strncpy(qe_firmware_info.id, (char *)firmware->id, 62);
  460. qe_firmware_info.extended_modes = firmware->extended_modes;
  461. memcpy(qe_firmware_info.vtraps, firmware->vtraps,
  462. sizeof(firmware->vtraps));
  463. qe_firmware_uploaded = 1;
  464. /* Loop through each microcode. */
  465. for (i = 0; i < firmware->count; i++) {
  466. const struct qe_microcode *ucode = &firmware->microcode[i];
  467. /* Upload a microcode if it's present */
  468. if (ucode->code_offset)
  469. qe_upload_microcode(firmware, ucode);
  470. /* Program the traps for this processor */
  471. for (j = 0; j < 16; j++) {
  472. u32 trap = be32_to_cpu(ucode->traps[j]);
  473. if (trap)
  474. out_be32(&qe_immr->rsp[i].tibcr[j], trap);
  475. }
  476. /* Enable traps */
  477. out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
  478. }
  479. return 0;
  480. }
  481. #ifdef CONFIG_U_QE
  482. /*
  483. * Upload a microcode to the I-RAM at a specific address.
  484. *
  485. * See docs/README.qe_firmware for information on QE microcode uploading.
  486. *
  487. * Currently, only version 1 is supported, so the 'version' field must be
  488. * set to 1.
  489. *
  490. * The SOC model and revision are not validated, they are only displayed for
  491. * informational purposes.
  492. *
  493. * 'calc_size' is the calculated size, in bytes, of the firmware structure and
  494. * all of the microcode structures, minus the CRC.
  495. *
  496. * 'length' is the size that the structure says it is, including the CRC.
  497. */
  498. int u_qe_upload_firmware(const struct qe_firmware *firmware)
  499. {
  500. unsigned int i;
  501. unsigned int j;
  502. u32 crc;
  503. size_t calc_size = sizeof(struct qe_firmware);
  504. size_t length;
  505. const struct qe_header *hdr;
  506. #ifdef CONFIG_DEEP_SLEEP
  507. #ifdef CONFIG_ARCH_LS1021A
  508. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  509. #else
  510. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  511. #endif
  512. #endif
  513. if (!firmware) {
  514. printf("Invalid address\n");
  515. return -EINVAL;
  516. }
  517. hdr = &firmware->header;
  518. length = be32_to_cpu(hdr->length);
  519. /* Check the magic */
  520. if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
  521. (hdr->magic[2] != 'F')) {
  522. printf("Not a microcode\n");
  523. #ifdef CONFIG_DEEP_SLEEP
  524. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
  525. #endif
  526. return -EPERM;
  527. }
  528. /* Check the version */
  529. if (hdr->version != 1) {
  530. printf("Unsupported version\n");
  531. return -EPERM;
  532. }
  533. /* Validate some of the fields */
  534. if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
  535. printf("Invalid data\n");
  536. return -EINVAL;
  537. }
  538. /* Validate the length and check if there's a CRC */
  539. calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
  540. for (i = 0; i < firmware->count; i++)
  541. /*
  542. * For situations where the second RISC uses the same microcode
  543. * as the first, the 'code_offset' and 'count' fields will be
  544. * zero, so it's okay to add those.
  545. */
  546. calc_size += sizeof(u32) *
  547. be32_to_cpu(firmware->microcode[i].count);
  548. /* Validate the length */
  549. if (length != calc_size + sizeof(u32)) {
  550. printf("Invalid length\n");
  551. return -EPERM;
  552. }
  553. /*
  554. * Validate the CRC. We would normally call crc32_no_comp(), but that
  555. * function isn't available unless you turn on JFFS support.
  556. */
  557. crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
  558. if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
  559. printf("Firmware CRC is invalid\n");
  560. return -EIO;
  561. }
  562. /*
  563. * If the microcode calls for it, split the I-RAM.
  564. */
  565. if (!firmware->split) {
  566. out_be16(&qe_immr->cp.cercr,
  567. in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
  568. }
  569. if (firmware->soc.model)
  570. printf("Firmware '%s' for %u V%u.%u\n",
  571. firmware->id, be16_to_cpu(firmware->soc.model),
  572. firmware->soc.major, firmware->soc.minor);
  573. else
  574. printf("Firmware '%s'\n", firmware->id);
  575. /* Loop through each microcode. */
  576. for (i = 0; i < firmware->count; i++) {
  577. const struct qe_microcode *ucode = &firmware->microcode[i];
  578. /* Upload a microcode if it's present */
  579. if (ucode->code_offset)
  580. qe_upload_microcode(firmware, ucode);
  581. /* Program the traps for this processor */
  582. for (j = 0; j < 16; j++) {
  583. u32 trap = be32_to_cpu(ucode->traps[j]);
  584. if (trap)
  585. out_be32(&qe_immr->rsp[i].tibcr[j], trap);
  586. }
  587. /* Enable traps */
  588. out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
  589. }
  590. return 0;
  591. }
  592. #endif
  593. #ifdef CONFIG_U_QE
  594. int u_qe_firmware_resume(const struct qe_firmware *firmware, qe_map_t *qe_immrr)
  595. {
  596. unsigned int i;
  597. unsigned int j;
  598. const struct qe_header *hdr;
  599. const u32 *code;
  600. #ifdef CONFIG_DEEP_SLEEP
  601. #ifdef CONFIG_PPC
  602. ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  603. #else
  604. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  605. #endif
  606. #endif
  607. if (!firmware)
  608. return -EINVAL;
  609. hdr = &firmware->header;
  610. /* Check the magic */
  611. if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
  612. (hdr->magic[2] != 'F')) {
  613. #ifdef CONFIG_DEEP_SLEEP
  614. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
  615. #endif
  616. return -EPERM;
  617. }
  618. /*
  619. * If the microcode calls for it, split the I-RAM.
  620. */
  621. if (!firmware->split) {
  622. out_be16(&qe_immrr->cp.cercr,
  623. in_be16(&qe_immrr->cp.cercr) | QE_CP_CERCR_CIR);
  624. }
  625. /* Loop through each microcode. */
  626. for (i = 0; i < firmware->count; i++) {
  627. const struct qe_microcode *ucode = &firmware->microcode[i];
  628. /* Upload a microcode if it's present */
  629. if (!ucode->code_offset)
  630. return 0;
  631. code = (const void *)firmware + be32_to_cpu(ucode->code_offset);
  632. /* Use auto-increment */
  633. out_be32(&qe_immrr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
  634. QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
  635. for (i = 0; i < be32_to_cpu(ucode->count); i++)
  636. out_be32(&qe_immrr->iram.idata, be32_to_cpu(code[i]));
  637. /* Program the traps for this processor */
  638. for (j = 0; j < 16; j++) {
  639. u32 trap = be32_to_cpu(ucode->traps[j]);
  640. if (trap)
  641. out_be32(&qe_immrr->rsp[i].tibcr[j], trap);
  642. }
  643. /* Enable traps */
  644. out_be32(&qe_immrr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
  645. }
  646. return 0;
  647. }
  648. #endif
  649. struct qe_firmware_info *qe_get_firmware_info(void)
  650. {
  651. return qe_firmware_uploaded ? &qe_firmware_info : NULL;
  652. }
  653. static int qe_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  654. {
  655. ulong addr;
  656. if (argc < 3)
  657. return cmd_usage(cmdtp);
  658. if (strcmp(argv[1], "fw") == 0) {
  659. addr = simple_strtoul(argv[2], NULL, 16);
  660. if (!addr) {
  661. printf("Invalid address\n");
  662. return -EINVAL;
  663. }
  664. /*
  665. * If a length was supplied, compare that with the 'length'
  666. * field.
  667. */
  668. if (argc > 3) {
  669. ulong length = simple_strtoul(argv[3], NULL, 16);
  670. struct qe_firmware *firmware = (void *) addr;
  671. if (length != be32_to_cpu(firmware->header.length)) {
  672. printf("Length mismatch\n");
  673. return -EINVAL;
  674. }
  675. }
  676. return qe_upload_firmware((const struct qe_firmware *) addr);
  677. }
  678. return cmd_usage(cmdtp);
  679. }
  680. U_BOOT_CMD(
  681. qe, 4, 0, qe_cmd,
  682. "QUICC Engine commands",
  683. "fw <addr> [<length>] - Upload firmware binary at address <addr> to "
  684. "the QE,\n"
  685. "\twith optional length <length> verification."
  686. );