pinctrl_stm32.c 11 KB

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  1. #include <common.h>
  2. #include <dm.h>
  3. #include <hwspinlock.h>
  4. #include <asm/arch/gpio.h>
  5. #include <asm/gpio.h>
  6. #include <asm/io.h>
  7. #include <dm/lists.h>
  8. #include <dm/pinctrl.h>
  9. DECLARE_GLOBAL_DATA_PTR;
  10. #define MAX_PINS_ONE_IP 70
  11. #define MODE_BITS_MASK 3
  12. #define OSPEED_MASK 3
  13. #define PUPD_MASK 3
  14. #define OTYPE_MSK 1
  15. #define AFR_MASK 0xF
  16. struct stm32_pinctrl_priv {
  17. struct hwspinlock hws;
  18. int pinctrl_ngpios;
  19. struct list_head gpio_dev;
  20. };
  21. struct stm32_gpio_bank {
  22. struct udevice *gpio_dev;
  23. struct list_head list;
  24. };
  25. #ifndef CONFIG_SPL_BUILD
  26. static char pin_name[PINNAME_SIZE];
  27. #define PINMUX_MODE_COUNT 5
  28. static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
  29. "gpio input",
  30. "gpio output",
  31. "analog",
  32. "unknown",
  33. "alt function",
  34. };
  35. static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
  36. {
  37. struct stm32_gpio_priv *priv = dev_get_priv(dev);
  38. struct stm32_gpio_regs *regs = priv->regs;
  39. u32 af;
  40. u32 alt_shift = (offset % 8) * 4;
  41. u32 alt_index = offset / 8;
  42. af = (readl(&regs->afr[alt_index]) &
  43. GENMASK(alt_shift + 3, alt_shift)) >> alt_shift;
  44. return af;
  45. }
  46. static int stm32_populate_gpio_dev_list(struct udevice *dev)
  47. {
  48. struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
  49. struct udevice *gpio_dev;
  50. struct udevice *child;
  51. struct stm32_gpio_bank *gpio_bank;
  52. int ret;
  53. /*
  54. * parse pin-controller sub-nodes (ie gpio bank nodes) and fill
  55. * a list with all gpio device reference which belongs to the
  56. * current pin-controller. This list is used to find pin_name and
  57. * pin muxing
  58. */
  59. list_for_each_entry(child, &dev->child_head, sibling_node) {
  60. ret = uclass_get_device_by_name(UCLASS_GPIO, child->name,
  61. &gpio_dev);
  62. if (ret < 0)
  63. continue;
  64. gpio_bank = malloc(sizeof(*gpio_bank));
  65. if (!gpio_bank) {
  66. dev_err(dev, "Not enough memory\n");
  67. return -ENOMEM;
  68. }
  69. gpio_bank->gpio_dev = gpio_dev;
  70. list_add_tail(&gpio_bank->list, &priv->gpio_dev);
  71. }
  72. return 0;
  73. }
  74. static int stm32_pinctrl_get_pins_count(struct udevice *dev)
  75. {
  76. struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
  77. struct gpio_dev_priv *uc_priv;
  78. struct stm32_gpio_bank *gpio_bank;
  79. /*
  80. * if get_pins_count has already been executed once on this
  81. * pin-controller, no need to run it again
  82. */
  83. if (priv->pinctrl_ngpios)
  84. return priv->pinctrl_ngpios;
  85. if (list_empty(&priv->gpio_dev))
  86. stm32_populate_gpio_dev_list(dev);
  87. /*
  88. * walk through all banks to retrieve the pin-controller
  89. * pins number
  90. */
  91. list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
  92. uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
  93. priv->pinctrl_ngpios += uc_priv->gpio_count;
  94. }
  95. return priv->pinctrl_ngpios;
  96. }
  97. static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
  98. unsigned int selector,
  99. unsigned int *idx)
  100. {
  101. struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
  102. struct stm32_gpio_bank *gpio_bank;
  103. struct gpio_dev_priv *uc_priv;
  104. int pin_count = 0;
  105. if (list_empty(&priv->gpio_dev))
  106. stm32_populate_gpio_dev_list(dev);
  107. /* look up for the bank which owns the requested pin */
  108. list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
  109. uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
  110. if (selector < (pin_count + uc_priv->gpio_count)) {
  111. /*
  112. * we found the bank, convert pin selector to
  113. * gpio bank index
  114. */
  115. *idx = stm32_offset_to_index(gpio_bank->gpio_dev,
  116. selector - pin_count);
  117. if (IS_ERR_VALUE(*idx))
  118. return NULL;
  119. return gpio_bank->gpio_dev;
  120. }
  121. pin_count += uc_priv->gpio_count;
  122. }
  123. return NULL;
  124. }
  125. static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
  126. unsigned int selector)
  127. {
  128. struct gpio_dev_priv *uc_priv;
  129. struct udevice *gpio_dev;
  130. unsigned int gpio_idx;
  131. /* look up for the bank which owns the requested pin */
  132. gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
  133. if (!gpio_dev) {
  134. snprintf(pin_name, PINNAME_SIZE, "Error");
  135. } else {
  136. uc_priv = dev_get_uclass_priv(gpio_dev);
  137. snprintf(pin_name, PINNAME_SIZE, "%s%d",
  138. uc_priv->bank_name,
  139. gpio_idx);
  140. }
  141. return pin_name;
  142. }
  143. static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
  144. unsigned int selector,
  145. char *buf,
  146. int size)
  147. {
  148. struct udevice *gpio_dev;
  149. const char *label;
  150. int mode;
  151. int af_num;
  152. unsigned int gpio_idx;
  153. /* look up for the bank which owns the requested pin */
  154. gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
  155. if (!gpio_dev)
  156. return -ENODEV;
  157. mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
  158. dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
  159. selector, gpio_idx, mode);
  160. switch (mode) {
  161. case GPIOF_UNKNOWN:
  162. /* should never happen */
  163. return -EINVAL;
  164. case GPIOF_UNUSED:
  165. snprintf(buf, size, "%s", pinmux_mode[mode]);
  166. break;
  167. case GPIOF_FUNC:
  168. af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
  169. snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
  170. break;
  171. case GPIOF_OUTPUT:
  172. case GPIOF_INPUT:
  173. snprintf(buf, size, "%s %s",
  174. pinmux_mode[mode], label ? label : "");
  175. break;
  176. }
  177. return 0;
  178. }
  179. #endif
  180. static int stm32_pinctrl_probe(struct udevice *dev)
  181. {
  182. struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
  183. int ret;
  184. INIT_LIST_HEAD(&priv->gpio_dev);
  185. /* hwspinlock property is optional, just log the error */
  186. ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
  187. if (ret)
  188. debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
  189. __func__, ret);
  190. return 0;
  191. }
  192. static int stm32_gpio_config(struct gpio_desc *desc,
  193. const struct stm32_gpio_ctl *ctl)
  194. {
  195. struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
  196. struct stm32_gpio_regs *regs = priv->regs;
  197. struct stm32_pinctrl_priv *ctrl_priv;
  198. int ret;
  199. u32 index;
  200. if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
  201. ctl->pupd > 2 || ctl->speed > 3)
  202. return -EINVAL;
  203. ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
  204. ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
  205. if (ret == -ETIME) {
  206. dev_err(desc->dev, "HWSpinlock timeout\n");
  207. return ret;
  208. }
  209. index = (desc->offset & 0x07) * 4;
  210. clrsetbits_le32(&regs->afr[desc->offset >> 3], AFR_MASK << index,
  211. ctl->af << index);
  212. index = desc->offset * 2;
  213. clrsetbits_le32(&regs->moder, MODE_BITS_MASK << index,
  214. ctl->mode << index);
  215. clrsetbits_le32(&regs->ospeedr, OSPEED_MASK << index,
  216. ctl->speed << index);
  217. clrsetbits_le32(&regs->pupdr, PUPD_MASK << index, ctl->pupd << index);
  218. index = desc->offset;
  219. clrsetbits_le32(&regs->otyper, OTYPE_MSK << index, ctl->otype << index);
  220. hwspinlock_unlock(&ctrl_priv->hws);
  221. return 0;
  222. }
  223. static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
  224. {
  225. gpio_dsc->port = (port_pin & 0x1F000) >> 12;
  226. gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
  227. debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
  228. gpio_dsc->pin);
  229. return 0;
  230. }
  231. static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
  232. {
  233. gpio_fn &= 0x00FF;
  234. gpio_ctl->af = 0;
  235. switch (gpio_fn) {
  236. case 0:
  237. gpio_ctl->mode = STM32_GPIO_MODE_IN;
  238. break;
  239. case 1 ... 16:
  240. gpio_ctl->mode = STM32_GPIO_MODE_AF;
  241. gpio_ctl->af = gpio_fn - 1;
  242. break;
  243. case 17:
  244. gpio_ctl->mode = STM32_GPIO_MODE_AN;
  245. break;
  246. default:
  247. gpio_ctl->mode = STM32_GPIO_MODE_OUT;
  248. break;
  249. }
  250. gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
  251. if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
  252. gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
  253. else
  254. gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
  255. if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
  256. gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
  257. else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
  258. gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
  259. else
  260. gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
  261. debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
  262. __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
  263. gpio_ctl->pupd);
  264. return 0;
  265. }
  266. static int stm32_pinctrl_config(int offset)
  267. {
  268. u32 pin_mux[MAX_PINS_ONE_IP];
  269. int rv, len;
  270. /*
  271. * check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
  272. * usart1) of pin controller phandle "pinctrl-0"
  273. * */
  274. fdt_for_each_subnode(offset, gd->fdt_blob, offset) {
  275. struct stm32_gpio_dsc gpio_dsc;
  276. struct stm32_gpio_ctl gpio_ctl;
  277. int i;
  278. len = fdtdec_get_int_array_count(gd->fdt_blob, offset,
  279. "pinmux", pin_mux,
  280. ARRAY_SIZE(pin_mux));
  281. debug("%s: no of pinmux entries= %d\n", __func__, len);
  282. if (len < 0)
  283. return -EINVAL;
  284. for (i = 0; i < len; i++) {
  285. struct gpio_desc desc;
  286. debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
  287. prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
  288. prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), offset);
  289. rv = uclass_get_device_by_seq(UCLASS_GPIO,
  290. gpio_dsc.port,
  291. &desc.dev);
  292. if (rv)
  293. return rv;
  294. desc.offset = gpio_dsc.pin;
  295. rv = stm32_gpio_config(&desc, &gpio_ctl);
  296. debug("%s: rv = %d\n\n", __func__, rv);
  297. if (rv)
  298. return rv;
  299. }
  300. }
  301. return 0;
  302. }
  303. static int stm32_pinctrl_bind(struct udevice *dev)
  304. {
  305. ofnode node;
  306. const char *name;
  307. int ret;
  308. dev_for_each_subnode(node, dev) {
  309. debug("%s: bind %s\n", __func__, ofnode_get_name(node));
  310. ofnode_get_property(node, "gpio-controller", &ret);
  311. if (ret < 0)
  312. continue;
  313. /* Get the name of each gpio node */
  314. name = ofnode_get_name(node);
  315. if (!name)
  316. return -EINVAL;
  317. /* Bind each gpio node */
  318. ret = device_bind_driver_to_node(dev, "gpio_stm32",
  319. name, node, NULL);
  320. if (ret)
  321. return ret;
  322. debug("%s: bind %s\n", __func__, name);
  323. }
  324. return 0;
  325. }
  326. #if CONFIG_IS_ENABLED(PINCTRL_FULL)
  327. static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config)
  328. {
  329. return stm32_pinctrl_config(dev_of_offset(config));
  330. }
  331. #else /* PINCTRL_FULL */
  332. static int stm32_pinctrl_set_state_simple(struct udevice *dev,
  333. struct udevice *periph)
  334. {
  335. const void *fdt = gd->fdt_blob;
  336. const fdt32_t *list;
  337. uint32_t phandle;
  338. int config_node;
  339. int size, i, ret;
  340. list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size);
  341. if (!list)
  342. return -EINVAL;
  343. debug("%s: periph->name = %s\n", __func__, periph->name);
  344. size /= sizeof(*list);
  345. for (i = 0; i < size; i++) {
  346. phandle = fdt32_to_cpu(*list++);
  347. config_node = fdt_node_offset_by_phandle(fdt, phandle);
  348. if (config_node < 0) {
  349. pr_err("prop pinctrl-0 index %d invalid phandle\n", i);
  350. return -EINVAL;
  351. }
  352. ret = stm32_pinctrl_config(config_node);
  353. if (ret)
  354. return ret;
  355. }
  356. return 0;
  357. }
  358. #endif /* PINCTRL_FULL */
  359. static struct pinctrl_ops stm32_pinctrl_ops = {
  360. #if CONFIG_IS_ENABLED(PINCTRL_FULL)
  361. .set_state = stm32_pinctrl_set_state,
  362. #else /* PINCTRL_FULL */
  363. .set_state_simple = stm32_pinctrl_set_state_simple,
  364. #endif /* PINCTRL_FULL */
  365. #ifndef CONFIG_SPL_BUILD
  366. .get_pin_name = stm32_pinctrl_get_pin_name,
  367. .get_pins_count = stm32_pinctrl_get_pins_count,
  368. .get_pin_muxing = stm32_pinctrl_get_pin_muxing,
  369. #endif
  370. };
  371. static const struct udevice_id stm32_pinctrl_ids[] = {
  372. { .compatible = "st,stm32f429-pinctrl" },
  373. { .compatible = "st,stm32f469-pinctrl" },
  374. { .compatible = "st,stm32f746-pinctrl" },
  375. { .compatible = "st,stm32f769-pinctrl" },
  376. { .compatible = "st,stm32h743-pinctrl" },
  377. { .compatible = "st,stm32mp157-pinctrl" },
  378. { .compatible = "st,stm32mp157-z-pinctrl" },
  379. { }
  380. };
  381. U_BOOT_DRIVER(pinctrl_stm32) = {
  382. .name = "pinctrl_stm32",
  383. .id = UCLASS_PINCTRL,
  384. .of_match = stm32_pinctrl_ids,
  385. .ops = &stm32_pinctrl_ops,
  386. .bind = stm32_pinctrl_bind,
  387. .probe = stm32_pinctrl_probe,
  388. .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),
  389. };