uli526x.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007, 2010 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Roy Zang <tie-fei.zang@freescale.com>, Sep, 2007
  6. *
  7. * Description:
  8. * ULI 526x Ethernet port driver.
  9. * Based on the Linux driver: drivers/net/tulip/uli526x.c
  10. */
  11. #include <common.h>
  12. #include <malloc.h>
  13. #include <net.h>
  14. #include <netdev.h>
  15. #include <asm/io.h>
  16. #include <pci.h>
  17. #include <miiphy.h>
  18. /* some kernel function compatible define */
  19. #undef DEBUG
  20. /* Board/System/Debug information/definition */
  21. #define ULI_VENDOR_ID 0x10B9
  22. #define ULI5261_DEVICE_ID 0x5261
  23. #define ULI5263_DEVICE_ID 0x5263
  24. /* ULi M5261 ID*/
  25. #define PCI_ULI5261_ID (ULI5261_DEVICE_ID << 16 | ULI_VENDOR_ID)
  26. /* ULi M5263 ID*/
  27. #define PCI_ULI5263_ID (ULI5263_DEVICE_ID << 16 | ULI_VENDOR_ID)
  28. #define ULI526X_IO_SIZE 0x100
  29. #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
  30. #define RX_DESC_CNT PKTBUFSRX /* Allocated Rx descriptors */
  31. #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
  32. #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
  33. #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
  34. #define TX_BUF_ALLOC 0x300
  35. #define RX_ALLOC_SIZE PKTSIZE
  36. #define ULI526X_RESET 1
  37. #define CR0_DEFAULT 0
  38. #define CR6_DEFAULT 0x22200000
  39. #define CR7_DEFAULT 0x180c1
  40. #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
  41. #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
  42. #define MAX_PACKET_SIZE 1514
  43. #define ULI5261_MAX_MULTICAST 14
  44. #define RX_COPY_SIZE 100
  45. #define MAX_CHECK_PACKET 0x8000
  46. #define ULI526X_10MHF 0
  47. #define ULI526X_100MHF 1
  48. #define ULI526X_10MFD 4
  49. #define ULI526X_100MFD 5
  50. #define ULI526X_AUTO 8
  51. #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
  52. #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
  53. #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
  54. #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
  55. #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
  56. #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
  57. /* CR9 definition: SROM/MII */
  58. #define CR9_SROM_READ 0x4800
  59. #define CR9_SRCS 0x1
  60. #define CR9_SRCLK 0x2
  61. #define CR9_CRDOUT 0x8
  62. #define SROM_DATA_0 0x0
  63. #define SROM_DATA_1 0x4
  64. #define PHY_DATA_1 0x20000
  65. #define PHY_DATA_0 0x00000
  66. #define MDCLKH 0x10000
  67. #define PHY_POWER_DOWN 0x800
  68. #define SROM_V41_CODE 0x14
  69. #define SROM_CLK_WRITE(data, ioaddr) do { \
  70. outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
  71. udelay(5); \
  72. outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK, ioaddr); \
  73. udelay(5); \
  74. outl(data|CR9_SROM_READ|CR9_SRCS, ioaddr); \
  75. udelay(5); \
  76. } while (0)
  77. /* Structure/enum declaration */
  78. struct tx_desc {
  79. u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
  80. char *tx_buf_ptr; /* Data for us */
  81. struct tx_desc *next_tx_desc;
  82. };
  83. struct rx_desc {
  84. u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
  85. char *rx_buf_ptr; /* Data for us */
  86. struct rx_desc *next_rx_desc;
  87. };
  88. struct uli526x_board_info {
  89. u32 chip_id; /* Chip vendor/Device ID */
  90. pci_dev_t pdev;
  91. long ioaddr; /* I/O base address */
  92. u32 cr0_data;
  93. u32 cr5_data;
  94. u32 cr6_data;
  95. u32 cr7_data;
  96. u32 cr15_data;
  97. /* pointer for memory physical address */
  98. dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
  99. dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
  100. dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
  101. dma_addr_t first_tx_desc_dma;
  102. dma_addr_t first_rx_desc_dma;
  103. /* descriptor pointer */
  104. unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
  105. unsigned char *buf_pool_start; /* Tx buffer pool align dword */
  106. unsigned char *desc_pool_ptr; /* descriptor pool memory */
  107. struct tx_desc *first_tx_desc;
  108. struct tx_desc *tx_insert_ptr;
  109. struct tx_desc *tx_remove_ptr;
  110. struct rx_desc *first_rx_desc;
  111. struct rx_desc *rx_ready_ptr; /* packet come pointer */
  112. unsigned long tx_packet_cnt; /* transmitted packet count */
  113. u16 PHY_reg4; /* Saved Phyxcer register 4 value */
  114. u8 media_mode; /* user specify media mode */
  115. u8 op_mode; /* real work dedia mode */
  116. u8 phy_addr;
  117. /* NIC SROM data */
  118. unsigned char srom[128];
  119. };
  120. enum uli526x_offsets {
  121. DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
  122. DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
  123. DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
  124. DCR15 = 0x78
  125. };
  126. enum uli526x_CR6_bits {
  127. CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
  128. CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
  129. CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
  130. };
  131. /* Global variable declaration -- */
  132. static unsigned char uli526x_media_mode = ULI526X_AUTO;
  133. static struct tx_desc desc_pool_array[DESC_ALL_CNT + 0x20]
  134. __attribute__ ((aligned(32)));
  135. static char buf_pool[TX_BUF_ALLOC * TX_DESC_CNT + 4];
  136. /* For module input parameter */
  137. static int mode = 8;
  138. /* function declaration -- */
  139. static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length);
  140. static u16 read_srom_word(long, int);
  141. static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
  142. static void allocate_rx_buffer(struct uli526x_board_info *);
  143. static void update_cr6(u32, unsigned long);
  144. static u16 uli_phy_read(unsigned long, u8, u8, u32);
  145. static u16 phy_readby_cr10(unsigned long, u8, u8);
  146. static void uli_phy_write(unsigned long, u8, u8, u16, u32);
  147. static void phy_writeby_cr10(unsigned long, u8, u8, u16);
  148. static void phy_write_1bit(unsigned long, u32, u32);
  149. static u16 phy_read_1bit(unsigned long, u32);
  150. static int uli526x_rx_packet(struct eth_device *);
  151. static void uli526x_free_tx_pkt(struct eth_device *,
  152. struct uli526x_board_info *);
  153. static void uli526x_reuse_buf(struct rx_desc *);
  154. static void uli526x_init(struct eth_device *);
  155. static void uli526x_set_phyxcer(struct uli526x_board_info *);
  156. static int uli526x_init_one(struct eth_device *, bd_t *);
  157. static void uli526x_disable(struct eth_device *);
  158. static void set_mac_addr(struct eth_device *);
  159. static struct pci_device_id uli526x_pci_tbl[] = {
  160. { ULI_VENDOR_ID, ULI5261_DEVICE_ID}, /* 5261 device */
  161. { ULI_VENDOR_ID, ULI5263_DEVICE_ID}, /* 5263 device */
  162. {}
  163. };
  164. /* ULI526X network board routine */
  165. /*
  166. * Search ULI526X board, register it
  167. */
  168. int uli526x_initialize(bd_t *bis)
  169. {
  170. pci_dev_t devno;
  171. int card_number = 0;
  172. struct eth_device *dev;
  173. struct uli526x_board_info *db; /* board information structure */
  174. u32 iobase;
  175. int idx = 0;
  176. while (1) {
  177. /* Find PCI device */
  178. devno = pci_find_devices(uli526x_pci_tbl, idx++);
  179. if (devno < 0)
  180. break;
  181. pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
  182. iobase &= ~0xf;
  183. dev = (struct eth_device *)malloc(sizeof *dev);
  184. if (!dev) {
  185. printf("uli526x: Can not allocate memory\n");
  186. break;
  187. }
  188. memset(dev, 0, sizeof(*dev));
  189. sprintf(dev->name, "uli526x#%d", card_number);
  190. db = (struct uli526x_board_info *)
  191. malloc(sizeof(struct uli526x_board_info));
  192. dev->priv = db;
  193. db->pdev = devno;
  194. dev->iobase = iobase;
  195. dev->init = uli526x_init_one;
  196. dev->halt = uli526x_disable;
  197. dev->send = uli526x_start_xmit;
  198. dev->recv = uli526x_rx_packet;
  199. /* init db */
  200. db->ioaddr = dev->iobase;
  201. /* get chip id */
  202. pci_read_config_dword(devno, PCI_VENDOR_ID, &db->chip_id);
  203. #ifdef DEBUG
  204. printf("uli526x: uli526x @0x%x\n", iobase);
  205. printf("uli526x: chip_id%x\n", db->chip_id);
  206. #endif
  207. eth_register(dev);
  208. card_number++;
  209. pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
  210. udelay(10 * 1000);
  211. }
  212. return card_number;
  213. }
  214. static int uli526x_init_one(struct eth_device *dev, bd_t *bis)
  215. {
  216. struct uli526x_board_info *db = dev->priv;
  217. int i;
  218. switch (mode) {
  219. case ULI526X_10MHF:
  220. case ULI526X_100MHF:
  221. case ULI526X_10MFD:
  222. case ULI526X_100MFD:
  223. uli526x_media_mode = mode;
  224. break;
  225. default:
  226. uli526x_media_mode = ULI526X_AUTO;
  227. break;
  228. }
  229. /* Allocate Tx/Rx descriptor memory */
  230. db->desc_pool_ptr = (uchar *)&desc_pool_array[0];
  231. db->desc_pool_dma_ptr = (dma_addr_t)&desc_pool_array[0];
  232. if (db->desc_pool_ptr == NULL)
  233. return -1;
  234. db->buf_pool_ptr = (uchar *)&buf_pool[0];
  235. db->buf_pool_dma_ptr = (dma_addr_t)&buf_pool[0];
  236. if (db->buf_pool_ptr == NULL)
  237. return -1;
  238. db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
  239. db->first_tx_desc_dma = db->desc_pool_dma_ptr;
  240. db->buf_pool_start = db->buf_pool_ptr;
  241. db->buf_pool_dma_start = db->buf_pool_dma_ptr;
  242. #ifdef DEBUG
  243. printf("%s(): db->ioaddr= 0x%x\n",
  244. __FUNCTION__, db->ioaddr);
  245. printf("%s(): media_mode= 0x%x\n",
  246. __FUNCTION__, uli526x_media_mode);
  247. printf("%s(): db->desc_pool_ptr= 0x%x\n",
  248. __FUNCTION__, db->desc_pool_ptr);
  249. printf("%s(): db->desc_pool_dma_ptr= 0x%x\n",
  250. __FUNCTION__, db->desc_pool_dma_ptr);
  251. printf("%s(): db->buf_pool_ptr= 0x%x\n",
  252. __FUNCTION__, db->buf_pool_ptr);
  253. printf("%s(): db->buf_pool_dma_ptr= 0x%x\n",
  254. __FUNCTION__, db->buf_pool_dma_ptr);
  255. #endif
  256. /* read 64 word srom data */
  257. for (i = 0; i < 64; i++)
  258. ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr,
  259. i));
  260. /* Set Node address */
  261. if (((db->srom[0] == 0xff) && (db->srom[1] == 0xff)) ||
  262. ((db->srom[0] == 0x00) && (db->srom[1] == 0x00)))
  263. /* SROM absent, so write MAC address to ID Table */
  264. set_mac_addr(dev);
  265. else { /*Exist SROM*/
  266. for (i = 0; i < 6; i++)
  267. dev->enetaddr[i] = db->srom[20 + i];
  268. }
  269. #ifdef DEBUG
  270. for (i = 0; i < 6; i++)
  271. printf("%c%02x", i ? ':' : ' ', dev->enetaddr[i]);
  272. #endif
  273. db->PHY_reg4 = 0x1e0;
  274. /* system variable init */
  275. db->cr6_data = CR6_DEFAULT ;
  276. db->cr6_data |= ULI526X_TXTH_256;
  277. db->cr0_data = CR0_DEFAULT;
  278. uli526x_init(dev);
  279. return 0;
  280. }
  281. static void uli526x_disable(struct eth_device *dev)
  282. {
  283. #ifdef DEBUG
  284. printf("uli526x_disable\n");
  285. #endif
  286. struct uli526x_board_info *db = dev->priv;
  287. if (!((inl(db->ioaddr + DCR12)) & 0x8)) {
  288. /* Reset & stop ULI526X board */
  289. outl(ULI526X_RESET, db->ioaddr + DCR0);
  290. udelay(5);
  291. uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
  292. /* reset the board */
  293. db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
  294. update_cr6(db->cr6_data, dev->iobase);
  295. outl(0, dev->iobase + DCR7); /* Disable Interrupt */
  296. outl(inl(dev->iobase + DCR5), dev->iobase + DCR5);
  297. }
  298. }
  299. /* Initialize ULI526X board
  300. * Reset ULI526X board
  301. * Initialize TX/Rx descriptor chain structure
  302. * Send the set-up frame
  303. * Enable Tx/Rx machine
  304. */
  305. static void uli526x_init(struct eth_device *dev)
  306. {
  307. struct uli526x_board_info *db = dev->priv;
  308. u8 phy_tmp;
  309. u16 phy_value;
  310. u16 phy_reg_reset;
  311. /* Reset M526x MAC controller */
  312. outl(ULI526X_RESET, db->ioaddr + DCR0); /* RESET MAC */
  313. udelay(100);
  314. outl(db->cr0_data, db->ioaddr + DCR0);
  315. udelay(5);
  316. /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
  317. db->phy_addr = 1;
  318. db->tx_packet_cnt = 0;
  319. for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
  320. /* peer add */
  321. phy_value = uli_phy_read(db->ioaddr, phy_tmp, 3, db->chip_id);
  322. if (phy_value != 0xffff && phy_value != 0) {
  323. db->phy_addr = phy_tmp;
  324. break;
  325. }
  326. }
  327. #ifdef DEBUG
  328. printf("%s(): db->ioaddr= 0x%x\n", __FUNCTION__, db->ioaddr);
  329. printf("%s(): db->phy_addr= 0x%x\n", __FUNCTION__, db->phy_addr);
  330. #endif
  331. if (phy_tmp == 32)
  332. printf("Can not find the phy address!!!");
  333. /* Parser SROM and media mode */
  334. db->media_mode = uli526x_media_mode;
  335. if (!(inl(db->ioaddr + DCR12) & 0x8)) {
  336. /* Phyxcer capability setting */
  337. phy_reg_reset = uli_phy_read(db->ioaddr,
  338. db->phy_addr, 0, db->chip_id);
  339. phy_reg_reset = (phy_reg_reset | 0x8000);
  340. uli_phy_write(db->ioaddr, db->phy_addr, 0,
  341. phy_reg_reset, db->chip_id);
  342. udelay(500);
  343. /* Process Phyxcer Media Mode */
  344. uli526x_set_phyxcer(db);
  345. }
  346. /* Media Mode Process */
  347. if (!(db->media_mode & ULI526X_AUTO))
  348. db->op_mode = db->media_mode; /* Force Mode */
  349. /* Initialize Transmit/Receive decriptor and CR3/4 */
  350. uli526x_descriptor_init(db, db->ioaddr);
  351. /* Init CR6 to program M526X operation */
  352. update_cr6(db->cr6_data, db->ioaddr);
  353. /* Init CR7, interrupt active bit */
  354. db->cr7_data = CR7_DEFAULT;
  355. outl(db->cr7_data, db->ioaddr + DCR7);
  356. /* Init CR15, Tx jabber and Rx watchdog timer */
  357. outl(db->cr15_data, db->ioaddr + DCR15);
  358. /* Enable ULI526X Tx/Rx function */
  359. db->cr6_data |= CR6_RXSC | CR6_TXSC;
  360. update_cr6(db->cr6_data, db->ioaddr);
  361. while (!(inl(db->ioaddr + DCR12) & 0x8))
  362. udelay(10);
  363. }
  364. /*
  365. * Hardware start transmission.
  366. * Send a packet to media from the upper layer.
  367. */
  368. static int uli526x_start_xmit(struct eth_device *dev, void *packet, int length)
  369. {
  370. struct uli526x_board_info *db = dev->priv;
  371. struct tx_desc *txptr;
  372. unsigned int len = length;
  373. /* Too large packet check */
  374. if (len > MAX_PACKET_SIZE) {
  375. printf(": big packet = %d\n", len);
  376. return 0;
  377. }
  378. /* No Tx resource check, it never happen nromally */
  379. if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
  380. printf("No Tx resource %ld\n", db->tx_packet_cnt);
  381. return 0;
  382. }
  383. /* Disable NIC interrupt */
  384. outl(0, dev->iobase + DCR7);
  385. /* transmit this packet */
  386. txptr = db->tx_insert_ptr;
  387. memcpy((char *)txptr->tx_buf_ptr, (char *)packet, (int)length);
  388. txptr->tdes1 = cpu_to_le32(0xe1000000 | length);
  389. /* Point to next transmit free descriptor */
  390. db->tx_insert_ptr = txptr->next_tx_desc;
  391. /* Transmit Packet Process */
  392. if ((db->tx_packet_cnt < TX_DESC_CNT)) {
  393. txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
  394. db->tx_packet_cnt++; /* Ready to send */
  395. outl(0x1, dev->iobase + DCR1); /* Issue Tx polling */
  396. }
  397. /* Got ULI526X status */
  398. db->cr5_data = inl(db->ioaddr + DCR5);
  399. outl(db->cr5_data, db->ioaddr + DCR5);
  400. #ifdef TX_DEBUG
  401. printf("%s(): length = 0x%x\n", __FUNCTION__, length);
  402. printf("%s(): cr5_data=%x\n", __FUNCTION__, db->cr5_data);
  403. #endif
  404. outl(db->cr7_data, dev->iobase + DCR7);
  405. uli526x_free_tx_pkt(dev, db);
  406. return length;
  407. }
  408. /*
  409. * Free TX resource after TX complete
  410. */
  411. static void uli526x_free_tx_pkt(struct eth_device *dev,
  412. struct uli526x_board_info *db)
  413. {
  414. struct tx_desc *txptr;
  415. u32 tdes0;
  416. txptr = db->tx_remove_ptr;
  417. while (db->tx_packet_cnt) {
  418. tdes0 = le32_to_cpu(txptr->tdes0);
  419. /* printf(DRV_NAME ": tdes0=%x\n", tdes0); */
  420. if (tdes0 & 0x80000000)
  421. break;
  422. /* A packet sent completed */
  423. db->tx_packet_cnt--;
  424. if (tdes0 != 0x7fffffff) {
  425. #ifdef TX_DEBUG
  426. printf("%s()tdes0=%x\n", __FUNCTION__, tdes0);
  427. #endif
  428. if (tdes0 & TDES0_ERR_MASK) {
  429. if (tdes0 & 0x0002) { /* UnderRun */
  430. if (!(db->cr6_data & CR6_SFT)) {
  431. db->cr6_data = db->cr6_data |
  432. CR6_SFT;
  433. update_cr6(db->cr6_data,
  434. db->ioaddr);
  435. }
  436. }
  437. }
  438. }
  439. txptr = txptr->next_tx_desc;
  440. }/* End of while */
  441. /* Update TX remove pointer to next */
  442. db->tx_remove_ptr = txptr;
  443. }
  444. /*
  445. * Receive the come packet and pass to upper layer
  446. */
  447. static int uli526x_rx_packet(struct eth_device *dev)
  448. {
  449. struct uli526x_board_info *db = dev->priv;
  450. struct rx_desc *rxptr;
  451. int rxlen = 0;
  452. u32 rdes0;
  453. rxptr = db->rx_ready_ptr;
  454. rdes0 = le32_to_cpu(rxptr->rdes0);
  455. #ifdef RX_DEBUG
  456. printf("%s(): rxptr->rdes0=%x\n", __FUNCTION__, rxptr->rdes0);
  457. #endif
  458. if (!(rdes0 & 0x80000000)) { /* packet owner check */
  459. if ((rdes0 & 0x300) != 0x300) {
  460. /* A packet without First/Last flag */
  461. /* reuse this buf */
  462. printf("A packet without First/Last flag");
  463. uli526x_reuse_buf(rxptr);
  464. } else {
  465. /* A packet with First/Last flag */
  466. rxlen = ((rdes0 >> 16) & 0x3fff) - 4;
  467. #ifdef RX_DEBUG
  468. printf("%s(): rxlen =%x\n", __FUNCTION__, rxlen);
  469. #endif
  470. /* error summary bit check */
  471. if (rdes0 & 0x8000) {
  472. /* This is a error packet */
  473. printf("Error: rdes0: %x\n", rdes0);
  474. }
  475. if (!(rdes0 & 0x8000) ||
  476. ((db->cr6_data & CR6_PM) && (rxlen > 6))) {
  477. #ifdef RX_DEBUG
  478. printf("%s(): rx_skb_ptr =%x\n",
  479. __FUNCTION__, rxptr->rx_buf_ptr);
  480. printf("%s(): rxlen =%x\n",
  481. __FUNCTION__, rxlen);
  482. printf("%s(): buf addr =%x\n",
  483. __FUNCTION__, rxptr->rx_buf_ptr);
  484. printf("%s(): rxlen =%x\n",
  485. __FUNCTION__, rxlen);
  486. int i;
  487. for (i = 0; i < 0x20; i++)
  488. printf("%s(): data[%x] =%x\n",
  489. __FUNCTION__, i, rxptr->rx_buf_ptr[i]);
  490. #endif
  491. net_process_received_packet(
  492. (uchar *)rxptr->rx_buf_ptr, rxlen);
  493. uli526x_reuse_buf(rxptr);
  494. } else {
  495. /* Reuse SKB buffer when the packet is error */
  496. printf("Reuse buffer, rdes0");
  497. uli526x_reuse_buf(rxptr);
  498. }
  499. }
  500. rxptr = rxptr->next_rx_desc;
  501. }
  502. db->rx_ready_ptr = rxptr;
  503. return rxlen;
  504. }
  505. /*
  506. * Reuse the RX buffer
  507. */
  508. static void uli526x_reuse_buf(struct rx_desc *rxptr)
  509. {
  510. if (!(rxptr->rdes0 & cpu_to_le32(0x80000000)))
  511. rxptr->rdes0 = cpu_to_le32(0x80000000);
  512. else
  513. printf("Buffer reuse method error");
  514. }
  515. /*
  516. * Initialize transmit/Receive descriptor
  517. * Using Chain structure, and allocate Tx/Rx buffer
  518. */
  519. static void uli526x_descriptor_init(struct uli526x_board_info *db,
  520. unsigned long ioaddr)
  521. {
  522. struct tx_desc *tmp_tx;
  523. struct rx_desc *tmp_rx;
  524. unsigned char *tmp_buf;
  525. dma_addr_t tmp_tx_dma, tmp_rx_dma;
  526. dma_addr_t tmp_buf_dma;
  527. int i;
  528. /* tx descriptor start pointer */
  529. db->tx_insert_ptr = db->first_tx_desc;
  530. db->tx_remove_ptr = db->first_tx_desc;
  531. outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
  532. /* rx descriptor start pointer */
  533. db->first_rx_desc = (void *)db->first_tx_desc +
  534. sizeof(struct tx_desc) * TX_DESC_CNT;
  535. db->first_rx_desc_dma = db->first_tx_desc_dma +
  536. sizeof(struct tx_desc) * TX_DESC_CNT;
  537. db->rx_ready_ptr = db->first_rx_desc;
  538. outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
  539. #ifdef DEBUG
  540. printf("%s(): db->first_tx_desc= 0x%x\n",
  541. __FUNCTION__, db->first_tx_desc);
  542. printf("%s(): db->first_rx_desc_dma= 0x%x\n",
  543. __FUNCTION__, db->first_rx_desc_dma);
  544. #endif
  545. /* Init Transmit chain */
  546. tmp_buf = db->buf_pool_start;
  547. tmp_buf_dma = db->buf_pool_dma_start;
  548. tmp_tx_dma = db->first_tx_desc_dma;
  549. for (tmp_tx = db->first_tx_desc, i = 0;
  550. i < TX_DESC_CNT; i++, tmp_tx++) {
  551. tmp_tx->tx_buf_ptr = (char *)tmp_buf;
  552. tmp_tx->tdes0 = cpu_to_le32(0);
  553. tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
  554. tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
  555. tmp_tx_dma += sizeof(struct tx_desc);
  556. tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
  557. tmp_tx->next_tx_desc = tmp_tx + 1;
  558. tmp_buf = tmp_buf + TX_BUF_ALLOC;
  559. tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
  560. }
  561. (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
  562. tmp_tx->next_tx_desc = db->first_tx_desc;
  563. /* Init Receive descriptor chain */
  564. tmp_rx_dma = db->first_rx_desc_dma;
  565. for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT;
  566. i++, tmp_rx++) {
  567. tmp_rx->rdes0 = cpu_to_le32(0);
  568. tmp_rx->rdes1 = cpu_to_le32(0x01000600);
  569. tmp_rx_dma += sizeof(struct rx_desc);
  570. tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
  571. tmp_rx->next_rx_desc = tmp_rx + 1;
  572. }
  573. (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
  574. tmp_rx->next_rx_desc = db->first_rx_desc;
  575. /* pre-allocate Rx buffer */
  576. allocate_rx_buffer(db);
  577. }
  578. /*
  579. * Update CR6 value
  580. * Firstly stop ULI526X, then written value and start
  581. */
  582. static void update_cr6(u32 cr6_data, unsigned long ioaddr)
  583. {
  584. outl(cr6_data, ioaddr + DCR6);
  585. udelay(5);
  586. }
  587. /*
  588. * Allocate rx buffer,
  589. */
  590. static void allocate_rx_buffer(struct uli526x_board_info *db)
  591. {
  592. int index;
  593. struct rx_desc *rxptr;
  594. rxptr = db->first_rx_desc;
  595. u32 addr;
  596. for (index = 0; index < RX_DESC_CNT; index++) {
  597. addr = (u32)net_rx_packets[index];
  598. addr += (16 - (addr & 15));
  599. rxptr->rx_buf_ptr = (char *) addr;
  600. rxptr->rdes2 = cpu_to_le32(addr);
  601. rxptr->rdes0 = cpu_to_le32(0x80000000);
  602. #ifdef DEBUG
  603. printf("%s(): Number 0x%x:\n", __FUNCTION__, index);
  604. printf("%s(): addr 0x%x:\n", __FUNCTION__, addr);
  605. printf("%s(): rxptr address = 0x%x\n", __FUNCTION__, rxptr);
  606. printf("%s(): rxptr buf address = 0x%x\n", \
  607. __FUNCTION__, rxptr->rx_buf_ptr);
  608. printf("%s(): rdes2 = 0x%x\n", __FUNCTION__, rxptr->rdes2);
  609. #endif
  610. rxptr = rxptr->next_rx_desc;
  611. }
  612. }
  613. /*
  614. * Read one word data from the serial ROM
  615. */
  616. static u16 read_srom_word(long ioaddr, int offset)
  617. {
  618. int i;
  619. u16 srom_data = 0;
  620. long cr9_ioaddr = ioaddr + DCR9;
  621. outl(CR9_SROM_READ, cr9_ioaddr);
  622. outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
  623. /* Send the Read Command 110b */
  624. SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
  625. SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
  626. SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
  627. /* Send the offset */
  628. for (i = 5; i >= 0; i--) {
  629. srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
  630. SROM_CLK_WRITE(srom_data, cr9_ioaddr);
  631. }
  632. outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
  633. for (i = 16; i > 0; i--) {
  634. outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
  635. udelay(5);
  636. srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT)
  637. ? 1 : 0);
  638. outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
  639. udelay(5);
  640. }
  641. outl(CR9_SROM_READ, cr9_ioaddr);
  642. return srom_data;
  643. }
  644. /*
  645. * Set 10/100 phyxcer capability
  646. * AUTO mode : phyxcer register4 is NIC capability
  647. * Force mode: phyxcer register4 is the force media
  648. */
  649. static void uli526x_set_phyxcer(struct uli526x_board_info *db)
  650. {
  651. u16 phy_reg;
  652. /* Phyxcer capability setting */
  653. phy_reg = uli_phy_read(db->ioaddr,
  654. db->phy_addr, 4, db->chip_id) & ~0x01e0;
  655. if (db->media_mode & ULI526X_AUTO) {
  656. /* AUTO Mode */
  657. phy_reg |= db->PHY_reg4;
  658. } else {
  659. /* Force Mode */
  660. switch (db->media_mode) {
  661. case ULI526X_10MHF: phy_reg |= 0x20; break;
  662. case ULI526X_10MFD: phy_reg |= 0x40; break;
  663. case ULI526X_100MHF: phy_reg |= 0x80; break;
  664. case ULI526X_100MFD: phy_reg |= 0x100; break;
  665. }
  666. }
  667. /* Write new capability to Phyxcer Reg4 */
  668. if (!(phy_reg & 0x01e0)) {
  669. phy_reg |= db->PHY_reg4;
  670. db->media_mode |= ULI526X_AUTO;
  671. }
  672. uli_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
  673. /* Restart Auto-Negotiation */
  674. uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
  675. udelay(50);
  676. }
  677. /*
  678. * Write a word to Phy register
  679. */
  680. static void uli_phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
  681. u16 phy_data, u32 chip_id)
  682. {
  683. u16 i;
  684. unsigned long ioaddr;
  685. if (chip_id == PCI_ULI5263_ID) {
  686. phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
  687. return;
  688. }
  689. /* M5261/M5263 Chip */
  690. ioaddr = iobase + DCR9;
  691. /* Send 33 synchronization clock to Phy controller */
  692. for (i = 0; i < 35; i++)
  693. phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
  694. /* Send start command(01) to Phy */
  695. phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
  696. phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
  697. /* Send write command(01) to Phy */
  698. phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
  699. phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
  700. /* Send Phy address */
  701. for (i = 0x10; i > 0; i = i >> 1)
  702. phy_write_1bit(ioaddr, phy_addr & i ?
  703. PHY_DATA_1 : PHY_DATA_0, chip_id);
  704. /* Send register address */
  705. for (i = 0x10; i > 0; i = i >> 1)
  706. phy_write_1bit(ioaddr, offset & i ?
  707. PHY_DATA_1 : PHY_DATA_0, chip_id);
  708. /* written trasnition */
  709. phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
  710. phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
  711. /* Write a word data to PHY controller */
  712. for (i = 0x8000; i > 0; i >>= 1)
  713. phy_write_1bit(ioaddr, phy_data & i ?
  714. PHY_DATA_1 : PHY_DATA_0, chip_id);
  715. }
  716. /*
  717. * Read a word data from phy register
  718. */
  719. static u16 uli_phy_read(unsigned long iobase, u8 phy_addr, u8 offset,
  720. u32 chip_id)
  721. {
  722. int i;
  723. u16 phy_data;
  724. unsigned long ioaddr;
  725. if (chip_id == PCI_ULI5263_ID)
  726. return phy_readby_cr10(iobase, phy_addr, offset);
  727. /* M5261/M5263 Chip */
  728. ioaddr = iobase + DCR9;
  729. /* Send 33 synchronization clock to Phy controller */
  730. for (i = 0; i < 35; i++)
  731. phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
  732. /* Send start command(01) to Phy */
  733. phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
  734. phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
  735. /* Send read command(10) to Phy */
  736. phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
  737. phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
  738. /* Send Phy address */
  739. for (i = 0x10; i > 0; i = i >> 1)
  740. phy_write_1bit(ioaddr, phy_addr & i ?
  741. PHY_DATA_1 : PHY_DATA_0, chip_id);
  742. /* Send register address */
  743. for (i = 0x10; i > 0; i = i >> 1)
  744. phy_write_1bit(ioaddr, offset & i ?
  745. PHY_DATA_1 : PHY_DATA_0, chip_id);
  746. /* Skip transition state */
  747. phy_read_1bit(ioaddr, chip_id);
  748. /* read 16bit data */
  749. for (phy_data = 0, i = 0; i < 16; i++) {
  750. phy_data <<= 1;
  751. phy_data |= phy_read_1bit(ioaddr, chip_id);
  752. }
  753. return phy_data;
  754. }
  755. static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
  756. {
  757. unsigned long ioaddr, cr10_value;
  758. ioaddr = iobase + DCR10;
  759. cr10_value = phy_addr;
  760. cr10_value = (cr10_value<<5) + offset;
  761. cr10_value = (cr10_value<<16) + 0x08000000;
  762. outl(cr10_value, ioaddr);
  763. udelay(1);
  764. while (1) {
  765. cr10_value = inl(ioaddr);
  766. if (cr10_value & 0x10000000)
  767. break;
  768. }
  769. return (cr10_value&0x0ffff);
  770. }
  771. static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr,
  772. u8 offset, u16 phy_data)
  773. {
  774. unsigned long ioaddr, cr10_value;
  775. ioaddr = iobase + DCR10;
  776. cr10_value = phy_addr;
  777. cr10_value = (cr10_value<<5) + offset;
  778. cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
  779. outl(cr10_value, ioaddr);
  780. udelay(1);
  781. }
  782. /*
  783. * Write one bit data to Phy Controller
  784. */
  785. static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
  786. {
  787. outl(phy_data , ioaddr); /* MII Clock Low */
  788. udelay(1);
  789. outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
  790. udelay(1);
  791. outl(phy_data , ioaddr); /* MII Clock Low */
  792. udelay(1);
  793. }
  794. /*
  795. * Read one bit phy data from PHY controller
  796. */
  797. static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
  798. {
  799. u16 phy_data;
  800. outl(0x50000 , ioaddr);
  801. udelay(1);
  802. phy_data = (inl(ioaddr) >> 19) & 0x1;
  803. outl(0x40000 , ioaddr);
  804. udelay(1);
  805. return phy_data;
  806. }
  807. /*
  808. * Set MAC address to ID Table
  809. */
  810. static void set_mac_addr(struct eth_device *dev)
  811. {
  812. int i;
  813. u16 addr;
  814. struct uli526x_board_info *db = dev->priv;
  815. outl(0x10000, db->ioaddr + DCR0); /* Diagnosis mode */
  816. /* Reset dianostic pointer port */
  817. outl(0x1c0, db->ioaddr + DCR13);
  818. outl(0, db->ioaddr + DCR14); /* Clear reset port */
  819. outl(0x10, db->ioaddr + DCR14); /* Reset ID Table pointer */
  820. outl(0, db->ioaddr + DCR14); /* Clear reset port */
  821. outl(0, db->ioaddr + DCR13); /* Clear CR13 */
  822. /* Select ID Table access port */
  823. outl(0x1b0, db->ioaddr + DCR13);
  824. /* Read MAC address from CR14 */
  825. for (i = 0; i < 3; i++) {
  826. addr = dev->enetaddr[2 * i] | (dev->enetaddr[2 * i + 1] << 8);
  827. outl(addr, db->ioaddr + DCR14);
  828. }
  829. /* write end */
  830. outl(0, db->ioaddr + DCR13); /* Clear CR13 */
  831. outl(0, db->ioaddr + DCR0); /* Clear CR0 */
  832. udelay(10);
  833. return;
  834. }