sunxi_emac.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * sunxi_emac.c -- Allwinner A10 ethernet driver
  4. *
  5. * (C) Copyright 2012, Stefan Roese <sr@denx.de>
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <dm.h>
  10. #include <linux/err.h>
  11. #include <malloc.h>
  12. #include <miiphy.h>
  13. #include <net.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/clock.h>
  16. #include <asm/arch/gpio.h>
  17. /* EMAC register */
  18. struct emac_regs {
  19. u32 ctl; /* 0x00 */
  20. u32 tx_mode; /* 0x04 */
  21. u32 tx_flow; /* 0x08 */
  22. u32 tx_ctl0; /* 0x0c */
  23. u32 tx_ctl1; /* 0x10 */
  24. u32 tx_ins; /* 0x14 */
  25. u32 tx_pl0; /* 0x18 */
  26. u32 tx_pl1; /* 0x1c */
  27. u32 tx_sta; /* 0x20 */
  28. u32 tx_io_data; /* 0x24 */
  29. u32 tx_io_data1;/* 0x28 */
  30. u32 tx_tsvl0; /* 0x2c */
  31. u32 tx_tsvh0; /* 0x30 */
  32. u32 tx_tsvl1; /* 0x34 */
  33. u32 tx_tsvh1; /* 0x38 */
  34. u32 rx_ctl; /* 0x3c */
  35. u32 rx_hash0; /* 0x40 */
  36. u32 rx_hash1; /* 0x44 */
  37. u32 rx_sta; /* 0x48 */
  38. u32 rx_io_data; /* 0x4c */
  39. u32 rx_fbc; /* 0x50 */
  40. u32 int_ctl; /* 0x54 */
  41. u32 int_sta; /* 0x58 */
  42. u32 mac_ctl0; /* 0x5c */
  43. u32 mac_ctl1; /* 0x60 */
  44. u32 mac_ipgt; /* 0x64 */
  45. u32 mac_ipgr; /* 0x68 */
  46. u32 mac_clrt; /* 0x6c */
  47. u32 mac_maxf; /* 0x70 */
  48. u32 mac_supp; /* 0x74 */
  49. u32 mac_test; /* 0x78 */
  50. u32 mac_mcfg; /* 0x7c */
  51. u32 mac_mcmd; /* 0x80 */
  52. u32 mac_madr; /* 0x84 */
  53. u32 mac_mwtd; /* 0x88 */
  54. u32 mac_mrdd; /* 0x8c */
  55. u32 mac_mind; /* 0x90 */
  56. u32 mac_ssrr; /* 0x94 */
  57. u32 mac_a0; /* 0x98 */
  58. u32 mac_a1; /* 0x9c */
  59. };
  60. /* SRAMC register */
  61. struct sunxi_sramc_regs {
  62. u32 ctrl0;
  63. u32 ctrl1;
  64. };
  65. /* 0: Disable 1: Aborted frame enable(default) */
  66. #define EMAC_TX_AB_M (0x1 << 0)
  67. /* 0: CPU 1: DMA(default) */
  68. #define EMAC_TX_TM (0x1 << 1)
  69. #define EMAC_TX_SETUP (0)
  70. /* 0: DRQ asserted 1: DRQ automatically(default) */
  71. #define EMAC_RX_DRQ_MODE (0x1 << 1)
  72. /* 0: CPU 1: DMA(default) */
  73. #define EMAC_RX_TM (0x1 << 2)
  74. /* 0: Normal(default) 1: Pass all Frames */
  75. #define EMAC_RX_PA (0x1 << 4)
  76. /* 0: Normal(default) 1: Pass Control Frames */
  77. #define EMAC_RX_PCF (0x1 << 5)
  78. /* 0: Normal(default) 1: Pass Frames with CRC Error */
  79. #define EMAC_RX_PCRCE (0x1 << 6)
  80. /* 0: Normal(default) 1: Pass Frames with Length Error */
  81. #define EMAC_RX_PLE (0x1 << 7)
  82. /* 0: Normal 1: Pass Frames length out of range(default) */
  83. #define EMAC_RX_POR (0x1 << 8)
  84. /* 0: Not accept 1: Accept unicast Packets(default) */
  85. #define EMAC_RX_UCAD (0x1 << 16)
  86. /* 0: Normal(default) 1: DA Filtering */
  87. #define EMAC_RX_DAF (0x1 << 17)
  88. /* 0: Not accept 1: Accept multicast Packets(default) */
  89. #define EMAC_RX_MCO (0x1 << 20)
  90. /* 0: Disable(default) 1: Enable Hash filter */
  91. #define EMAC_RX_MHF (0x1 << 21)
  92. /* 0: Not accept 1: Accept Broadcast Packets(default) */
  93. #define EMAC_RX_BCO (0x1 << 22)
  94. /* 0: Disable(default) 1: Enable SA Filtering */
  95. #define EMAC_RX_SAF (0x1 << 24)
  96. /* 0: Normal(default) 1: Inverse Filtering */
  97. #define EMAC_RX_SAIF (0x1 << 25)
  98. #define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
  99. EMAC_RX_MCO | EMAC_RX_BCO)
  100. /* 0: Disable 1: Enable Receive Flow Control(default) */
  101. #define EMAC_MAC_CTL0_RFC (0x1 << 2)
  102. /* 0: Disable 1: Enable Transmit Flow Control(default) */
  103. #define EMAC_MAC_CTL0_TFC (0x1 << 3)
  104. #define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)
  105. /* 0: Disable 1: Enable MAC Frame Length Checking(default) */
  106. #define EMAC_MAC_CTL1_FLC (0x1 << 1)
  107. /* 0: Disable(default) 1: Enable Huge Frame */
  108. #define EMAC_MAC_CTL1_HF (0x1 << 2)
  109. /* 0: Disable(default) 1: Enable MAC Delayed CRC */
  110. #define EMAC_MAC_CTL1_DCRC (0x1 << 3)
  111. /* 0: Disable 1: Enable MAC CRC(default) */
  112. #define EMAC_MAC_CTL1_CRC (0x1 << 4)
  113. /* 0: Disable 1: Enable MAC PAD Short frames(default) */
  114. #define EMAC_MAC_CTL1_PC (0x1 << 5)
  115. /* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */
  116. #define EMAC_MAC_CTL1_VC (0x1 << 6)
  117. /* 0: Disable(default) 1: Enable MAC auto detect Short frames */
  118. #define EMAC_MAC_CTL1_ADP (0x1 << 7)
  119. /* 0: Disable(default) 1: Enable */
  120. #define EMAC_MAC_CTL1_PRE (0x1 << 8)
  121. /* 0: Disable(default) 1: Enable */
  122. #define EMAC_MAC_CTL1_LPE (0x1 << 9)
  123. /* 0: Disable(default) 1: Enable no back off */
  124. #define EMAC_MAC_CTL1_NB (0x1 << 12)
  125. /* 0: Disable(default) 1: Enable */
  126. #define EMAC_MAC_CTL1_BNB (0x1 << 13)
  127. /* 0: Disable(default) 1: Enable */
  128. #define EMAC_MAC_CTL1_ED (0x1 << 14)
  129. #define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
  130. EMAC_MAC_CTL1_PC)
  131. #define EMAC_MAC_IPGT 0x15
  132. #define EMAC_MAC_NBTB_IPG1 0xc
  133. #define EMAC_MAC_NBTB_IPG2 0x12
  134. #define EMAC_MAC_CW 0x37
  135. #define EMAC_MAC_RM 0xf
  136. #define EMAC_MAC_MFL 0x0600
  137. /* Receive status */
  138. #define EMAC_CRCERR (0x1 << 4)
  139. #define EMAC_LENERR (0x3 << 5)
  140. #define EMAC_RX_BUFSIZE 2000
  141. struct emac_eth_dev {
  142. struct emac_regs *regs;
  143. struct clk clk;
  144. struct mii_dev *bus;
  145. struct phy_device *phydev;
  146. int link_printed;
  147. #ifdef CONFIG_DM_ETH
  148. uchar rx_buf[EMAC_RX_BUFSIZE];
  149. #endif
  150. };
  151. struct emac_rxhdr {
  152. s16 rx_len;
  153. u16 rx_status;
  154. };
  155. static void emac_inblk_32bit(void *reg, void *data, int count)
  156. {
  157. int cnt = (count + 3) >> 2;
  158. if (cnt) {
  159. u32 *buf = data;
  160. do {
  161. u32 x = readl(reg);
  162. *buf++ = x;
  163. } while (--cnt);
  164. }
  165. }
  166. static void emac_outblk_32bit(void *reg, void *data, int count)
  167. {
  168. int cnt = (count + 3) >> 2;
  169. if (cnt) {
  170. const u32 *buf = data;
  171. do {
  172. writel(*buf++, reg);
  173. } while (--cnt);
  174. }
  175. }
  176. /* Read a word from phyxcer */
  177. static int emac_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  178. {
  179. struct emac_eth_dev *priv = bus->priv;
  180. struct emac_regs *regs = priv->regs;
  181. /* issue the phy address and reg */
  182. writel(addr << 8 | reg, &regs->mac_madr);
  183. /* pull up the phy io line */
  184. writel(0x1, &regs->mac_mcmd);
  185. /* Wait read complete */
  186. mdelay(1);
  187. /* push down the phy io line */
  188. writel(0x0, &regs->mac_mcmd);
  189. /* And read data */
  190. return readl(&regs->mac_mrdd);
  191. }
  192. /* Write a word to phyxcer */
  193. static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  194. u16 value)
  195. {
  196. struct emac_eth_dev *priv = bus->priv;
  197. struct emac_regs *regs = priv->regs;
  198. /* issue the phy address and reg */
  199. writel(addr << 8 | reg, &regs->mac_madr);
  200. /* pull up the phy io line */
  201. writel(0x1, &regs->mac_mcmd);
  202. /* Wait write complete */
  203. mdelay(1);
  204. /* push down the phy io line */
  205. writel(0x0, &regs->mac_mcmd);
  206. /* and write data */
  207. writel(value, &regs->mac_mwtd);
  208. return 0;
  209. }
  210. static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev)
  211. {
  212. int ret, mask = 0xffffffff;
  213. #ifdef CONFIG_PHY_ADDR
  214. mask = 1 << CONFIG_PHY_ADDR;
  215. #endif
  216. priv->bus = mdio_alloc();
  217. if (!priv->bus) {
  218. printf("Failed to allocate MDIO bus\n");
  219. return -ENOMEM;
  220. }
  221. priv->bus->read = emac_mdio_read;
  222. priv->bus->write = emac_mdio_write;
  223. priv->bus->priv = priv;
  224. strcpy(priv->bus->name, "emac");
  225. ret = mdio_register(priv->bus);
  226. if (ret)
  227. return ret;
  228. priv->phydev = phy_find_by_mask(priv->bus, mask,
  229. PHY_INTERFACE_MODE_MII);
  230. if (!priv->phydev)
  231. return -ENODEV;
  232. phy_connect_dev(priv->phydev, dev);
  233. phy_config(priv->phydev);
  234. return 0;
  235. }
  236. static void emac_setup(struct emac_eth_dev *priv)
  237. {
  238. struct emac_regs *regs = priv->regs;
  239. u32 reg_val;
  240. /* Set up TX */
  241. writel(EMAC_TX_SETUP, &regs->tx_mode);
  242. /* Set up RX */
  243. writel(EMAC_RX_SETUP, &regs->rx_ctl);
  244. /* Set MAC */
  245. /* Set MAC CTL0 */
  246. writel(EMAC_MAC_CTL0_SETUP, &regs->mac_ctl0);
  247. /* Set MAC CTL1 */
  248. reg_val = 0;
  249. if (priv->phydev->duplex == DUPLEX_FULL)
  250. reg_val = (0x1 << 0);
  251. writel(EMAC_MAC_CTL1_SETUP | reg_val, &regs->mac_ctl1);
  252. /* Set up IPGT */
  253. writel(EMAC_MAC_IPGT, &regs->mac_ipgt);
  254. /* Set up IPGR */
  255. writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), &regs->mac_ipgr);
  256. /* Set up Collison window */
  257. writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), &regs->mac_clrt);
  258. /* Set up Max Frame Length */
  259. writel(EMAC_MAC_MFL, &regs->mac_maxf);
  260. }
  261. static void emac_reset(struct emac_eth_dev *priv)
  262. {
  263. struct emac_regs *regs = priv->regs;
  264. debug("resetting device\n");
  265. /* RESET device */
  266. writel(0, &regs->ctl);
  267. udelay(200);
  268. writel(1, &regs->ctl);
  269. udelay(200);
  270. }
  271. static int _sunxi_write_hwaddr(struct emac_eth_dev *priv, u8 *enetaddr)
  272. {
  273. struct emac_regs *regs = priv->regs;
  274. u32 enetaddr_lo, enetaddr_hi;
  275. enetaddr_lo = enetaddr[2] | (enetaddr[1] << 8) | (enetaddr[0] << 16);
  276. enetaddr_hi = enetaddr[5] | (enetaddr[4] << 8) | (enetaddr[3] << 16);
  277. writel(enetaddr_hi, &regs->mac_a0);
  278. writel(enetaddr_lo, &regs->mac_a1);
  279. return 0;
  280. }
  281. static int _sunxi_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
  282. {
  283. struct emac_regs *regs = priv->regs;
  284. int ret;
  285. /* Init EMAC */
  286. /* Flush RX FIFO */
  287. setbits_le32(&regs->rx_ctl, 0x8);
  288. udelay(1);
  289. /* Init MAC */
  290. /* Soft reset MAC */
  291. clrbits_le32(&regs->mac_ctl0, 0x1 << 15);
  292. /* Clear RX counter */
  293. writel(0x0, &regs->rx_fbc);
  294. udelay(1);
  295. /* Set up EMAC */
  296. emac_setup(priv);
  297. _sunxi_write_hwaddr(priv, enetaddr);
  298. mdelay(1);
  299. emac_reset(priv);
  300. /* PHY POWER UP */
  301. ret = phy_startup(priv->phydev);
  302. if (ret) {
  303. printf("Could not initialize PHY %s\n",
  304. priv->phydev->dev->name);
  305. return ret;
  306. }
  307. /* Print link status only once */
  308. if (!priv->link_printed) {
  309. printf("ENET Speed is %d Mbps - %s duplex connection\n",
  310. priv->phydev->speed,
  311. priv->phydev->duplex ? "FULL" : "HALF");
  312. priv->link_printed = 1;
  313. }
  314. /* Set EMAC SPEED depend on PHY */
  315. if (priv->phydev->speed == SPEED_100)
  316. setbits_le32(&regs->mac_supp, 1 << 8);
  317. else
  318. clrbits_le32(&regs->mac_supp, 1 << 8);
  319. /* Set duplex depend on phy */
  320. if (priv->phydev->duplex == DUPLEX_FULL)
  321. setbits_le32(&regs->mac_ctl1, 1 << 0);
  322. else
  323. clrbits_le32(&regs->mac_ctl1, 1 << 0);
  324. /* Enable RX/TX */
  325. setbits_le32(&regs->ctl, 0x7);
  326. return 0;
  327. }
  328. static int _sunxi_emac_eth_recv(struct emac_eth_dev *priv, void *packet)
  329. {
  330. struct emac_regs *regs = priv->regs;
  331. struct emac_rxhdr rxhdr;
  332. u32 rxcount;
  333. u32 reg_val;
  334. int rx_len;
  335. int rx_status;
  336. int good_packet;
  337. /* Check packet ready or not */
  338. /* Race warning: The first packet might arrive with
  339. * the interrupts disabled, but the second will fix
  340. */
  341. rxcount = readl(&regs->rx_fbc);
  342. if (!rxcount) {
  343. /* Had one stuck? */
  344. rxcount = readl(&regs->rx_fbc);
  345. if (!rxcount)
  346. return -EAGAIN;
  347. }
  348. reg_val = readl(&regs->rx_io_data);
  349. if (reg_val != 0x0143414d) {
  350. /* Disable RX */
  351. clrbits_le32(&regs->ctl, 0x1 << 2);
  352. /* Flush RX FIFO */
  353. setbits_le32(&regs->rx_ctl, 0x1 << 3);
  354. while (readl(&regs->rx_ctl) & (0x1 << 3))
  355. ;
  356. /* Enable RX */
  357. setbits_le32(&regs->ctl, 0x1 << 2);
  358. return -EAGAIN;
  359. }
  360. /* A packet ready now
  361. * Get status/length
  362. */
  363. good_packet = 1;
  364. emac_inblk_32bit(&regs->rx_io_data, &rxhdr, sizeof(rxhdr));
  365. rx_len = rxhdr.rx_len;
  366. rx_status = rxhdr.rx_status;
  367. /* Packet Status check */
  368. if (rx_len < 0x40) {
  369. good_packet = 0;
  370. debug("RX: Bad Packet (runt)\n");
  371. }
  372. /* rx_status is identical to RSR register. */
  373. if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) {
  374. good_packet = 0;
  375. if (rx_status & EMAC_CRCERR)
  376. printf("crc error\n");
  377. if (rx_status & EMAC_LENERR)
  378. printf("length error\n");
  379. }
  380. /* Move data from EMAC */
  381. if (good_packet) {
  382. if (rx_len > EMAC_RX_BUFSIZE) {
  383. printf("Received packet is too big (len=%d)\n", rx_len);
  384. return -EMSGSIZE;
  385. }
  386. emac_inblk_32bit((void *)&regs->rx_io_data, packet, rx_len);
  387. return rx_len;
  388. }
  389. return -EIO; /* Bad packet */
  390. }
  391. static int _sunxi_emac_eth_send(struct emac_eth_dev *priv, void *packet,
  392. int len)
  393. {
  394. struct emac_regs *regs = priv->regs;
  395. /* Select channel 0 */
  396. writel(0, &regs->tx_ins);
  397. /* Write packet */
  398. emac_outblk_32bit((void *)&regs->tx_io_data, packet, len);
  399. /* Set TX len */
  400. writel(len, &regs->tx_pl0);
  401. /* Start translate from fifo to phy */
  402. setbits_le32(&regs->tx_ctl0, 1);
  403. return 0;
  404. }
  405. static int sunxi_emac_board_setup(struct emac_eth_dev *priv)
  406. {
  407. struct sunxi_sramc_regs *sram =
  408. (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
  409. struct emac_regs *regs = priv->regs;
  410. int pin, ret;
  411. /* Map SRAM to EMAC */
  412. setbits_le32(&sram->ctrl1, 0x5 << 2);
  413. /* Configure pin mux settings for MII Ethernet */
  414. for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
  415. sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
  416. /* Set up clock gating */
  417. ret = clk_enable(&priv->clk);
  418. if (ret) {
  419. dev_err(dev, "failed to enable emac clock\n");
  420. return ret;
  421. }
  422. /* Set MII clock */
  423. clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2);
  424. return 0;
  425. }
  426. static int sunxi_emac_eth_start(struct udevice *dev)
  427. {
  428. struct eth_pdata *pdata = dev_get_platdata(dev);
  429. return _sunxi_emac_eth_init(dev->priv, pdata->enetaddr);
  430. }
  431. static int sunxi_emac_eth_send(struct udevice *dev, void *packet, int length)
  432. {
  433. struct emac_eth_dev *priv = dev_get_priv(dev);
  434. return _sunxi_emac_eth_send(priv, packet, length);
  435. }
  436. static int sunxi_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  437. {
  438. struct emac_eth_dev *priv = dev_get_priv(dev);
  439. int rx_len;
  440. rx_len = _sunxi_emac_eth_recv(priv, priv->rx_buf);
  441. *packetp = priv->rx_buf;
  442. return rx_len;
  443. }
  444. static void sunxi_emac_eth_stop(struct udevice *dev)
  445. {
  446. /* Nothing to do here */
  447. }
  448. static int sunxi_emac_eth_probe(struct udevice *dev)
  449. {
  450. struct eth_pdata *pdata = dev_get_platdata(dev);
  451. struct emac_eth_dev *priv = dev_get_priv(dev);
  452. int ret;
  453. priv->regs = (struct emac_regs *)pdata->iobase;
  454. ret = clk_get_by_index(dev, 0, &priv->clk);
  455. if (ret) {
  456. dev_err(dev, "failed to get emac clock\n");
  457. return ret;
  458. }
  459. ret = sunxi_emac_board_setup(priv);
  460. if (ret)
  461. return ret;
  462. return sunxi_emac_init_phy(priv, dev);
  463. }
  464. static const struct eth_ops sunxi_emac_eth_ops = {
  465. .start = sunxi_emac_eth_start,
  466. .send = sunxi_emac_eth_send,
  467. .recv = sunxi_emac_eth_recv,
  468. .stop = sunxi_emac_eth_stop,
  469. };
  470. static int sunxi_emac_eth_ofdata_to_platdata(struct udevice *dev)
  471. {
  472. struct eth_pdata *pdata = dev_get_platdata(dev);
  473. pdata->iobase = devfdt_get_addr(dev);
  474. return 0;
  475. }
  476. static const struct udevice_id sunxi_emac_eth_ids[] = {
  477. { .compatible = "allwinner,sun4i-a10-emac" },
  478. { }
  479. };
  480. U_BOOT_DRIVER(eth_sunxi_emac) = {
  481. .name = "eth_sunxi_emac",
  482. .id = UCLASS_ETH,
  483. .of_match = sunxi_emac_eth_ids,
  484. .ofdata_to_platdata = sunxi_emac_eth_ofdata_to_platdata,
  485. .probe = sunxi_emac_eth_probe,
  486. .ops = &sunxi_emac_eth_ops,
  487. .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
  488. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  489. };