sni_ave.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /**
  3. * sni_ave.c - Socionext UniPhier AVE ethernet driver
  4. * Copyright 2016-2018 Socionext inc.
  5. */
  6. #include <clk.h>
  7. #include <dm.h>
  8. #include <fdt_support.h>
  9. #include <linux/io.h>
  10. #include <linux/iopoll.h>
  11. #include <miiphy.h>
  12. #include <net.h>
  13. #include <regmap.h>
  14. #include <reset.h>
  15. #include <syscon.h>
  16. #define AVE_GRST_DELAY_MSEC 40
  17. #define AVE_MIN_XMITSIZE 60
  18. #define AVE_SEND_TIMEOUT_COUNT 1000
  19. #define AVE_MDIO_TIMEOUT_USEC 10000
  20. #define AVE_HALT_TIMEOUT_USEC 10000
  21. /* General Register Group */
  22. #define AVE_IDR 0x000 /* ID */
  23. #define AVE_VR 0x004 /* Version */
  24. #define AVE_GRR 0x008 /* Global Reset */
  25. #define AVE_CFGR 0x00c /* Configuration */
  26. /* Interrupt Register Group */
  27. #define AVE_GIMR 0x100 /* Global Interrupt Mask */
  28. #define AVE_GISR 0x104 /* Global Interrupt Status */
  29. /* MAC Register Group */
  30. #define AVE_TXCR 0x200 /* TX Setup */
  31. #define AVE_RXCR 0x204 /* RX Setup */
  32. #define AVE_RXMAC1R 0x208 /* MAC address (lower) */
  33. #define AVE_RXMAC2R 0x20c /* MAC address (upper) */
  34. #define AVE_MDIOCTR 0x214 /* MDIO Control */
  35. #define AVE_MDIOAR 0x218 /* MDIO Address */
  36. #define AVE_MDIOWDR 0x21c /* MDIO Data */
  37. #define AVE_MDIOSR 0x220 /* MDIO Status */
  38. #define AVE_MDIORDR 0x224 /* MDIO Rd Data */
  39. /* Descriptor Control Register Group */
  40. #define AVE_DESCC 0x300 /* Descriptor Control */
  41. #define AVE_TXDC 0x304 /* TX Descriptor Configuration */
  42. #define AVE_RXDC 0x308 /* RX Descriptor Ring0 Configuration */
  43. #define AVE_IIRQC 0x34c /* Interval IRQ Control */
  44. /* 64bit descriptor memory */
  45. #define AVE_DESC_SIZE_64 12 /* Descriptor Size */
  46. #define AVE_TXDM_64 0x1000 /* Tx Descriptor Memory */
  47. #define AVE_RXDM_64 0x1c00 /* Rx Descriptor Memory */
  48. /* 32bit descriptor memory */
  49. #define AVE_DESC_SIZE_32 8 /* Descriptor Size */
  50. #define AVE_TXDM_32 0x1000 /* Tx Descriptor Memory */
  51. #define AVE_RXDM_32 0x1800 /* Rx Descriptor Memory */
  52. /* RMII Bridge Register Group */
  53. #define AVE_RSTCTRL 0x8028 /* Reset control */
  54. #define AVE_RSTCTRL_RMIIRST BIT(16)
  55. #define AVE_LINKSEL 0x8034 /* Link speed setting */
  56. #define AVE_LINKSEL_100M BIT(0)
  57. /* AVE_GRR */
  58. #define AVE_GRR_PHYRST BIT(4) /* Reset external PHY */
  59. #define AVE_GRR_GRST BIT(0) /* Reset all MAC */
  60. /* AVE_CFGR */
  61. #define AVE_CFGR_MII BIT(27) /* Func mode (1:MII/RMII, 0:RGMII) */
  62. /* AVE_GISR (common with GIMR) */
  63. #define AVE_GIMR_CLR 0
  64. #define AVE_GISR_CLR GENMASK(31, 0)
  65. /* AVE_TXCR */
  66. #define AVE_TXCR_FLOCTR BIT(18) /* Flow control */
  67. #define AVE_TXCR_TXSPD_1G BIT(17)
  68. #define AVE_TXCR_TXSPD_100 BIT(16)
  69. /* AVE_RXCR */
  70. #define AVE_RXCR_RXEN BIT(30) /* Rx enable */
  71. #define AVE_RXCR_FDUPEN BIT(22) /* Interface mode */
  72. #define AVE_RXCR_FLOCTR BIT(21) /* Flow control */
  73. /* AVE_MDIOCTR */
  74. #define AVE_MDIOCTR_RREQ BIT(3) /* Read request */
  75. #define AVE_MDIOCTR_WREQ BIT(2) /* Write request */
  76. /* AVE_MDIOSR */
  77. #define AVE_MDIOSR_STS BIT(0) /* access status */
  78. /* AVE_DESCC */
  79. #define AVE_DESCC_RXDSTPSTS BIT(20)
  80. #define AVE_DESCC_RD0 BIT(8) /* Enable Rx descriptor Ring0 */
  81. #define AVE_DESCC_RXDSTP BIT(4) /* Pause Rx descriptor */
  82. #define AVE_DESCC_TD BIT(0) /* Enable Tx descriptor */
  83. /* AVE_TXDC/RXDC */
  84. #define AVE_DESC_SIZE(priv, num) \
  85. ((num) * ((priv)->data->is_desc_64bit ? AVE_DESC_SIZE_64 : \
  86. AVE_DESC_SIZE_32))
  87. /* Command status for descriptor */
  88. #define AVE_STS_OWN BIT(31) /* Descriptor ownership */
  89. #define AVE_STS_OK BIT(27) /* Normal transmit */
  90. #define AVE_STS_1ST BIT(26) /* Head of buffer chain */
  91. #define AVE_STS_LAST BIT(25) /* Tail of buffer chain */
  92. #define AVE_STS_PKTLEN_TX_MASK GENMASK(15, 0)
  93. #define AVE_STS_PKTLEN_RX_MASK GENMASK(10, 0)
  94. #define AVE_DESC_OFS_CMDSTS 0
  95. #define AVE_DESC_OFS_ADDRL 4
  96. #define AVE_DESC_OFS_ADDRU 8
  97. /* Parameter for ethernet frame */
  98. #define AVE_RXCR_MTU 1518
  99. /* SG */
  100. #define SG_ETPINMODE 0x540
  101. #define SG_ETPINMODE_EXTPHY BIT(1) /* for LD11 */
  102. #define SG_ETPINMODE_RMII(ins) BIT(ins)
  103. #define AVE_MAX_CLKS 4
  104. #define AVE_MAX_RSTS 2
  105. enum desc_id {
  106. AVE_DESCID_TX,
  107. AVE_DESCID_RX,
  108. };
  109. struct ave_private {
  110. phys_addr_t iobase;
  111. unsigned int nclks;
  112. struct clk clk[AVE_MAX_CLKS];
  113. unsigned int nrsts;
  114. struct reset_ctl rst[AVE_MAX_RSTS];
  115. struct regmap *regmap;
  116. unsigned int regmap_arg;
  117. struct mii_dev *bus;
  118. struct phy_device *phydev;
  119. int phy_mode;
  120. int max_speed;
  121. int rx_pos;
  122. int rx_siz;
  123. int rx_off;
  124. int tx_num;
  125. u8 tx_adj_packetbuf[PKTSIZE_ALIGN + PKTALIGN];
  126. void *tx_adj_buf;
  127. const struct ave_soc_data *data;
  128. };
  129. struct ave_soc_data {
  130. bool is_desc_64bit;
  131. const char *clock_names[AVE_MAX_CLKS];
  132. const char *reset_names[AVE_MAX_RSTS];
  133. int (*get_pinmode)(struct ave_private *priv);
  134. };
  135. static u32 ave_desc_read(struct ave_private *priv, enum desc_id id, int entry,
  136. int offset)
  137. {
  138. int desc_size;
  139. u32 addr;
  140. if (priv->data->is_desc_64bit) {
  141. desc_size = AVE_DESC_SIZE_64;
  142. addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64;
  143. } else {
  144. desc_size = AVE_DESC_SIZE_32;
  145. addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32;
  146. }
  147. addr += entry * desc_size + offset;
  148. return readl(priv->iobase + addr);
  149. }
  150. static u32 ave_desc_read_cmdsts(struct ave_private *priv, enum desc_id id,
  151. int entry)
  152. {
  153. return ave_desc_read(priv, id, entry, AVE_DESC_OFS_CMDSTS);
  154. }
  155. static void ave_desc_write(struct ave_private *priv, enum desc_id id,
  156. int entry, int offset, u32 val)
  157. {
  158. int desc_size;
  159. u32 addr;
  160. if (priv->data->is_desc_64bit) {
  161. desc_size = AVE_DESC_SIZE_64;
  162. addr = (id == AVE_DESCID_TX) ? AVE_TXDM_64 : AVE_RXDM_64;
  163. } else {
  164. desc_size = AVE_DESC_SIZE_32;
  165. addr = (id == AVE_DESCID_TX) ? AVE_TXDM_32 : AVE_RXDM_32;
  166. }
  167. addr += entry * desc_size + offset;
  168. writel(val, priv->iobase + addr);
  169. }
  170. static void ave_desc_write_cmdsts(struct ave_private *priv, enum desc_id id,
  171. int entry, u32 val)
  172. {
  173. ave_desc_write(priv, id, entry, AVE_DESC_OFS_CMDSTS, val);
  174. }
  175. static void ave_desc_write_addr(struct ave_private *priv, enum desc_id id,
  176. int entry, uintptr_t paddr)
  177. {
  178. ave_desc_write(priv, id, entry,
  179. AVE_DESC_OFS_ADDRL, lower_32_bits(paddr));
  180. if (priv->data->is_desc_64bit)
  181. ave_desc_write(priv, id, entry,
  182. AVE_DESC_OFS_ADDRU, upper_32_bits(paddr));
  183. }
  184. static void ave_cache_invalidate(uintptr_t vaddr, int len)
  185. {
  186. invalidate_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
  187. roundup(vaddr + len, ARCH_DMA_MINALIGN));
  188. }
  189. static void ave_cache_flush(uintptr_t vaddr, int len)
  190. {
  191. flush_dcache_range(rounddown(vaddr, ARCH_DMA_MINALIGN),
  192. roundup(vaddr + len, ARCH_DMA_MINALIGN));
  193. }
  194. static int ave_mdiobus_read(struct mii_dev *bus,
  195. int phyid, int devad, int regnum)
  196. {
  197. struct ave_private *priv = bus->priv;
  198. u32 mdioctl, mdiosr;
  199. int ret;
  200. /* write address */
  201. writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR);
  202. /* read request */
  203. mdioctl = readl(priv->iobase + AVE_MDIOCTR);
  204. writel(mdioctl | AVE_MDIOCTR_RREQ, priv->iobase + AVE_MDIOCTR);
  205. ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr,
  206. !(mdiosr & AVE_MDIOSR_STS),
  207. AVE_MDIO_TIMEOUT_USEC);
  208. if (ret) {
  209. pr_err("%s: failed to read from mdio (phy:%d reg:%x)\n",
  210. priv->phydev->dev->name, phyid, regnum);
  211. return ret;
  212. }
  213. return readl(priv->iobase + AVE_MDIORDR) & GENMASK(15, 0);
  214. }
  215. static int ave_mdiobus_write(struct mii_dev *bus,
  216. int phyid, int devad, int regnum, u16 val)
  217. {
  218. struct ave_private *priv = bus->priv;
  219. u32 mdioctl, mdiosr;
  220. int ret;
  221. /* write address */
  222. writel((phyid << 8) | regnum, priv->iobase + AVE_MDIOAR);
  223. /* write data */
  224. writel(val, priv->iobase + AVE_MDIOWDR);
  225. /* write request */
  226. mdioctl = readl(priv->iobase + AVE_MDIOCTR);
  227. writel((mdioctl | AVE_MDIOCTR_WREQ) & ~AVE_MDIOCTR_RREQ,
  228. priv->iobase + AVE_MDIOCTR);
  229. ret = readl_poll_timeout(priv->iobase + AVE_MDIOSR, mdiosr,
  230. !(mdiosr & AVE_MDIOSR_STS),
  231. AVE_MDIO_TIMEOUT_USEC);
  232. if (ret)
  233. pr_err("%s: failed to write to mdio (phy:%d reg:%x)\n",
  234. priv->phydev->dev->name, phyid, regnum);
  235. return ret;
  236. }
  237. static int ave_adjust_link(struct ave_private *priv)
  238. {
  239. struct phy_device *phydev = priv->phydev;
  240. struct eth_pdata *pdata = dev_get_platdata(phydev->dev);
  241. u32 val, txcr, rxcr, rxcr_org;
  242. u16 rmt_adv = 0, lcl_adv = 0;
  243. u8 cap;
  244. /* set RGMII speed */
  245. val = readl(priv->iobase + AVE_TXCR);
  246. val &= ~(AVE_TXCR_TXSPD_100 | AVE_TXCR_TXSPD_1G);
  247. if (phy_interface_is_rgmii(phydev) && phydev->speed == SPEED_1000)
  248. val |= AVE_TXCR_TXSPD_1G;
  249. else if (phydev->speed == SPEED_100)
  250. val |= AVE_TXCR_TXSPD_100;
  251. writel(val, priv->iobase + AVE_TXCR);
  252. /* set RMII speed (100M/10M only) */
  253. if (!phy_interface_is_rgmii(phydev)) {
  254. val = readl(priv->iobase + AVE_LINKSEL);
  255. if (phydev->speed == SPEED_10)
  256. val &= ~AVE_LINKSEL_100M;
  257. else
  258. val |= AVE_LINKSEL_100M;
  259. writel(val, priv->iobase + AVE_LINKSEL);
  260. }
  261. /* check current RXCR/TXCR */
  262. rxcr = readl(priv->iobase + AVE_RXCR);
  263. txcr = readl(priv->iobase + AVE_TXCR);
  264. rxcr_org = rxcr;
  265. if (phydev->duplex) {
  266. rxcr |= AVE_RXCR_FDUPEN;
  267. if (phydev->pause)
  268. rmt_adv |= LPA_PAUSE_CAP;
  269. if (phydev->asym_pause)
  270. rmt_adv |= LPA_PAUSE_ASYM;
  271. if (phydev->advertising & ADVERTISED_Pause)
  272. lcl_adv |= ADVERTISE_PAUSE_CAP;
  273. if (phydev->advertising & ADVERTISED_Asym_Pause)
  274. lcl_adv |= ADVERTISE_PAUSE_ASYM;
  275. cap = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
  276. if (cap & FLOW_CTRL_TX)
  277. txcr |= AVE_TXCR_FLOCTR;
  278. else
  279. txcr &= ~AVE_TXCR_FLOCTR;
  280. if (cap & FLOW_CTRL_RX)
  281. rxcr |= AVE_RXCR_FLOCTR;
  282. else
  283. rxcr &= ~AVE_RXCR_FLOCTR;
  284. } else {
  285. rxcr &= ~AVE_RXCR_FDUPEN;
  286. rxcr &= ~AVE_RXCR_FLOCTR;
  287. txcr &= ~AVE_TXCR_FLOCTR;
  288. }
  289. if (rxcr_org != rxcr) {
  290. /* disable Rx mac */
  291. writel(rxcr & ~AVE_RXCR_RXEN, priv->iobase + AVE_RXCR);
  292. /* change and enable TX/Rx mac */
  293. writel(txcr, priv->iobase + AVE_TXCR);
  294. writel(rxcr, priv->iobase + AVE_RXCR);
  295. }
  296. pr_notice("%s: phy:%s speed:%d mac:%pM\n",
  297. phydev->dev->name, phydev->drv->name, phydev->speed,
  298. pdata->enetaddr);
  299. return phydev->link;
  300. }
  301. static int ave_mdiobus_init(struct ave_private *priv, const char *name)
  302. {
  303. struct mii_dev *bus = mdio_alloc();
  304. if (!bus)
  305. return -ENOMEM;
  306. bus->read = ave_mdiobus_read;
  307. bus->write = ave_mdiobus_write;
  308. snprintf(bus->name, sizeof(bus->name), "%s", name);
  309. bus->priv = priv;
  310. return mdio_register(bus);
  311. }
  312. static int ave_phy_init(struct ave_private *priv, void *dev)
  313. {
  314. struct phy_device *phydev;
  315. int mask = GENMASK(31, 0), ret;
  316. phydev = phy_find_by_mask(priv->bus, mask, priv->phy_mode);
  317. if (!phydev)
  318. return -ENODEV;
  319. phy_connect_dev(phydev, dev);
  320. phydev->supported &= PHY_GBIT_FEATURES;
  321. if (priv->max_speed) {
  322. ret = phy_set_supported(phydev, priv->max_speed);
  323. if (ret)
  324. return ret;
  325. }
  326. phydev->advertising = phydev->supported;
  327. priv->phydev = phydev;
  328. phy_config(phydev);
  329. return 0;
  330. }
  331. static void ave_stop(struct udevice *dev)
  332. {
  333. struct ave_private *priv = dev_get_priv(dev);
  334. u32 val;
  335. int ret;
  336. val = readl(priv->iobase + AVE_GRR);
  337. if (val)
  338. return;
  339. val = readl(priv->iobase + AVE_RXCR);
  340. val &= ~AVE_RXCR_RXEN;
  341. writel(val, priv->iobase + AVE_RXCR);
  342. writel(0, priv->iobase + AVE_DESCC);
  343. ret = readl_poll_timeout(priv->iobase + AVE_DESCC, val, !val,
  344. AVE_HALT_TIMEOUT_USEC);
  345. if (ret)
  346. pr_warn("%s: halt timeout\n", priv->phydev->dev->name);
  347. writel(AVE_GRR_GRST, priv->iobase + AVE_GRR);
  348. phy_shutdown(priv->phydev);
  349. }
  350. static void ave_reset(struct ave_private *priv)
  351. {
  352. u32 val;
  353. /* reset RMII register */
  354. val = readl(priv->iobase + AVE_RSTCTRL);
  355. val &= ~AVE_RSTCTRL_RMIIRST;
  356. writel(val, priv->iobase + AVE_RSTCTRL);
  357. /* assert reset */
  358. writel(AVE_GRR_GRST | AVE_GRR_PHYRST, priv->iobase + AVE_GRR);
  359. mdelay(AVE_GRST_DELAY_MSEC);
  360. /* 1st, negate PHY reset only */
  361. writel(AVE_GRR_GRST, priv->iobase + AVE_GRR);
  362. mdelay(AVE_GRST_DELAY_MSEC);
  363. /* negate reset */
  364. writel(0, priv->iobase + AVE_GRR);
  365. mdelay(AVE_GRST_DELAY_MSEC);
  366. /* negate RMII register */
  367. val = readl(priv->iobase + AVE_RSTCTRL);
  368. val |= AVE_RSTCTRL_RMIIRST;
  369. writel(val, priv->iobase + AVE_RSTCTRL);
  370. }
  371. static int ave_start(struct udevice *dev)
  372. {
  373. struct ave_private *priv = dev_get_priv(dev);
  374. uintptr_t paddr;
  375. u32 val;
  376. int i;
  377. ave_reset(priv);
  378. priv->rx_pos = 0;
  379. priv->rx_off = 2; /* RX data has 2byte offsets */
  380. priv->tx_num = 0;
  381. priv->tx_adj_buf =
  382. (void *)roundup((uintptr_t)&priv->tx_adj_packetbuf[0],
  383. PKTALIGN);
  384. priv->rx_siz = (PKTSIZE_ALIGN - priv->rx_off);
  385. val = 0;
  386. if (priv->phy_mode != PHY_INTERFACE_MODE_RGMII)
  387. val |= AVE_CFGR_MII;
  388. writel(val, priv->iobase + AVE_CFGR);
  389. /* use one descriptor for Tx */
  390. writel(AVE_DESC_SIZE(priv, 1) << 16, priv->iobase + AVE_TXDC);
  391. ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, 0);
  392. ave_desc_write_addr(priv, AVE_DESCID_TX, 0, 0);
  393. /* use PKTBUFSRX descriptors for Rx */
  394. writel(AVE_DESC_SIZE(priv, PKTBUFSRX) << 16, priv->iobase + AVE_RXDC);
  395. for (i = 0; i < PKTBUFSRX; i++) {
  396. paddr = (uintptr_t)net_rx_packets[i];
  397. ave_cache_flush(paddr, priv->rx_siz + priv->rx_off);
  398. ave_desc_write_addr(priv, AVE_DESCID_RX, i, paddr);
  399. ave_desc_write_cmdsts(priv, AVE_DESCID_RX, i, priv->rx_siz);
  400. }
  401. writel(AVE_GISR_CLR, priv->iobase + AVE_GISR);
  402. writel(AVE_GIMR_CLR, priv->iobase + AVE_GIMR);
  403. writel(AVE_RXCR_RXEN | AVE_RXCR_FDUPEN | AVE_RXCR_FLOCTR | AVE_RXCR_MTU,
  404. priv->iobase + AVE_RXCR);
  405. writel(AVE_DESCC_RD0 | AVE_DESCC_TD, priv->iobase + AVE_DESCC);
  406. phy_startup(priv->phydev);
  407. ave_adjust_link(priv);
  408. return 0;
  409. }
  410. static int ave_write_hwaddr(struct udevice *dev)
  411. {
  412. struct ave_private *priv = dev_get_priv(dev);
  413. struct eth_pdata *pdata = dev_get_platdata(dev);
  414. u8 *mac = pdata->enetaddr;
  415. writel(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24,
  416. priv->iobase + AVE_RXMAC1R);
  417. writel(mac[4] | mac[5] << 8, priv->iobase + AVE_RXMAC2R);
  418. return 0;
  419. }
  420. static int ave_send(struct udevice *dev, void *packet, int length)
  421. {
  422. struct ave_private *priv = dev_get_priv(dev);
  423. u32 val;
  424. void *ptr = packet;
  425. int count;
  426. /* adjust alignment for descriptor */
  427. if ((uintptr_t)ptr & 0x3) {
  428. memcpy(priv->tx_adj_buf, (const void *)ptr, length);
  429. ptr = priv->tx_adj_buf;
  430. }
  431. /* padding for minimum length */
  432. if (length < AVE_MIN_XMITSIZE) {
  433. memset(ptr + length, 0, AVE_MIN_XMITSIZE - length);
  434. length = AVE_MIN_XMITSIZE;
  435. }
  436. /* check ownership and wait for previous xmit done */
  437. count = AVE_SEND_TIMEOUT_COUNT;
  438. do {
  439. val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0);
  440. } while ((val & AVE_STS_OWN) && --count);
  441. if (!count)
  442. return -ETIMEDOUT;
  443. ave_cache_flush((uintptr_t)ptr, length);
  444. ave_desc_write_addr(priv, AVE_DESCID_TX, 0, (uintptr_t)ptr);
  445. val = AVE_STS_OWN | AVE_STS_1ST | AVE_STS_LAST |
  446. (length & AVE_STS_PKTLEN_TX_MASK);
  447. ave_desc_write_cmdsts(priv, AVE_DESCID_TX, 0, val);
  448. priv->tx_num++;
  449. count = AVE_SEND_TIMEOUT_COUNT;
  450. do {
  451. val = ave_desc_read_cmdsts(priv, AVE_DESCID_TX, 0);
  452. } while ((val & AVE_STS_OWN) && --count);
  453. if (!count)
  454. return -ETIMEDOUT;
  455. if (!(val & AVE_STS_OK))
  456. pr_warn("%s: bad send packet status:%08x\n",
  457. priv->phydev->dev->name, le32_to_cpu(val));
  458. return 0;
  459. }
  460. static int ave_recv(struct udevice *dev, int flags, uchar **packetp)
  461. {
  462. struct ave_private *priv = dev_get_priv(dev);
  463. uchar *ptr;
  464. int length = 0;
  465. u32 cmdsts;
  466. while (1) {
  467. cmdsts = ave_desc_read_cmdsts(priv, AVE_DESCID_RX,
  468. priv->rx_pos);
  469. if (!(cmdsts & AVE_STS_OWN))
  470. /* hardware ownership, no received packets */
  471. return -EAGAIN;
  472. ptr = net_rx_packets[priv->rx_pos] + priv->rx_off;
  473. if (cmdsts & AVE_STS_OK)
  474. break;
  475. pr_warn("%s: bad packet[%d] status:%08x ptr:%p\n",
  476. priv->phydev->dev->name, priv->rx_pos,
  477. le32_to_cpu(cmdsts), ptr);
  478. }
  479. length = cmdsts & AVE_STS_PKTLEN_RX_MASK;
  480. /* invalidate after DMA is done */
  481. ave_cache_invalidate((uintptr_t)ptr, length);
  482. *packetp = ptr;
  483. return length;
  484. }
  485. static int ave_free_packet(struct udevice *dev, uchar *packet, int length)
  486. {
  487. struct ave_private *priv = dev_get_priv(dev);
  488. ave_cache_flush((uintptr_t)net_rx_packets[priv->rx_pos],
  489. priv->rx_siz + priv->rx_off);
  490. ave_desc_write_cmdsts(priv, AVE_DESCID_RX,
  491. priv->rx_pos, priv->rx_siz);
  492. if (++priv->rx_pos >= PKTBUFSRX)
  493. priv->rx_pos = 0;
  494. return 0;
  495. }
  496. static int ave_pro4_get_pinmode(struct ave_private *priv)
  497. {
  498. u32 reg, mask, val = 0;
  499. if (priv->regmap_arg > 0)
  500. return -EINVAL;
  501. mask = SG_ETPINMODE_RMII(0);
  502. switch (priv->phy_mode) {
  503. case PHY_INTERFACE_MODE_RMII:
  504. val = SG_ETPINMODE_RMII(0);
  505. break;
  506. case PHY_INTERFACE_MODE_MII:
  507. case PHY_INTERFACE_MODE_RGMII:
  508. break;
  509. default:
  510. return -EINVAL;
  511. }
  512. regmap_read(priv->regmap, SG_ETPINMODE, &reg);
  513. reg &= ~mask;
  514. reg |= val;
  515. regmap_write(priv->regmap, SG_ETPINMODE, reg);
  516. return 0;
  517. }
  518. static int ave_ld11_get_pinmode(struct ave_private *priv)
  519. {
  520. u32 reg, mask, val = 0;
  521. if (priv->regmap_arg > 0)
  522. return -EINVAL;
  523. mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0);
  524. switch (priv->phy_mode) {
  525. case PHY_INTERFACE_MODE_INTERNAL:
  526. break;
  527. case PHY_INTERFACE_MODE_RMII:
  528. val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0);
  529. break;
  530. default:
  531. return -EINVAL;
  532. }
  533. regmap_read(priv->regmap, SG_ETPINMODE, &reg);
  534. reg &= ~mask;
  535. reg |= val;
  536. regmap_write(priv->regmap, SG_ETPINMODE, reg);
  537. return 0;
  538. }
  539. static int ave_ld20_get_pinmode(struct ave_private *priv)
  540. {
  541. u32 reg, mask, val = 0;
  542. if (priv->regmap_arg > 0)
  543. return -EINVAL;
  544. mask = SG_ETPINMODE_RMII(0);
  545. switch (priv->phy_mode) {
  546. case PHY_INTERFACE_MODE_RMII:
  547. val = SG_ETPINMODE_RMII(0);
  548. break;
  549. case PHY_INTERFACE_MODE_RGMII:
  550. break;
  551. default:
  552. return -EINVAL;
  553. }
  554. regmap_read(priv->regmap, SG_ETPINMODE, &reg);
  555. reg &= ~mask;
  556. reg |= val;
  557. regmap_write(priv->regmap, SG_ETPINMODE, reg);
  558. return 0;
  559. }
  560. static int ave_pxs3_get_pinmode(struct ave_private *priv)
  561. {
  562. u32 reg, mask, val = 0;
  563. if (priv->regmap_arg > 1)
  564. return -EINVAL;
  565. mask = SG_ETPINMODE_RMII(priv->regmap_arg);
  566. switch (priv->phy_mode) {
  567. case PHY_INTERFACE_MODE_RMII:
  568. val = SG_ETPINMODE_RMII(priv->regmap_arg);
  569. break;
  570. case PHY_INTERFACE_MODE_RGMII:
  571. break;
  572. default:
  573. return -EINVAL;
  574. }
  575. regmap_read(priv->regmap, SG_ETPINMODE, &reg);
  576. reg &= ~mask;
  577. reg |= val;
  578. regmap_write(priv->regmap, SG_ETPINMODE, reg);
  579. return 0;
  580. }
  581. static int ave_ofdata_to_platdata(struct udevice *dev)
  582. {
  583. struct eth_pdata *pdata = dev_get_platdata(dev);
  584. struct ave_private *priv = dev_get_priv(dev);
  585. struct ofnode_phandle_args args;
  586. const char *phy_mode;
  587. const u32 *valp;
  588. int ret, nc, nr;
  589. const char *name;
  590. priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev);
  591. if (!priv->data)
  592. return -EINVAL;
  593. pdata->iobase = devfdt_get_addr(dev);
  594. pdata->phy_interface = -1;
  595. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  596. NULL);
  597. if (phy_mode)
  598. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  599. if (pdata->phy_interface == -1) {
  600. dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
  601. return -EINVAL;
  602. }
  603. pdata->max_speed = 0;
  604. valp = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed",
  605. NULL);
  606. if (valp)
  607. pdata->max_speed = fdt32_to_cpu(*valp);
  608. for (nc = 0; nc < AVE_MAX_CLKS; nc++) {
  609. name = priv->data->clock_names[nc];
  610. if (!name)
  611. break;
  612. ret = clk_get_by_name(dev, name, &priv->clk[nc]);
  613. if (ret) {
  614. dev_err(dev, "Failed to get clocks property: %d\n",
  615. ret);
  616. goto out_clk_free;
  617. }
  618. priv->nclks++;
  619. }
  620. for (nr = 0; nr < AVE_MAX_RSTS; nr++) {
  621. name = priv->data->reset_names[nr];
  622. if (!name)
  623. break;
  624. ret = reset_get_by_name(dev, name, &priv->rst[nr]);
  625. if (ret) {
  626. dev_err(dev, "Failed to get resets property: %d\n",
  627. ret);
  628. goto out_reset_free;
  629. }
  630. priv->nrsts++;
  631. }
  632. ret = dev_read_phandle_with_args(dev, "socionext,syscon-phy-mode",
  633. NULL, 1, 0, &args);
  634. if (ret) {
  635. dev_err(dev, "Failed to get syscon-phy-mode property: %d\n",
  636. ret);
  637. goto out_reset_free;
  638. }
  639. priv->regmap = syscon_node_to_regmap(args.node);
  640. if (IS_ERR(priv->regmap)) {
  641. ret = PTR_ERR(priv->regmap);
  642. dev_err(dev, "can't get syscon: %d\n", ret);
  643. goto out_reset_free;
  644. }
  645. if (args.args_count != 1) {
  646. ret = -EINVAL;
  647. dev_err(dev, "Invalid argument of syscon-phy-mode\n");
  648. goto out_reset_free;
  649. }
  650. priv->regmap_arg = args.args[0];
  651. return 0;
  652. out_reset_free:
  653. while (--nr >= 0)
  654. reset_free(&priv->rst[nr]);
  655. out_clk_free:
  656. while (--nc >= 0)
  657. clk_free(&priv->clk[nc]);
  658. return ret;
  659. }
  660. static int ave_probe(struct udevice *dev)
  661. {
  662. struct eth_pdata *pdata = dev_get_platdata(dev);
  663. struct ave_private *priv = dev_get_priv(dev);
  664. int ret, nc, nr;
  665. priv->data = (const struct ave_soc_data *)dev_get_driver_data(dev);
  666. if (!priv->data)
  667. return -EINVAL;
  668. priv->iobase = pdata->iobase;
  669. priv->phy_mode = pdata->phy_interface;
  670. priv->max_speed = pdata->max_speed;
  671. ret = priv->data->get_pinmode(priv);
  672. if (ret) {
  673. dev_err(dev, "Invalid phy-mode\n");
  674. return -EINVAL;
  675. }
  676. for (nc = 0; nc < priv->nclks; nc++) {
  677. ret = clk_enable(&priv->clk[nc]);
  678. if (ret) {
  679. dev_err(dev, "Failed to enable clk: %d\n", ret);
  680. goto out_clk_release;
  681. }
  682. }
  683. for (nr = 0; nr < priv->nrsts; nr++) {
  684. ret = reset_deassert(&priv->rst[nr]);
  685. if (ret) {
  686. dev_err(dev, "Failed to deassert reset: %d\n", ret);
  687. goto out_reset_release;
  688. }
  689. }
  690. ave_reset(priv);
  691. ret = ave_mdiobus_init(priv, dev->name);
  692. if (ret) {
  693. dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
  694. goto out_reset_release;
  695. }
  696. priv->bus = miiphy_get_dev_by_name(dev->name);
  697. ret = ave_phy_init(priv, dev);
  698. if (ret) {
  699. dev_err(dev, "Failed to initialize phy: %d\n", ret);
  700. goto out_mdiobus_release;
  701. }
  702. return 0;
  703. out_mdiobus_release:
  704. mdio_unregister(priv->bus);
  705. mdio_free(priv->bus);
  706. out_reset_release:
  707. reset_release_all(priv->rst, nr);
  708. out_clk_release:
  709. clk_release_all(priv->clk, nc);
  710. return ret;
  711. }
  712. static int ave_remove(struct udevice *dev)
  713. {
  714. struct ave_private *priv = dev_get_priv(dev);
  715. free(priv->phydev);
  716. mdio_unregister(priv->bus);
  717. mdio_free(priv->bus);
  718. reset_release_all(priv->rst, priv->nrsts);
  719. clk_release_all(priv->clk, priv->nclks);
  720. return 0;
  721. }
  722. static const struct eth_ops ave_ops = {
  723. .start = ave_start,
  724. .stop = ave_stop,
  725. .send = ave_send,
  726. .recv = ave_recv,
  727. .free_pkt = ave_free_packet,
  728. .write_hwaddr = ave_write_hwaddr,
  729. };
  730. static const struct ave_soc_data ave_pro4_data = {
  731. .is_desc_64bit = false,
  732. .clock_names = {
  733. "gio", "ether", "ether-gb", "ether-phy",
  734. },
  735. .reset_names = {
  736. "gio", "ether",
  737. },
  738. .get_pinmode = ave_pro4_get_pinmode,
  739. };
  740. static const struct ave_soc_data ave_pxs2_data = {
  741. .is_desc_64bit = false,
  742. .clock_names = {
  743. "ether",
  744. },
  745. .reset_names = {
  746. "ether",
  747. },
  748. .get_pinmode = ave_pro4_get_pinmode,
  749. };
  750. static const struct ave_soc_data ave_ld11_data = {
  751. .is_desc_64bit = false,
  752. .clock_names = {
  753. "ether",
  754. },
  755. .reset_names = {
  756. "ether",
  757. },
  758. .get_pinmode = ave_ld11_get_pinmode,
  759. };
  760. static const struct ave_soc_data ave_ld20_data = {
  761. .is_desc_64bit = true,
  762. .clock_names = {
  763. "ether",
  764. },
  765. .reset_names = {
  766. "ether",
  767. },
  768. .get_pinmode = ave_ld20_get_pinmode,
  769. };
  770. static const struct ave_soc_data ave_pxs3_data = {
  771. .is_desc_64bit = false,
  772. .clock_names = {
  773. "ether",
  774. },
  775. .reset_names = {
  776. "ether",
  777. },
  778. .get_pinmode = ave_pxs3_get_pinmode,
  779. };
  780. static const struct udevice_id ave_ids[] = {
  781. {
  782. .compatible = "socionext,uniphier-pro4-ave4",
  783. .data = (ulong)&ave_pro4_data,
  784. },
  785. {
  786. .compatible = "socionext,uniphier-pxs2-ave4",
  787. .data = (ulong)&ave_pxs2_data,
  788. },
  789. {
  790. .compatible = "socionext,uniphier-ld11-ave4",
  791. .data = (ulong)&ave_ld11_data,
  792. },
  793. {
  794. .compatible = "socionext,uniphier-ld20-ave4",
  795. .data = (ulong)&ave_ld20_data,
  796. },
  797. {
  798. .compatible = "socionext,uniphier-pxs3-ave4",
  799. .data = (ulong)&ave_pxs3_data,
  800. },
  801. { /* Sentinel */ }
  802. };
  803. U_BOOT_DRIVER(ave) = {
  804. .name = "ave",
  805. .id = UCLASS_ETH,
  806. .of_match = ave_ids,
  807. .probe = ave_probe,
  808. .remove = ave_remove,
  809. .ofdata_to_platdata = ave_ofdata_to_platdata,
  810. .ops = &ave_ops,
  811. .priv_auto_alloc_size = sizeof(struct ave_private),
  812. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  813. };