smc911x.h 17 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * SMSC LAN9[12]1[567] Network driver
  4. *
  5. * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  6. */
  7. #ifndef _SMC911X_H_
  8. #define _SMC911X_H_
  9. #include <linux/types.h>
  10. #define DRIVERNAME "smc911x"
  11. #if defined (CONFIG_SMC911X_32_BIT) && \
  12. defined (CONFIG_SMC911X_16_BIT)
  13. #error "SMC911X: Only one of CONFIG_SMC911X_32_BIT and \
  14. CONFIG_SMC911X_16_BIT shall be set"
  15. #endif
  16. #if defined (CONFIG_SMC911X_32_BIT)
  17. static inline u32 __smc911x_reg_read(struct eth_device *dev, u32 offset)
  18. {
  19. return *(volatile u32*)(dev->iobase + offset);
  20. }
  21. u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
  22. __attribute__((weak, alias("__smc911x_reg_read")));
  23. static inline void __smc911x_reg_write(struct eth_device *dev,
  24. u32 offset, u32 val)
  25. {
  26. *(volatile u32*)(dev->iobase + offset) = val;
  27. }
  28. void smc911x_reg_write(struct eth_device *dev, u32 offset, u32 val)
  29. __attribute__((weak, alias("__smc911x_reg_write")));
  30. #elif defined (CONFIG_SMC911X_16_BIT)
  31. static inline u32 smc911x_reg_read(struct eth_device *dev, u32 offset)
  32. {
  33. volatile u16 *addr_16 = (u16 *)(dev->iobase + offset);
  34. return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
  35. }
  36. static inline void smc911x_reg_write(struct eth_device *dev,
  37. u32 offset, u32 val)
  38. {
  39. *(volatile u16 *)(dev->iobase + offset) = (u16)val;
  40. *(volatile u16 *)(dev->iobase + offset + 2) = (u16)(val >> 16);
  41. }
  42. #else
  43. #error "SMC911X: undefined bus width"
  44. #endif /* CONFIG_SMC911X_16_BIT */
  45. /* Below are the register offsets and bit definitions
  46. * of the Lan911x memory space
  47. */
  48. #define RX_DATA_FIFO 0x00
  49. #define TX_DATA_FIFO 0x20
  50. #define TX_CMD_A_INT_ON_COMP 0x80000000
  51. #define TX_CMD_A_INT_BUF_END_ALGN 0x03000000
  52. #define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000
  53. #define TX_CMD_A_INT_16_BYTE_ALGN 0x01000000
  54. #define TX_CMD_A_INT_32_BYTE_ALGN 0x02000000
  55. #define TX_CMD_A_INT_DATA_OFFSET 0x001F0000
  56. #define TX_CMD_A_INT_FIRST_SEG 0x00002000
  57. #define TX_CMD_A_INT_LAST_SEG 0x00001000
  58. #define TX_CMD_A_BUF_SIZE 0x000007FF
  59. #define TX_CMD_B_PKT_TAG 0xFFFF0000
  60. #define TX_CMD_B_ADD_CRC_DISABLE 0x00002000
  61. #define TX_CMD_B_DISABLE_PADDING 0x00001000
  62. #define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF
  63. #define RX_STATUS_FIFO 0x40
  64. #define RX_STS_PKT_LEN 0x3FFF0000
  65. #define RX_STS_ES 0x00008000
  66. #define RX_STS_BCST 0x00002000
  67. #define RX_STS_LEN_ERR 0x00001000
  68. #define RX_STS_RUNT_ERR 0x00000800
  69. #define RX_STS_MCAST 0x00000400
  70. #define RX_STS_TOO_LONG 0x00000080
  71. #define RX_STS_COLL 0x00000040
  72. #define RX_STS_ETH_TYPE 0x00000020
  73. #define RX_STS_WDOG_TMT 0x00000010
  74. #define RX_STS_MII_ERR 0x00000008
  75. #define RX_STS_DRIBBLING 0x00000004
  76. #define RX_STS_CRC_ERR 0x00000002
  77. #define RX_STATUS_FIFO_PEEK 0x44
  78. #define TX_STATUS_FIFO 0x48
  79. #define TX_STS_TAG 0xFFFF0000
  80. #define TX_STS_ES 0x00008000
  81. #define TX_STS_LOC 0x00000800
  82. #define TX_STS_NO_CARR 0x00000400
  83. #define TX_STS_LATE_COLL 0x00000200
  84. #define TX_STS_MANY_COLL 0x00000100
  85. #define TX_STS_COLL_CNT 0x00000078
  86. #define TX_STS_MANY_DEFER 0x00000004
  87. #define TX_STS_UNDERRUN 0x00000002
  88. #define TX_STS_DEFERRED 0x00000001
  89. #define TX_STATUS_FIFO_PEEK 0x4C
  90. #define ID_REV 0x50
  91. #define ID_REV_CHIP_ID 0xFFFF0000 /* RO */
  92. #define ID_REV_REV_ID 0x0000FFFF /* RO */
  93. #define INT_CFG 0x54
  94. #define INT_CFG_INT_DEAS 0xFF000000 /* R/W */
  95. #define INT_CFG_INT_DEAS_CLR 0x00004000
  96. #define INT_CFG_INT_DEAS_STS 0x00002000
  97. #define INT_CFG_IRQ_INT 0x00001000 /* RO */
  98. #define INT_CFG_IRQ_EN 0x00000100 /* R/W */
  99. /* R/W Not Affected by SW Reset */
  100. #define INT_CFG_IRQ_POL 0x00000010
  101. /* R/W Not Affected by SW Reset */
  102. #define INT_CFG_IRQ_TYPE 0x00000001
  103. #define INT_STS 0x58
  104. #define INT_STS_SW_INT 0x80000000 /* R/WC */
  105. #define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */
  106. #define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */
  107. #define INT_STS_RXDFH_INT 0x00800000 /* R/WC */
  108. #define INT_STS_RXDF_INT 0x00400000 /* R/WC */
  109. #define INT_STS_TX_IOC 0x00200000 /* R/WC */
  110. #define INT_STS_RXD_INT 0x00100000 /* R/WC */
  111. #define INT_STS_GPT_INT 0x00080000 /* R/WC */
  112. #define INT_STS_PHY_INT 0x00040000 /* RO */
  113. #define INT_STS_PME_INT 0x00020000 /* R/WC */
  114. #define INT_STS_TXSO 0x00010000 /* R/WC */
  115. #define INT_STS_RWT 0x00008000 /* R/WC */
  116. #define INT_STS_RXE 0x00004000 /* R/WC */
  117. #define INT_STS_TXE 0x00002000 /* R/WC */
  118. /*#define INT_STS_ERX 0x00001000*/ /* R/WC */
  119. #define INT_STS_TDFU 0x00000800 /* R/WC */
  120. #define INT_STS_TDFO 0x00000400 /* R/WC */
  121. #define INT_STS_TDFA 0x00000200 /* R/WC */
  122. #define INT_STS_TSFF 0x00000100 /* R/WC */
  123. #define INT_STS_TSFL 0x00000080 /* R/WC */
  124. /*#define INT_STS_RXDF 0x00000040*/ /* R/WC */
  125. #define INT_STS_RDFO 0x00000040 /* R/WC */
  126. #define INT_STS_RDFL 0x00000020 /* R/WC */
  127. #define INT_STS_RSFF 0x00000010 /* R/WC */
  128. #define INT_STS_RSFL 0x00000008 /* R/WC */
  129. #define INT_STS_GPIO2_INT 0x00000004 /* R/WC */
  130. #define INT_STS_GPIO1_INT 0x00000002 /* R/WC */
  131. #define INT_STS_GPIO0_INT 0x00000001 /* R/WC */
  132. #define INT_EN 0x5C
  133. #define INT_EN_SW_INT_EN 0x80000000 /* R/W */
  134. #define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */
  135. #define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */
  136. #define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */
  137. /*#define INT_EN_RXDF_INT_EN 0x00400000*/ /* R/W */
  138. #define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */
  139. #define INT_EN_RXD_INT_EN 0x00100000 /* R/W */
  140. #define INT_EN_GPT_INT_EN 0x00080000 /* R/W */
  141. #define INT_EN_PHY_INT_EN 0x00040000 /* R/W */
  142. #define INT_EN_PME_INT_EN 0x00020000 /* R/W */
  143. #define INT_EN_TXSO_EN 0x00010000 /* R/W */
  144. #define INT_EN_RWT_EN 0x00008000 /* R/W */
  145. #define INT_EN_RXE_EN 0x00004000 /* R/W */
  146. #define INT_EN_TXE_EN 0x00002000 /* R/W */
  147. /*#define INT_EN_ERX_EN 0x00001000*/ /* R/W */
  148. #define INT_EN_TDFU_EN 0x00000800 /* R/W */
  149. #define INT_EN_TDFO_EN 0x00000400 /* R/W */
  150. #define INT_EN_TDFA_EN 0x00000200 /* R/W */
  151. #define INT_EN_TSFF_EN 0x00000100 /* R/W */
  152. #define INT_EN_TSFL_EN 0x00000080 /* R/W */
  153. /*#define INT_EN_RXDF_EN 0x00000040*/ /* R/W */
  154. #define INT_EN_RDFO_EN 0x00000040 /* R/W */
  155. #define INT_EN_RDFL_EN 0x00000020 /* R/W */
  156. #define INT_EN_RSFF_EN 0x00000010 /* R/W */
  157. #define INT_EN_RSFL_EN 0x00000008 /* R/W */
  158. #define INT_EN_GPIO2_INT 0x00000004 /* R/W */
  159. #define INT_EN_GPIO1_INT 0x00000002 /* R/W */
  160. #define INT_EN_GPIO0_INT 0x00000001 /* R/W */
  161. #define BYTE_TEST 0x64
  162. #define FIFO_INT 0x68
  163. #define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */
  164. #define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */
  165. #define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */
  166. #define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */
  167. #define RX_CFG 0x6C
  168. #define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */
  169. #define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */
  170. #define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */
  171. #define RX_CFG_RX_END_ALGN32 0x80000000 /* R/W */
  172. #define RX_CFG_RX_DMA_CNT 0x0FFF0000 /* R/W */
  173. #define RX_CFG_RX_DUMP 0x00008000 /* R/W */
  174. #define RX_CFG_RXDOFF 0x00001F00 /* R/W */
  175. /*#define RX_CFG_RXBAD 0x00000001*/ /* R/W */
  176. #define TX_CFG 0x70
  177. /*#define TX_CFG_TX_DMA_LVL 0xE0000000*/ /* R/W */
  178. /* R/W Self Clearing */
  179. /*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/
  180. #define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */
  181. #define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */
  182. #define TX_CFG_TXSAO 0x00000004 /* R/W */
  183. #define TX_CFG_TX_ON 0x00000002 /* R/W */
  184. #define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */
  185. #define HW_CFG 0x74
  186. #define HW_CFG_TTM 0x00200000 /* R/W */
  187. #define HW_CFG_SF 0x00100000 /* R/W */
  188. #define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */
  189. #define HW_CFG_TR 0x00003000 /* R/W */
  190. #define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */
  191. #define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */
  192. #define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */
  193. #define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */
  194. #define HW_CFG_SMI_SEL 0x00000010 /* R/W */
  195. #define HW_CFG_EXT_PHY_DET 0x00000008 /* RO */
  196. #define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */
  197. #define HW_CFG_32_16_BIT_MODE 0x00000004 /* RO */
  198. #define HW_CFG_SRST_TO 0x00000002 /* RO */
  199. #define HW_CFG_SRST 0x00000001 /* Self Clearing */
  200. #define RX_DP_CTRL 0x78
  201. #define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */
  202. #define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */
  203. #define RX_FIFO_INF 0x7C
  204. #define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */
  205. #define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */
  206. #define TX_FIFO_INF 0x80
  207. #define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */
  208. #define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */
  209. #define PMT_CTRL 0x84
  210. #define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */
  211. #define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */
  212. #define PMT_CTRL_WOL_EN 0x00000200 /* R/W */
  213. #define PMT_CTRL_ED_EN 0x00000100 /* R/W */
  214. /* R/W Not Affected by SW Reset */
  215. #define PMT_CTRL_PME_TYPE 0x00000040
  216. #define PMT_CTRL_WUPS 0x00000030 /* R/WC */
  217. #define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */
  218. #define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */
  219. #define PMT_CTRL_WUPS_WOL 0x00000020 /* R/WC */
  220. #define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */
  221. #define PMT_CTRL_PME_IND 0x00000008 /* R/W */
  222. #define PMT_CTRL_PME_POL 0x00000004 /* R/W */
  223. /* R/W Not Affected by SW Reset */
  224. #define PMT_CTRL_PME_EN 0x00000002
  225. #define PMT_CTRL_READY 0x00000001 /* RO */
  226. #define GPIO_CFG 0x88
  227. #define GPIO_CFG_LED3_EN 0x40000000 /* R/W */
  228. #define GPIO_CFG_LED2_EN 0x20000000 /* R/W */
  229. #define GPIO_CFG_LED1_EN 0x10000000 /* R/W */
  230. #define GPIO_CFG_GPIO2_INT_POL 0x04000000 /* R/W */
  231. #define GPIO_CFG_GPIO1_INT_POL 0x02000000 /* R/W */
  232. #define GPIO_CFG_GPIO0_INT_POL 0x01000000 /* R/W */
  233. #define GPIO_CFG_EEPR_EN 0x00700000 /* R/W */
  234. #define GPIO_CFG_GPIOBUF2 0x00040000 /* R/W */
  235. #define GPIO_CFG_GPIOBUF1 0x00020000 /* R/W */
  236. #define GPIO_CFG_GPIOBUF0 0x00010000 /* R/W */
  237. #define GPIO_CFG_GPIODIR2 0x00000400 /* R/W */
  238. #define GPIO_CFG_GPIODIR1 0x00000200 /* R/W */
  239. #define GPIO_CFG_GPIODIR0 0x00000100 /* R/W */
  240. #define GPIO_CFG_GPIOD4 0x00000010 /* R/W */
  241. #define GPIO_CFG_GPIOD3 0x00000008 /* R/W */
  242. #define GPIO_CFG_GPIOD2 0x00000004 /* R/W */
  243. #define GPIO_CFG_GPIOD1 0x00000002 /* R/W */
  244. #define GPIO_CFG_GPIOD0 0x00000001 /* R/W */
  245. #define GPT_CFG 0x8C
  246. #define GPT_CFG_TIMER_EN 0x20000000 /* R/W */
  247. #define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */
  248. #define GPT_CNT 0x90
  249. #define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */
  250. #define ENDIAN 0x98
  251. #define FREE_RUN 0x9C
  252. #define RX_DROP 0xA0
  253. #define MAC_CSR_CMD 0xA4
  254. #define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */
  255. #define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */
  256. #define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */
  257. #define MAC_CSR_DATA 0xA8
  258. #define AFC_CFG 0xAC
  259. #define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */
  260. #define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */
  261. #define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */
  262. #define AFC_CFG_FCMULT 0x00000008 /* R/W */
  263. #define AFC_CFG_FCBRD 0x00000004 /* R/W */
  264. #define AFC_CFG_FCADD 0x00000002 /* R/W */
  265. #define AFC_CFG_FCANY 0x00000001 /* R/W */
  266. #define E2P_CMD 0xB0
  267. #define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */
  268. #define E2P_CMD_EPC_CMD 0x70000000 /* R/W */
  269. #define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */
  270. #define E2P_CMD_EPC_CMD_EWDS 0x10000000 /* R/W */
  271. #define E2P_CMD_EPC_CMD_EWEN 0x20000000 /* R/W */
  272. #define E2P_CMD_EPC_CMD_WRITE 0x30000000 /* R/W */
  273. #define E2P_CMD_EPC_CMD_WRAL 0x40000000 /* R/W */
  274. #define E2P_CMD_EPC_CMD_ERASE 0x50000000 /* R/W */
  275. #define E2P_CMD_EPC_CMD_ERAL 0x60000000 /* R/W */
  276. #define E2P_CMD_EPC_CMD_RELOAD 0x70000000 /* R/W */
  277. #define E2P_CMD_EPC_TIMEOUT 0x00000200 /* RO */
  278. #define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */
  279. #define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */
  280. #define E2P_DATA 0xB4
  281. #define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */
  282. /* end of LAN register offsets and bit definitions */
  283. /* MAC Control and Status registers */
  284. #define MAC_CR 0x01 /* R/W */
  285. /* MAC_CR - MAC Control Register */
  286. #define MAC_CR_RXALL 0x80000000
  287. /* TODO: delete this bit? It is not described in the data sheet. */
  288. #define MAC_CR_HBDIS 0x10000000
  289. #define MAC_CR_RCVOWN 0x00800000
  290. #define MAC_CR_LOOPBK 0x00200000
  291. #define MAC_CR_FDPX 0x00100000
  292. #define MAC_CR_MCPAS 0x00080000
  293. #define MAC_CR_PRMS 0x00040000
  294. #define MAC_CR_INVFILT 0x00020000
  295. #define MAC_CR_PASSBAD 0x00010000
  296. #define MAC_CR_HFILT 0x00008000
  297. #define MAC_CR_HPFILT 0x00002000
  298. #define MAC_CR_LCOLL 0x00001000
  299. #define MAC_CR_BCAST 0x00000800
  300. #define MAC_CR_DISRTY 0x00000400
  301. #define MAC_CR_PADSTR 0x00000100
  302. #define MAC_CR_BOLMT_MASK 0x000000C0
  303. #define MAC_CR_DFCHK 0x00000020
  304. #define MAC_CR_TXEN 0x00000008
  305. #define MAC_CR_RXEN 0x00000004
  306. #define ADDRH 0x02 /* R/W mask 0x0000FFFFUL */
  307. #define ADDRL 0x03 /* R/W mask 0xFFFFFFFFUL */
  308. #define HASHH 0x04 /* R/W */
  309. #define HASHL 0x05 /* R/W */
  310. #define MII_ACC 0x06 /* R/W */
  311. #define MII_ACC_PHY_ADDR 0x0000F800
  312. #define MII_ACC_MIIRINDA 0x000007C0
  313. #define MII_ACC_MII_WRITE 0x00000002
  314. #define MII_ACC_MII_BUSY 0x00000001
  315. #define MII_DATA 0x07 /* R/W mask 0x0000FFFFUL */
  316. #define FLOW 0x08 /* R/W */
  317. #define FLOW_FCPT 0xFFFF0000
  318. #define FLOW_FCPASS 0x00000004
  319. #define FLOW_FCEN 0x00000002
  320. #define FLOW_FCBSY 0x00000001
  321. #define VLAN1 0x09 /* R/W mask 0x0000FFFFUL */
  322. #define VLAN1_VTI1 0x0000ffff
  323. #define VLAN2 0x0A /* R/W mask 0x0000FFFFUL */
  324. #define VLAN2_VTI2 0x0000ffff
  325. #define WUFF 0x0B /* WO */
  326. #define WUCSR 0x0C /* R/W */
  327. #define WUCSR_GUE 0x00000200
  328. #define WUCSR_WUFR 0x00000040
  329. #define WUCSR_MPR 0x00000020
  330. #define WUCSR_WAKE_EN 0x00000004
  331. #define WUCSR_MPEN 0x00000002
  332. /* Chip ID values */
  333. #define CHIP_89218 0x218a
  334. #define CHIP_9115 0x115
  335. #define CHIP_9116 0x116
  336. #define CHIP_9117 0x117
  337. #define CHIP_9118 0x118
  338. #define CHIP_9211 0x9211
  339. #define CHIP_9215 0x115a
  340. #define CHIP_9216 0x116a
  341. #define CHIP_9217 0x117a
  342. #define CHIP_9218 0x118a
  343. #define CHIP_9220 0x9220
  344. #define CHIP_9221 0x9221
  345. struct chip_id {
  346. u16 id;
  347. char *name;
  348. };
  349. static const struct chip_id chip_ids[] = {
  350. { CHIP_89218, "LAN89218" },
  351. { CHIP_9115, "LAN9115" },
  352. { CHIP_9116, "LAN9116" },
  353. { CHIP_9117, "LAN9117" },
  354. { CHIP_9118, "LAN9118" },
  355. { CHIP_9211, "LAN9211" },
  356. { CHIP_9215, "LAN9215" },
  357. { CHIP_9216, "LAN9216" },
  358. { CHIP_9217, "LAN9217" },
  359. { CHIP_9218, "LAN9218" },
  360. { CHIP_9220, "LAN9220" },
  361. { CHIP_9221, "LAN9221" },
  362. { 0, NULL },
  363. };
  364. static u32 smc911x_get_mac_csr(struct eth_device *dev, u8 reg)
  365. {
  366. while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
  367. ;
  368. smc911x_reg_write(dev, MAC_CSR_CMD,
  369. MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
  370. while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
  371. ;
  372. return smc911x_reg_read(dev, MAC_CSR_DATA);
  373. }
  374. static void smc911x_set_mac_csr(struct eth_device *dev, u8 reg, u32 data)
  375. {
  376. while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
  377. ;
  378. smc911x_reg_write(dev, MAC_CSR_DATA, data);
  379. smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
  380. while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY)
  381. ;
  382. }
  383. static int smc911x_detect_chip(struct eth_device *dev)
  384. {
  385. unsigned long val, i;
  386. val = smc911x_reg_read(dev, BYTE_TEST);
  387. if (val == 0xffffffff) {
  388. /* Special case -- no chip present */
  389. return -1;
  390. } else if (val != 0x87654321) {
  391. printf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
  392. return -1;
  393. }
  394. val = smc911x_reg_read(dev, ID_REV) >> 16;
  395. for (i = 0; chip_ids[i].id != 0; i++) {
  396. if (chip_ids[i].id == val) break;
  397. }
  398. if (!chip_ids[i].id) {
  399. printf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
  400. return -1;
  401. }
  402. dev->priv = (void *)&chip_ids[i];
  403. return 0;
  404. }
  405. static void smc911x_reset(struct eth_device *dev)
  406. {
  407. int timeout;
  408. /*
  409. * Take out of PM setting first
  410. * Device is already wake up if PMT_CTRL_READY bit is set
  411. */
  412. if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0) {
  413. /* Write to the bytetest will take out of powerdown */
  414. smc911x_reg_write(dev, BYTE_TEST, 0x0);
  415. timeout = 10;
  416. while (timeout-- &&
  417. !(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
  418. udelay(10);
  419. if (timeout < 0) {
  420. printf(DRIVERNAME
  421. ": timeout waiting for PM restore\n");
  422. return;
  423. }
  424. }
  425. /* Disable interrupts */
  426. smc911x_reg_write(dev, INT_EN, 0);
  427. smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST);
  428. timeout = 1000;
  429. while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
  430. udelay(10);
  431. if (timeout < 0) {
  432. printf(DRIVERNAME ": reset timeout\n");
  433. return;
  434. }
  435. /* Reset the FIFO level and flow control settings */
  436. smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN);
  437. smc911x_reg_write(dev, AFC_CFG, 0x0050287F);
  438. /* Set to LED outputs */
  439. smc911x_reg_write(dev, GPIO_CFG, 0x70070000);
  440. }
  441. #endif