pic32_eth.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
  4. *
  5. */
  6. #include <common.h>
  7. #include <errno.h>
  8. #include <dm.h>
  9. #include <net.h>
  10. #include <miiphy.h>
  11. #include <console.h>
  12. #include <wait_bit.h>
  13. #include <asm/gpio.h>
  14. #include "pic32_eth.h"
  15. #define MAX_RX_BUF_SIZE 1536
  16. #define MAX_RX_DESCR PKTBUFSRX
  17. #define MAX_TX_DESCR 2
  18. DECLARE_GLOBAL_DATA_PTR;
  19. struct pic32eth_dev {
  20. struct eth_dma_desc rxd_ring[MAX_RX_DESCR];
  21. struct eth_dma_desc txd_ring[MAX_TX_DESCR];
  22. u32 rxd_idx; /* index of RX desc to read */
  23. /* regs */
  24. struct pic32_ectl_regs *ectl_regs;
  25. struct pic32_emac_regs *emac_regs;
  26. /* Phy */
  27. struct phy_device *phydev;
  28. phy_interface_t phyif;
  29. u32 phy_addr;
  30. struct gpio_desc rst_gpio;
  31. };
  32. void __weak board_netphy_reset(void *dev)
  33. {
  34. struct pic32eth_dev *priv = dev;
  35. if (!dm_gpio_is_valid(&priv->rst_gpio))
  36. return;
  37. /* phy reset */
  38. dm_gpio_set_value(&priv->rst_gpio, 0);
  39. udelay(300);
  40. dm_gpio_set_value(&priv->rst_gpio, 1);
  41. udelay(300);
  42. }
  43. /* Initialize mii(MDIO) interface, discover which PHY is
  44. * attached to the device, and configure it properly.
  45. */
  46. static int pic32_mii_init(struct pic32eth_dev *priv)
  47. {
  48. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  49. struct pic32_emac_regs *emac_p = priv->emac_regs;
  50. /* board phy reset */
  51. board_netphy_reset(priv);
  52. /* disable RX, TX & all transactions */
  53. writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
  54. /* wait till busy */
  55. wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
  56. CONFIG_SYS_HZ, false);
  57. /* turn controller ON to access PHY over MII */
  58. writel(ETHCON_ON, &ectl_p->con1.set);
  59. mdelay(10);
  60. /* reset MAC */
  61. writel(EMAC_SOFTRESET, &emac_p->cfg1.set); /* reset assert */
  62. mdelay(10);
  63. writel(EMAC_SOFTRESET, &emac_p->cfg1.clr); /* reset deassert */
  64. /* initialize MDIO/MII */
  65. if (priv->phyif == PHY_INTERFACE_MODE_RMII) {
  66. writel(EMAC_RMII_RESET, &emac_p->supp.set);
  67. mdelay(10);
  68. writel(EMAC_RMII_RESET, &emac_p->supp.clr);
  69. }
  70. return pic32_mdio_init(PIC32_MDIO_NAME, (ulong)&emac_p->mii);
  71. }
  72. static int pic32_phy_init(struct pic32eth_dev *priv, struct udevice *dev)
  73. {
  74. struct mii_dev *mii;
  75. mii = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
  76. /* find & connect PHY */
  77. priv->phydev = phy_connect(mii, priv->phy_addr,
  78. dev, priv->phyif);
  79. if (!priv->phydev) {
  80. printf("%s: %s: Error, PHY connect\n", __FILE__, __func__);
  81. return 0;
  82. }
  83. /* Wait for phy to complete reset */
  84. mdelay(10);
  85. /* configure supported modes */
  86. priv->phydev->supported = SUPPORTED_10baseT_Half |
  87. SUPPORTED_10baseT_Full |
  88. SUPPORTED_100baseT_Half |
  89. SUPPORTED_100baseT_Full |
  90. SUPPORTED_Autoneg;
  91. priv->phydev->advertising = ADVERTISED_10baseT_Half |
  92. ADVERTISED_10baseT_Full |
  93. ADVERTISED_100baseT_Half |
  94. ADVERTISED_100baseT_Full |
  95. ADVERTISED_Autoneg;
  96. priv->phydev->autoneg = AUTONEG_ENABLE;
  97. return 0;
  98. }
  99. /* Configure MAC based on negotiated speed and duplex
  100. * reported by PHY.
  101. */
  102. static int pic32_mac_adjust_link(struct pic32eth_dev *priv)
  103. {
  104. struct phy_device *phydev = priv->phydev;
  105. struct pic32_emac_regs *emac_p = priv->emac_regs;
  106. if (!phydev->link) {
  107. printf("%s: No link.\n", phydev->dev->name);
  108. return -EINVAL;
  109. }
  110. if (phydev->duplex) {
  111. writel(EMAC_FULLDUP, &emac_p->cfg2.set);
  112. writel(FULLDUP_GAP_TIME, &emac_p->ipgt.raw);
  113. } else {
  114. writel(EMAC_FULLDUP, &emac_p->cfg2.clr);
  115. writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw);
  116. }
  117. switch (phydev->speed) {
  118. case SPEED_100:
  119. writel(EMAC_RMII_SPD100, &emac_p->supp.set);
  120. break;
  121. case SPEED_10:
  122. writel(EMAC_RMII_SPD100, &emac_p->supp.clr);
  123. break;
  124. default:
  125. printf("%s: Speed was bad\n", phydev->dev->name);
  126. return -EINVAL;
  127. }
  128. printf("pic32eth: PHY is %s with %dbase%s, %s\n",
  129. phydev->drv->name, phydev->speed,
  130. (phydev->port == PORT_TP) ? "T" : "X",
  131. (phydev->duplex) ? "full" : "half");
  132. return 0;
  133. }
  134. static void pic32_mac_init(struct pic32eth_dev *priv, u8 *macaddr)
  135. {
  136. struct pic32_emac_regs *emac_p = priv->emac_regs;
  137. u32 stat = 0, v;
  138. u64 expire;
  139. v = EMAC_TXPAUSE | EMAC_RXPAUSE | EMAC_RXENABLE;
  140. writel(v, &emac_p->cfg1.raw);
  141. v = EMAC_EXCESS | EMAC_AUTOPAD | EMAC_PADENABLE |
  142. EMAC_CRCENABLE | EMAC_LENGTHCK | EMAC_FULLDUP;
  143. writel(v, &emac_p->cfg2.raw);
  144. /* recommended back-to-back inter-packet gap for 10 Mbps half duplex */
  145. writel(HALFDUP_GAP_TIME, &emac_p->ipgt.raw);
  146. /* recommended non-back-to-back interpacket gap is 0xc12 */
  147. writel(0xc12, &emac_p->ipgr.raw);
  148. /* recommended collision window retry limit is 0x370F */
  149. writel(0x370f, &emac_p->clrt.raw);
  150. /* set maximum frame length: allow VLAN tagged frame */
  151. writel(0x600, &emac_p->maxf.raw);
  152. /* set the mac address */
  153. writel(macaddr[0] | (macaddr[1] << 8), &emac_p->sa2.raw);
  154. writel(macaddr[2] | (macaddr[3] << 8), &emac_p->sa1.raw);
  155. writel(macaddr[4] | (macaddr[5] << 8), &emac_p->sa0.raw);
  156. /* default, enable 10 Mbps operation */
  157. writel(EMAC_RMII_SPD100, &emac_p->supp.clr);
  158. /* wait until link status UP or deadline elapsed */
  159. expire = get_ticks() + get_tbclk() * 2;
  160. for (; get_ticks() < expire;) {
  161. stat = phy_read(priv->phydev, priv->phy_addr, MII_BMSR);
  162. if (stat & BMSR_LSTATUS)
  163. break;
  164. }
  165. if (!(stat & BMSR_LSTATUS))
  166. printf("MAC: Link is DOWN!\n");
  167. /* delay to stabilize before any tx/rx */
  168. mdelay(10);
  169. }
  170. static void pic32_mac_reset(struct pic32eth_dev *priv)
  171. {
  172. struct pic32_emac_regs *emac_p = priv->emac_regs;
  173. struct mii_dev *mii;
  174. /* Reset MAC */
  175. writel(EMAC_SOFTRESET, &emac_p->cfg1.raw);
  176. mdelay(10);
  177. /* clear reset */
  178. writel(0, &emac_p->cfg1.raw);
  179. /* Reset MII */
  180. mii = priv->phydev->bus;
  181. if (mii && mii->reset)
  182. mii->reset(mii);
  183. }
  184. /* initializes the MAC and PHY, then establishes a link */
  185. static void pic32_ctrl_reset(struct pic32eth_dev *priv)
  186. {
  187. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  188. u32 v;
  189. /* disable RX, TX & any other transactions */
  190. writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
  191. /* wait till busy */
  192. wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
  193. CONFIG_SYS_HZ, false);
  194. /* decrement received buffcnt to zero. */
  195. while (readl(&ectl_p->stat.raw) & ETHSTAT_BUFCNT)
  196. writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
  197. /* clear any existing interrupt event */
  198. writel(0xffffffff, &ectl_p->irq.clr);
  199. /* clear RX/TX start address */
  200. writel(0xffffffff, &ectl_p->txst.clr);
  201. writel(0xffffffff, &ectl_p->rxst.clr);
  202. /* clear the receive filters */
  203. writel(0x00ff, &ectl_p->rxfc.clr);
  204. /* set the receive filters
  205. * ETH_FILT_CRC_ERR_REJECT
  206. * ETH_FILT_RUNT_REJECT
  207. * ETH_FILT_UCAST_ACCEPT
  208. * ETH_FILT_MCAST_ACCEPT
  209. * ETH_FILT_BCAST_ACCEPT
  210. */
  211. v = ETHRXFC_BCEN | ETHRXFC_MCEN | ETHRXFC_UCEN |
  212. ETHRXFC_RUNTEN | ETHRXFC_CRCOKEN;
  213. writel(v, &ectl_p->rxfc.set);
  214. /* turn controller ON to access PHY over MII */
  215. writel(ETHCON_ON, &ectl_p->con1.set);
  216. }
  217. static void pic32_rx_desc_init(struct pic32eth_dev *priv)
  218. {
  219. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  220. struct eth_dma_desc *rxd;
  221. u32 idx, bufsz;
  222. priv->rxd_idx = 0;
  223. for (idx = 0; idx < MAX_RX_DESCR; idx++) {
  224. rxd = &priv->rxd_ring[idx];
  225. /* hw owned */
  226. rxd->hdr = EDH_NPV | EDH_EOWN | EDH_STICKY;
  227. /* packet buffer address */
  228. rxd->data_buff = virt_to_phys(net_rx_packets[idx]);
  229. /* link to next desc */
  230. rxd->next_ed = virt_to_phys(rxd + 1);
  231. /* reset status */
  232. rxd->stat1 = 0;
  233. rxd->stat2 = 0;
  234. /* decrement bufcnt */
  235. writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
  236. }
  237. /* link last descr to beginning of list */
  238. rxd->next_ed = virt_to_phys(&priv->rxd_ring[0]);
  239. /* flush rx ring */
  240. flush_dcache_range((ulong)priv->rxd_ring,
  241. (ulong)priv->rxd_ring + sizeof(priv->rxd_ring));
  242. /* set rx desc-ring start address */
  243. writel((ulong)virt_to_phys(&priv->rxd_ring[0]), &ectl_p->rxst.raw);
  244. /* RX Buffer size */
  245. bufsz = readl(&ectl_p->con2.raw);
  246. bufsz &= ~(ETHCON_RXBUFSZ << ETHCON_RXBUFSZ_SHFT);
  247. bufsz |= ((MAX_RX_BUF_SIZE / 16) << ETHCON_RXBUFSZ_SHFT);
  248. writel(bufsz, &ectl_p->con2.raw);
  249. /* enable the receiver in hardware which allows hardware
  250. * to DMA received pkts to the descriptor pointer address.
  251. */
  252. writel(ETHCON_RXEN, &ectl_p->con1.set);
  253. }
  254. static int pic32_eth_start(struct udevice *dev)
  255. {
  256. struct eth_pdata *pdata = dev_get_platdata(dev);
  257. struct pic32eth_dev *priv = dev_get_priv(dev);
  258. /* controller */
  259. pic32_ctrl_reset(priv);
  260. /* reset MAC */
  261. pic32_mac_reset(priv);
  262. /* configure PHY */
  263. phy_config(priv->phydev);
  264. /* initialize MAC */
  265. pic32_mac_init(priv, &pdata->enetaddr[0]);
  266. /* init RX descriptor; TX descriptors are handled in xmit */
  267. pic32_rx_desc_init(priv);
  268. /* Start up & update link status of PHY */
  269. phy_startup(priv->phydev);
  270. /* adjust mac with phy link status */
  271. return pic32_mac_adjust_link(priv);
  272. }
  273. static void pic32_eth_stop(struct udevice *dev)
  274. {
  275. struct pic32eth_dev *priv = dev_get_priv(dev);
  276. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  277. struct pic32_emac_regs *emac_p = priv->emac_regs;
  278. /* Reset the phy if the controller is enabled */
  279. if (readl(&ectl_p->con1.raw) & ETHCON_ON)
  280. phy_reset(priv->phydev);
  281. /* Shut down the PHY */
  282. phy_shutdown(priv->phydev);
  283. /* Stop rx/tx */
  284. writel(ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr);
  285. mdelay(10);
  286. /* reset MAC */
  287. writel(EMAC_SOFTRESET, &emac_p->cfg1.raw);
  288. /* clear reset */
  289. writel(0, &emac_p->cfg1.raw);
  290. mdelay(10);
  291. /* disable controller */
  292. writel(ETHCON_ON, &ectl_p->con1.clr);
  293. mdelay(10);
  294. /* wait until everything is down */
  295. wait_for_bit_le32(&ectl_p->stat.raw, ETHSTAT_BUSY, false,
  296. 2 * CONFIG_SYS_HZ, false);
  297. /* clear any existing interrupt event */
  298. writel(0xffffffff, &ectl_p->irq.clr);
  299. }
  300. static int pic32_eth_send(struct udevice *dev, void *packet, int length)
  301. {
  302. struct pic32eth_dev *priv = dev_get_priv(dev);
  303. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  304. struct eth_dma_desc *txd;
  305. u64 deadline;
  306. txd = &priv->txd_ring[0];
  307. /* set proper flags & length in descriptor header */
  308. txd->hdr = EDH_SOP | EDH_EOP | EDH_EOWN | EDH_BCOUNT(length);
  309. /* pass buffer address to hardware */
  310. txd->data_buff = virt_to_phys(packet);
  311. debug("%s: %d / .hdr %x, .data_buff %x, .stat %x, .nexted %x\n",
  312. __func__, __LINE__, txd->hdr, txd->data_buff, txd->stat2,
  313. txd->next_ed);
  314. /* cache flush (packet) */
  315. flush_dcache_range((ulong)packet, (ulong)packet + length);
  316. /* cache flush (txd) */
  317. flush_dcache_range((ulong)txd, (ulong)txd + sizeof(*txd));
  318. /* pass descriptor table base to h/w */
  319. writel(virt_to_phys(txd), &ectl_p->txst.raw);
  320. /* ready to send enabled, hardware can now send the packet(s) */
  321. writel(ETHCON_TXRTS | ETHCON_ON, &ectl_p->con1.set);
  322. /* wait until tx has completed and h/w has released ownership
  323. * of the tx descriptor or timeout elapsed.
  324. */
  325. deadline = get_ticks() + get_tbclk();
  326. for (;;) {
  327. /* check timeout */
  328. if (get_ticks() > deadline)
  329. return -ETIMEDOUT;
  330. if (ctrlc())
  331. return -EINTR;
  332. /* tx completed ? */
  333. if (readl(&ectl_p->con1.raw) & ETHCON_TXRTS) {
  334. udelay(1);
  335. continue;
  336. }
  337. /* h/w not released ownership yet? */
  338. invalidate_dcache_range((ulong)txd, (ulong)txd + sizeof(*txd));
  339. if (!(txd->hdr & EDH_EOWN))
  340. break;
  341. }
  342. return 0;
  343. }
  344. static int pic32_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  345. {
  346. struct pic32eth_dev *priv = dev_get_priv(dev);
  347. struct eth_dma_desc *rxd;
  348. u32 idx = priv->rxd_idx;
  349. u32 rx_count;
  350. /* find the next ready to receive */
  351. rxd = &priv->rxd_ring[idx];
  352. invalidate_dcache_range((ulong)rxd, (ulong)rxd + sizeof(*rxd));
  353. /* check if owned by MAC */
  354. if (rxd->hdr & EDH_EOWN)
  355. return -EAGAIN;
  356. /* Sanity check on header: SOP and EOP */
  357. if ((rxd->hdr & (EDH_SOP | EDH_EOP)) != (EDH_SOP | EDH_EOP)) {
  358. printf("%s: %s, rx pkt across multiple descr\n",
  359. __FILE__, __func__);
  360. return 0;
  361. }
  362. debug("%s: %d /idx %i, hdr=%x, data_buff %x, stat %x, nexted %x\n",
  363. __func__, __LINE__, idx, rxd->hdr,
  364. rxd->data_buff, rxd->stat2, rxd->next_ed);
  365. /* Sanity check on rx_stat: OK, CRC */
  366. if (!RSV_RX_OK(rxd->stat2) || RSV_CRC_ERR(rxd->stat2)) {
  367. debug("%s: %s: Error, rx problem detected\n",
  368. __FILE__, __func__);
  369. return 0;
  370. }
  371. /* invalidate dcache */
  372. rx_count = RSV_RX_COUNT(rxd->stat2);
  373. invalidate_dcache_range((ulong)net_rx_packets[idx],
  374. (ulong)net_rx_packets[idx] + rx_count);
  375. /* Pass the packet to protocol layer */
  376. *packetp = net_rx_packets[idx];
  377. /* increment number of bytes rcvd (ignore CRC) */
  378. return rx_count - 4;
  379. }
  380. static int pic32_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
  381. {
  382. struct pic32eth_dev *priv = dev_get_priv(dev);
  383. struct pic32_ectl_regs *ectl_p = priv->ectl_regs;
  384. struct eth_dma_desc *rxd;
  385. int idx = priv->rxd_idx;
  386. /* sanity check */
  387. if (packet != net_rx_packets[idx]) {
  388. printf("rxd_id %d: packet is not matched,\n", idx);
  389. return -EAGAIN;
  390. }
  391. /* prepare for receive */
  392. rxd = &priv->rxd_ring[idx];
  393. rxd->hdr = EDH_STICKY | EDH_NPV | EDH_EOWN;
  394. flush_dcache_range((ulong)rxd, (ulong)rxd + sizeof(*rxd));
  395. /* decrement rx pkt count */
  396. writel(ETHCON_BUFCDEC, &ectl_p->con1.set);
  397. debug("%s: %d / idx %i, hdr %x, data_buff %x, stat %x, nexted %x\n",
  398. __func__, __LINE__, idx, rxd->hdr, rxd->data_buff,
  399. rxd->stat2, rxd->next_ed);
  400. priv->rxd_idx = (priv->rxd_idx + 1) % MAX_RX_DESCR;
  401. return 0;
  402. }
  403. static const struct eth_ops pic32_eth_ops = {
  404. .start = pic32_eth_start,
  405. .send = pic32_eth_send,
  406. .recv = pic32_eth_recv,
  407. .free_pkt = pic32_eth_free_pkt,
  408. .stop = pic32_eth_stop,
  409. };
  410. static int pic32_eth_probe(struct udevice *dev)
  411. {
  412. struct eth_pdata *pdata = dev_get_platdata(dev);
  413. struct pic32eth_dev *priv = dev_get_priv(dev);
  414. const char *phy_mode;
  415. void __iomem *iobase;
  416. fdt_addr_t addr;
  417. fdt_size_t size;
  418. int offset = 0;
  419. int phy_addr = -1;
  420. addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
  421. &size);
  422. if (addr == FDT_ADDR_T_NONE)
  423. return -EINVAL;
  424. iobase = ioremap(addr, size);
  425. pdata->iobase = (phys_addr_t)addr;
  426. /* get phy mode */
  427. pdata->phy_interface = -1;
  428. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  429. NULL);
  430. if (phy_mode)
  431. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  432. if (pdata->phy_interface == -1) {
  433. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  434. return -EINVAL;
  435. }
  436. /* get phy addr */
  437. offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
  438. "phy-handle");
  439. if (offset > 0)
  440. phy_addr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
  441. /* phy reset gpio */
  442. gpio_request_by_name_nodev(dev_ofnode(dev), "reset-gpios", 0,
  443. &priv->rst_gpio, GPIOD_IS_OUT);
  444. priv->phyif = pdata->phy_interface;
  445. priv->phy_addr = phy_addr;
  446. priv->ectl_regs = iobase;
  447. priv->emac_regs = iobase + PIC32_EMAC1CFG1;
  448. pic32_mii_init(priv);
  449. return pic32_phy_init(priv, dev);
  450. }
  451. static int pic32_eth_remove(struct udevice *dev)
  452. {
  453. struct pic32eth_dev *priv = dev_get_priv(dev);
  454. struct mii_dev *bus;
  455. dm_gpio_free(dev, &priv->rst_gpio);
  456. phy_shutdown(priv->phydev);
  457. free(priv->phydev);
  458. bus = miiphy_get_dev_by_name(PIC32_MDIO_NAME);
  459. mdio_unregister(bus);
  460. mdio_free(bus);
  461. iounmap(priv->ectl_regs);
  462. return 0;
  463. }
  464. static const struct udevice_id pic32_eth_ids[] = {
  465. { .compatible = "microchip,pic32mzda-eth" },
  466. { }
  467. };
  468. U_BOOT_DRIVER(pic32_ethernet) = {
  469. .name = "pic32_ethernet",
  470. .id = UCLASS_ETH,
  471. .of_match = pic32_eth_ids,
  472. .probe = pic32_eth_probe,
  473. .remove = pic32_eth_remove,
  474. .ops = &pic32_eth_ops,
  475. .priv_auto_alloc_size = sizeof(struct pic32eth_dev),
  476. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  477. };