pch_gbe.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  4. *
  5. * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <asm/io.h>
  11. #include <pci.h>
  12. #include <miiphy.h>
  13. #include "pch_gbe.h"
  14. #if !defined(CONFIG_PHYLIB)
  15. # error "PCH Gigabit Ethernet driver requires PHYLIB - missing CONFIG_PHYLIB"
  16. #endif
  17. static struct pci_device_id supported[] = {
  18. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_GBE) },
  19. { }
  20. };
  21. static void pch_gbe_mac_read(struct pch_gbe_regs *mac_regs, u8 *addr)
  22. {
  23. u32 macid_hi, macid_lo;
  24. macid_hi = readl(&mac_regs->mac_adr[0].high);
  25. macid_lo = readl(&mac_regs->mac_adr[0].low) & 0xffff;
  26. debug("pch_gbe: macid_hi %#x macid_lo %#x\n", macid_hi, macid_lo);
  27. addr[0] = (u8)(macid_hi & 0xff);
  28. addr[1] = (u8)((macid_hi >> 8) & 0xff);
  29. addr[2] = (u8)((macid_hi >> 16) & 0xff);
  30. addr[3] = (u8)((macid_hi >> 24) & 0xff);
  31. addr[4] = (u8)(macid_lo & 0xff);
  32. addr[5] = (u8)((macid_lo >> 8) & 0xff);
  33. }
  34. static int pch_gbe_mac_write(struct pch_gbe_regs *mac_regs, u8 *addr)
  35. {
  36. u32 macid_hi, macid_lo;
  37. ulong start;
  38. macid_hi = addr[0] + (addr[1] << 8) + (addr[2] << 16) + (addr[3] << 24);
  39. macid_lo = addr[4] + (addr[5] << 8);
  40. writel(macid_hi, &mac_regs->mac_adr[0].high);
  41. writel(macid_lo, &mac_regs->mac_adr[0].low);
  42. writel(0xfffe, &mac_regs->addr_mask);
  43. start = get_timer(0);
  44. while (get_timer(start) < PCH_GBE_TIMEOUT) {
  45. if (!(readl(&mac_regs->addr_mask) & PCH_GBE_BUSY))
  46. return 0;
  47. udelay(10);
  48. }
  49. return -ETIME;
  50. }
  51. static int pch_gbe_reset(struct udevice *dev)
  52. {
  53. struct pch_gbe_priv *priv = dev_get_priv(dev);
  54. struct eth_pdata *plat = dev_get_platdata(dev);
  55. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  56. ulong start;
  57. priv->rx_idx = 0;
  58. priv->tx_idx = 0;
  59. writel(PCH_GBE_ALL_RST, &mac_regs->reset);
  60. /*
  61. * Configure the MAC to RGMII mode after reset
  62. *
  63. * For some unknown reason, we must do the configuration here right
  64. * after resetting the whole MAC, otherwise the reset bit in the RESET
  65. * register will never be cleared by the hardware. And there is another
  66. * way of having the same magic, that is to configure the MODE register
  67. * to have the MAC work in MII/GMII mode, which is how current Linux
  68. * pch_gbe driver does. Since anyway we need program the MAC to RGMII
  69. * mode in the driver, we just do it here.
  70. *
  71. * Note: this behavior is not documented in the hardware manual.
  72. */
  73. writel(PCH_GBE_RGMII_MODE_RGMII | PCH_GBE_CHIP_TYPE_INTERNAL,
  74. &mac_regs->rgmii_ctrl);
  75. start = get_timer(0);
  76. while (get_timer(start) < PCH_GBE_TIMEOUT) {
  77. if (!(readl(&mac_regs->reset) & PCH_GBE_ALL_RST)) {
  78. /*
  79. * Soft reset clears hardware MAC address registers,
  80. * so we have to reload MAC address here in order to
  81. * make linux pch_gbe driver happy.
  82. */
  83. return pch_gbe_mac_write(mac_regs, plat->enetaddr);
  84. }
  85. udelay(10);
  86. }
  87. debug("pch_gbe: reset timeout\n");
  88. return -ETIME;
  89. }
  90. static void pch_gbe_rx_descs_init(struct udevice *dev)
  91. {
  92. struct pch_gbe_priv *priv = dev_get_priv(dev);
  93. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  94. struct pch_gbe_rx_desc *rx_desc = &priv->rx_desc[0];
  95. int i;
  96. memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM);
  97. for (i = 0; i < PCH_GBE_DESC_NUM; i++)
  98. rx_desc[i].buffer_addr = dm_pci_virt_to_mem(priv->dev,
  99. priv->rx_buff[i]);
  100. flush_dcache_range((ulong)rx_desc, (ulong)&rx_desc[PCH_GBE_DESC_NUM]);
  101. writel(dm_pci_virt_to_mem(priv->dev, rx_desc),
  102. &mac_regs->rx_dsc_base);
  103. writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1),
  104. &mac_regs->rx_dsc_size);
  105. writel(dm_pci_virt_to_mem(priv->dev, rx_desc + 1),
  106. &mac_regs->rx_dsc_sw_p);
  107. }
  108. static void pch_gbe_tx_descs_init(struct udevice *dev)
  109. {
  110. struct pch_gbe_priv *priv = dev_get_priv(dev);
  111. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  112. struct pch_gbe_tx_desc *tx_desc = &priv->tx_desc[0];
  113. memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM);
  114. flush_dcache_range((ulong)tx_desc, (ulong)&tx_desc[PCH_GBE_DESC_NUM]);
  115. writel(dm_pci_virt_to_mem(priv->dev, tx_desc),
  116. &mac_regs->tx_dsc_base);
  117. writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1),
  118. &mac_regs->tx_dsc_size);
  119. writel(dm_pci_virt_to_mem(priv->dev, tx_desc + 1),
  120. &mac_regs->tx_dsc_sw_p);
  121. }
  122. static void pch_gbe_adjust_link(struct pch_gbe_regs *mac_regs,
  123. struct phy_device *phydev)
  124. {
  125. if (!phydev->link) {
  126. printf("%s: No link.\n", phydev->dev->name);
  127. return;
  128. }
  129. clrbits_le32(&mac_regs->rgmii_ctrl,
  130. PCH_GBE_RGMII_RATE_2_5M | PCH_GBE_CRS_SEL);
  131. clrbits_le32(&mac_regs->mode,
  132. PCH_GBE_MODE_GMII_ETHER | PCH_GBE_MODE_FULL_DUPLEX);
  133. switch (phydev->speed) {
  134. case 1000:
  135. setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_125M);
  136. setbits_le32(&mac_regs->mode, PCH_GBE_MODE_GMII_ETHER);
  137. break;
  138. case 100:
  139. setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_25M);
  140. setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
  141. break;
  142. case 10:
  143. setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_2_5M);
  144. setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
  145. break;
  146. }
  147. if (phydev->duplex) {
  148. setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_CRS_SEL);
  149. setbits_le32(&mac_regs->mode, PCH_GBE_MODE_FULL_DUPLEX);
  150. }
  151. printf("Speed: %d, %s duplex\n", phydev->speed,
  152. (phydev->duplex) ? "full" : "half");
  153. return;
  154. }
  155. static int pch_gbe_start(struct udevice *dev)
  156. {
  157. struct pch_gbe_priv *priv = dev_get_priv(dev);
  158. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  159. if (pch_gbe_reset(dev))
  160. return -1;
  161. pch_gbe_rx_descs_init(dev);
  162. pch_gbe_tx_descs_init(dev);
  163. /* Enable frame bursting */
  164. writel(PCH_GBE_MODE_FR_BST, &mac_regs->mode);
  165. /* Disable TCP/IP accelerator */
  166. writel(PCH_GBE_RX_TCPIPACC_OFF, &mac_regs->tcpip_acc);
  167. /* Disable RX flow control */
  168. writel(0, &mac_regs->rx_fctrl);
  169. /* Configure RX/TX mode */
  170. writel(PCH_GBE_RH_ALM_EMP_16 | PCH_GBE_RH_ALM_FULL_16 |
  171. PCH_GBE_RH_RD_TRG_32, &mac_regs->rx_mode);
  172. writel(PCH_GBE_TM_TH_TX_STRT_32 | PCH_GBE_TM_TH_ALM_EMP_16 |
  173. PCH_GBE_TM_TH_ALM_FULL_32 | PCH_GBE_TM_ST_AND_FD |
  174. PCH_GBE_TM_SHORT_PKT, &mac_regs->tx_mode);
  175. /* Start up the PHY */
  176. if (phy_startup(priv->phydev)) {
  177. printf("Could not initialize PHY %s\n",
  178. priv->phydev->dev->name);
  179. return -1;
  180. }
  181. pch_gbe_adjust_link(mac_regs, priv->phydev);
  182. if (!priv->phydev->link)
  183. return -1;
  184. /* Enable TX & RX */
  185. writel(PCH_GBE_RX_DMA_EN | PCH_GBE_TX_DMA_EN, &mac_regs->dma_ctrl);
  186. writel(PCH_GBE_MRE_MAC_RX_EN, &mac_regs->mac_rx_en);
  187. return 0;
  188. }
  189. static void pch_gbe_stop(struct udevice *dev)
  190. {
  191. struct pch_gbe_priv *priv = dev_get_priv(dev);
  192. pch_gbe_reset(dev);
  193. phy_shutdown(priv->phydev);
  194. }
  195. static int pch_gbe_send(struct udevice *dev, void *packet, int length)
  196. {
  197. struct pch_gbe_priv *priv = dev_get_priv(dev);
  198. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  199. struct pch_gbe_tx_desc *tx_head, *tx_desc;
  200. u16 frame_ctrl = 0;
  201. u32 int_st;
  202. ulong start;
  203. flush_dcache_range((ulong)packet, (ulong)packet + length);
  204. tx_head = &priv->tx_desc[0];
  205. tx_desc = &priv->tx_desc[priv->tx_idx];
  206. if (length < 64)
  207. frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
  208. tx_desc->buffer_addr = dm_pci_virt_to_mem(priv->dev, packet);
  209. tx_desc->length = length;
  210. tx_desc->tx_words_eob = length + 3;
  211. tx_desc->tx_frame_ctrl = frame_ctrl;
  212. tx_desc->dma_status = 0;
  213. tx_desc->gbec_status = 0;
  214. flush_dcache_range((ulong)tx_desc, (ulong)&tx_desc[1]);
  215. /* Test the wrap-around condition */
  216. if (++priv->tx_idx >= PCH_GBE_DESC_NUM)
  217. priv->tx_idx = 0;
  218. writel(dm_pci_virt_to_mem(priv->dev, tx_head + priv->tx_idx),
  219. &mac_regs->tx_dsc_sw_p);
  220. start = get_timer(0);
  221. while (get_timer(start) < PCH_GBE_TIMEOUT) {
  222. int_st = readl(&mac_regs->int_st);
  223. if (int_st & PCH_GBE_INT_TX_CMPLT)
  224. return 0;
  225. udelay(10);
  226. }
  227. debug("pch_gbe: sent failed\n");
  228. return -ETIME;
  229. }
  230. static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp)
  231. {
  232. struct pch_gbe_priv *priv = dev_get_priv(dev);
  233. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  234. struct pch_gbe_rx_desc *rx_desc;
  235. ulong hw_desc, length;
  236. void *buffer;
  237. rx_desc = &priv->rx_desc[priv->rx_idx];
  238. readl(&mac_regs->int_st);
  239. hw_desc = readl(&mac_regs->rx_dsc_hw_p_hld);
  240. /* Just return if not receiving any packet */
  241. if (virt_to_phys(rx_desc) == hw_desc)
  242. return -EAGAIN;
  243. /* Invalidate the descriptor */
  244. invalidate_dcache_range((ulong)rx_desc, (ulong)&rx_desc[1]);
  245. length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN;
  246. buffer = dm_pci_mem_to_virt(priv->dev, rx_desc->buffer_addr, length, 0);
  247. invalidate_dcache_range((ulong)buffer, (ulong)buffer + length);
  248. *packetp = (uchar *)buffer;
  249. return length;
  250. }
  251. static int pch_gbe_free_pkt(struct udevice *dev, uchar *packet, int length)
  252. {
  253. struct pch_gbe_priv *priv = dev_get_priv(dev);
  254. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  255. struct pch_gbe_rx_desc *rx_head = &priv->rx_desc[0];
  256. int rx_swp;
  257. /* Test the wrap-around condition */
  258. if (++priv->rx_idx >= PCH_GBE_DESC_NUM)
  259. priv->rx_idx = 0;
  260. rx_swp = priv->rx_idx;
  261. if (++rx_swp >= PCH_GBE_DESC_NUM)
  262. rx_swp = 0;
  263. writel(dm_pci_virt_to_mem(priv->dev, rx_head + rx_swp),
  264. &mac_regs->rx_dsc_sw_p);
  265. return 0;
  266. }
  267. static int pch_gbe_mdio_ready(struct pch_gbe_regs *mac_regs)
  268. {
  269. ulong start = get_timer(0);
  270. while (get_timer(start) < PCH_GBE_TIMEOUT) {
  271. if (readl(&mac_regs->miim) & PCH_GBE_MIIM_OPER_READY)
  272. return 0;
  273. udelay(10);
  274. }
  275. return -ETIME;
  276. }
  277. static int pch_gbe_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  278. {
  279. struct pch_gbe_regs *mac_regs = bus->priv;
  280. u32 miim;
  281. if (pch_gbe_mdio_ready(mac_regs))
  282. return -ETIME;
  283. miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
  284. (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
  285. PCH_GBE_MIIM_OPER_READ;
  286. writel(miim, &mac_regs->miim);
  287. if (pch_gbe_mdio_ready(mac_regs))
  288. return -ETIME;
  289. return readl(&mac_regs->miim) & 0xffff;
  290. }
  291. static int pch_gbe_mdio_write(struct mii_dev *bus, int addr, int devad,
  292. int reg, u16 val)
  293. {
  294. struct pch_gbe_regs *mac_regs = bus->priv;
  295. u32 miim;
  296. if (pch_gbe_mdio_ready(mac_regs))
  297. return -ETIME;
  298. miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
  299. (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
  300. PCH_GBE_MIIM_OPER_WRITE | val;
  301. writel(miim, &mac_regs->miim);
  302. if (pch_gbe_mdio_ready(mac_regs))
  303. return -ETIME;
  304. else
  305. return 0;
  306. }
  307. static int pch_gbe_mdio_init(const char *name, struct pch_gbe_regs *mac_regs)
  308. {
  309. struct mii_dev *bus;
  310. bus = mdio_alloc();
  311. if (!bus) {
  312. debug("pch_gbe: failed to allocate MDIO bus\n");
  313. return -ENOMEM;
  314. }
  315. bus->read = pch_gbe_mdio_read;
  316. bus->write = pch_gbe_mdio_write;
  317. strcpy(bus->name, name);
  318. bus->priv = (void *)mac_regs;
  319. return mdio_register(bus);
  320. }
  321. static int pch_gbe_phy_init(struct udevice *dev)
  322. {
  323. struct pch_gbe_priv *priv = dev_get_priv(dev);
  324. struct eth_pdata *plat = dev_get_platdata(dev);
  325. struct phy_device *phydev;
  326. int mask = 0xffffffff;
  327. phydev = phy_find_by_mask(priv->bus, mask, plat->phy_interface);
  328. if (!phydev) {
  329. printf("pch_gbe: cannot find the phy\n");
  330. return -1;
  331. }
  332. phy_connect_dev(phydev, dev);
  333. phydev->supported &= PHY_GBIT_FEATURES;
  334. phydev->advertising = phydev->supported;
  335. priv->phydev = phydev;
  336. phy_config(phydev);
  337. return 0;
  338. }
  339. static int pch_gbe_probe(struct udevice *dev)
  340. {
  341. struct pch_gbe_priv *priv;
  342. struct eth_pdata *plat = dev_get_platdata(dev);
  343. void *iobase;
  344. int err;
  345. /*
  346. * The priv structure contains the descriptors and frame buffers which
  347. * need a strict buswidth alignment (64 bytes). This is guaranteed by
  348. * DM_FLAG_ALLOC_PRIV_DMA flag in the U_BOOT_DRIVER.
  349. */
  350. priv = dev_get_priv(dev);
  351. priv->dev = dev;
  352. iobase = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, PCI_REGION_MEM);
  353. plat->iobase = (ulong)iobase;
  354. priv->mac_regs = (struct pch_gbe_regs *)iobase;
  355. /* Read MAC address from SROM and initialize dev->enetaddr with it */
  356. pch_gbe_mac_read(priv->mac_regs, plat->enetaddr);
  357. plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
  358. pch_gbe_mdio_init(dev->name, priv->mac_regs);
  359. priv->bus = miiphy_get_dev_by_name(dev->name);
  360. err = pch_gbe_reset(dev);
  361. if (err)
  362. return err;
  363. return pch_gbe_phy_init(dev);
  364. }
  365. static int pch_gbe_remove(struct udevice *dev)
  366. {
  367. struct pch_gbe_priv *priv = dev_get_priv(dev);
  368. free(priv->phydev);
  369. mdio_unregister(priv->bus);
  370. mdio_free(priv->bus);
  371. return 0;
  372. }
  373. static const struct eth_ops pch_gbe_ops = {
  374. .start = pch_gbe_start,
  375. .send = pch_gbe_send,
  376. .recv = pch_gbe_recv,
  377. .free_pkt = pch_gbe_free_pkt,
  378. .stop = pch_gbe_stop,
  379. };
  380. static const struct udevice_id pch_gbe_ids[] = {
  381. { .compatible = "intel,pch-gbe" },
  382. { }
  383. };
  384. U_BOOT_DRIVER(eth_pch_gbe) = {
  385. .name = "pch_gbe",
  386. .id = UCLASS_ETH,
  387. .of_match = pch_gbe_ids,
  388. .probe = pch_gbe_probe,
  389. .remove = pch_gbe_remove,
  390. .ops = &pch_gbe_ops,
  391. .priv_auto_alloc_size = sizeof(struct pch_gbe_priv),
  392. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  393. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  394. };
  395. U_BOOT_PCI_DEVICE(eth_pch_gbe, supported);