mvpp2.c 153 KB

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  1. /*
  2. * Driver for Marvell PPv2 network controller for Armada 375 SoC.
  3. *
  4. * Copyright (C) 2014 Marvell
  5. *
  6. * Marcin Wojtas <mw@semihalf.com>
  7. *
  8. * U-Boot version:
  9. * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
  10. *
  11. * This file is licensed under the terms of the GNU General Public
  12. * License version 2. This program is licensed "as is" without any
  13. * warranty of any kind, whether express or implied.
  14. */
  15. #include <common.h>
  16. #include <dm.h>
  17. #include <dm/device-internal.h>
  18. #include <dm/lists.h>
  19. #include <net.h>
  20. #include <netdev.h>
  21. #include <config.h>
  22. #include <malloc.h>
  23. #include <asm/io.h>
  24. #include <linux/errno.h>
  25. #include <phy.h>
  26. #include <miiphy.h>
  27. #include <watchdog.h>
  28. #include <asm/arch/cpu.h>
  29. #include <asm/arch/soc.h>
  30. #include <linux/compat.h>
  31. #include <linux/mbus.h>
  32. #include <asm-generic/gpio.h>
  33. #include <fdt_support.h>
  34. DECLARE_GLOBAL_DATA_PTR;
  35. #define __verify_pcpu_ptr(ptr) \
  36. do { \
  37. const void __percpu *__vpp_verify = (typeof((ptr) + 0))NULL; \
  38. (void)__vpp_verify; \
  39. } while (0)
  40. #define VERIFY_PERCPU_PTR(__p) \
  41. ({ \
  42. __verify_pcpu_ptr(__p); \
  43. (typeof(*(__p)) __kernel __force *)(__p); \
  44. })
  45. #define per_cpu_ptr(ptr, cpu) ({ (void)(cpu); VERIFY_PERCPU_PTR(ptr); })
  46. #define smp_processor_id() 0
  47. #define num_present_cpus() 1
  48. #define for_each_present_cpu(cpu) \
  49. for ((cpu) = 0; (cpu) < 1; (cpu)++)
  50. #define NET_SKB_PAD max(32, MVPP2_CPU_D_CACHE_LINE_SIZE)
  51. #define CONFIG_NR_CPUS 1
  52. /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
  53. #define WRAP (2 + ETH_HLEN + 4 + 32)
  54. #define MTU 1500
  55. #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
  56. #define MVPP2_SMI_TIMEOUT 10000
  57. /* RX Fifo Registers */
  58. #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
  59. #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
  60. #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
  61. #define MVPP2_RX_FIFO_INIT_REG 0x64
  62. /* RX DMA Top Registers */
  63. #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
  64. #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
  65. #define MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK BIT(31)
  66. #define MVPP2_POOL_BUF_SIZE_REG(pool) (0x180 + 4 * (pool))
  67. #define MVPP2_POOL_BUF_SIZE_OFFSET 5
  68. #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
  69. #define MVPP2_SNOOP_PKT_SIZE_MASK 0x1ff
  70. #define MVPP2_SNOOP_BUF_HDR_MASK BIT(9)
  71. #define MVPP2_RXQ_POOL_SHORT_OFFS 20
  72. #define MVPP21_RXQ_POOL_SHORT_MASK 0x700000
  73. #define MVPP22_RXQ_POOL_SHORT_MASK 0xf00000
  74. #define MVPP2_RXQ_POOL_LONG_OFFS 24
  75. #define MVPP21_RXQ_POOL_LONG_MASK 0x7000000
  76. #define MVPP22_RXQ_POOL_LONG_MASK 0xf000000
  77. #define MVPP2_RXQ_PACKET_OFFSET_OFFS 28
  78. #define MVPP2_RXQ_PACKET_OFFSET_MASK 0x70000000
  79. #define MVPP2_RXQ_DISABLE_MASK BIT(31)
  80. /* Parser Registers */
  81. #define MVPP2_PRS_INIT_LOOKUP_REG 0x1000
  82. #define MVPP2_PRS_PORT_LU_MAX 0xf
  83. #define MVPP2_PRS_PORT_LU_MASK(port) (0xff << ((port) * 4))
  84. #define MVPP2_PRS_PORT_LU_VAL(port, val) ((val) << ((port) * 4))
  85. #define MVPP2_PRS_INIT_OFFS_REG(port) (0x1004 + ((port) & 4))
  86. #define MVPP2_PRS_INIT_OFF_MASK(port) (0x3f << (((port) % 4) * 8))
  87. #define MVPP2_PRS_INIT_OFF_VAL(port, val) ((val) << (((port) % 4) * 8))
  88. #define MVPP2_PRS_MAX_LOOP_REG(port) (0x100c + ((port) & 4))
  89. #define MVPP2_PRS_MAX_LOOP_MASK(port) (0xff << (((port) % 4) * 8))
  90. #define MVPP2_PRS_MAX_LOOP_VAL(port, val) ((val) << (((port) % 4) * 8))
  91. #define MVPP2_PRS_TCAM_IDX_REG 0x1100
  92. #define MVPP2_PRS_TCAM_DATA_REG(idx) (0x1104 + (idx) * 4)
  93. #define MVPP2_PRS_TCAM_INV_MASK BIT(31)
  94. #define MVPP2_PRS_SRAM_IDX_REG 0x1200
  95. #define MVPP2_PRS_SRAM_DATA_REG(idx) (0x1204 + (idx) * 4)
  96. #define MVPP2_PRS_TCAM_CTRL_REG 0x1230
  97. #define MVPP2_PRS_TCAM_EN_MASK BIT(0)
  98. /* Classifier Registers */
  99. #define MVPP2_CLS_MODE_REG 0x1800
  100. #define MVPP2_CLS_MODE_ACTIVE_MASK BIT(0)
  101. #define MVPP2_CLS_PORT_WAY_REG 0x1810
  102. #define MVPP2_CLS_PORT_WAY_MASK(port) (1 << (port))
  103. #define MVPP2_CLS_LKP_INDEX_REG 0x1814
  104. #define MVPP2_CLS_LKP_INDEX_WAY_OFFS 6
  105. #define MVPP2_CLS_LKP_TBL_REG 0x1818
  106. #define MVPP2_CLS_LKP_TBL_RXQ_MASK 0xff
  107. #define MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK BIT(25)
  108. #define MVPP2_CLS_FLOW_INDEX_REG 0x1820
  109. #define MVPP2_CLS_FLOW_TBL0_REG 0x1824
  110. #define MVPP2_CLS_FLOW_TBL1_REG 0x1828
  111. #define MVPP2_CLS_FLOW_TBL2_REG 0x182c
  112. #define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port) (0x1980 + ((port) * 4))
  113. #define MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS 3
  114. #define MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK 0x7
  115. #define MVPP2_CLS_SWFWD_P2HQ_REG(port) (0x19b0 + ((port) * 4))
  116. #define MVPP2_CLS_SWFWD_PCTRL_REG 0x19d0
  117. #define MVPP2_CLS_SWFWD_PCTRL_MASK(port) (1 << (port))
  118. /* Descriptor Manager Top Registers */
  119. #define MVPP2_RXQ_NUM_REG 0x2040
  120. #define MVPP2_RXQ_DESC_ADDR_REG 0x2044
  121. #define MVPP22_DESC_ADDR_OFFS 8
  122. #define MVPP2_RXQ_DESC_SIZE_REG 0x2048
  123. #define MVPP2_RXQ_DESC_SIZE_MASK 0x3ff0
  124. #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
  125. #define MVPP2_RXQ_NUM_PROCESSED_OFFSET 0
  126. #define MVPP2_RXQ_NUM_NEW_OFFSET 16
  127. #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
  128. #define MVPP2_RXQ_OCCUPIED_MASK 0x3fff
  129. #define MVPP2_RXQ_NON_OCCUPIED_OFFSET 16
  130. #define MVPP2_RXQ_NON_OCCUPIED_MASK 0x3fff0000
  131. #define MVPP2_RXQ_THRESH_REG 0x204c
  132. #define MVPP2_OCCUPIED_THRESH_OFFSET 0
  133. #define MVPP2_OCCUPIED_THRESH_MASK 0x3fff
  134. #define MVPP2_RXQ_INDEX_REG 0x2050
  135. #define MVPP2_TXQ_NUM_REG 0x2080
  136. #define MVPP2_TXQ_DESC_ADDR_REG 0x2084
  137. #define MVPP2_TXQ_DESC_SIZE_REG 0x2088
  138. #define MVPP2_TXQ_DESC_SIZE_MASK 0x3ff0
  139. #define MVPP2_AGGR_TXQ_UPDATE_REG 0x2090
  140. #define MVPP2_TXQ_THRESH_REG 0x2094
  141. #define MVPP2_TRANSMITTED_THRESH_OFFSET 16
  142. #define MVPP2_TRANSMITTED_THRESH_MASK 0x3fff0000
  143. #define MVPP2_TXQ_INDEX_REG 0x2098
  144. #define MVPP2_TXQ_PREF_BUF_REG 0x209c
  145. #define MVPP2_PREF_BUF_PTR(desc) ((desc) & 0xfff)
  146. #define MVPP2_PREF_BUF_SIZE_4 (BIT(12) | BIT(13))
  147. #define MVPP2_PREF_BUF_SIZE_16 (BIT(12) | BIT(14))
  148. #define MVPP2_PREF_BUF_THRESH(val) ((val) << 17)
  149. #define MVPP2_TXQ_DRAIN_EN_MASK BIT(31)
  150. #define MVPP2_TXQ_PENDING_REG 0x20a0
  151. #define MVPP2_TXQ_PENDING_MASK 0x3fff
  152. #define MVPP2_TXQ_INT_STATUS_REG 0x20a4
  153. #define MVPP2_TXQ_SENT_REG(txq) (0x3c00 + 4 * (txq))
  154. #define MVPP2_TRANSMITTED_COUNT_OFFSET 16
  155. #define MVPP2_TRANSMITTED_COUNT_MASK 0x3fff0000
  156. #define MVPP2_TXQ_RSVD_REQ_REG 0x20b0
  157. #define MVPP2_TXQ_RSVD_REQ_Q_OFFSET 16
  158. #define MVPP2_TXQ_RSVD_RSLT_REG 0x20b4
  159. #define MVPP2_TXQ_RSVD_RSLT_MASK 0x3fff
  160. #define MVPP2_TXQ_RSVD_CLR_REG 0x20b8
  161. #define MVPP2_TXQ_RSVD_CLR_OFFSET 16
  162. #define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu) (0x2100 + 4 * (cpu))
  163. #define MVPP22_AGGR_TXQ_DESC_ADDR_OFFS 8
  164. #define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu) (0x2140 + 4 * (cpu))
  165. #define MVPP2_AGGR_TXQ_DESC_SIZE_MASK 0x3ff0
  166. #define MVPP2_AGGR_TXQ_STATUS_REG(cpu) (0x2180 + 4 * (cpu))
  167. #define MVPP2_AGGR_TXQ_PENDING_MASK 0x3fff
  168. #define MVPP2_AGGR_TXQ_INDEX_REG(cpu) (0x21c0 + 4 * (cpu))
  169. /* MBUS bridge registers */
  170. #define MVPP2_WIN_BASE(w) (0x4000 + ((w) << 2))
  171. #define MVPP2_WIN_SIZE(w) (0x4020 + ((w) << 2))
  172. #define MVPP2_WIN_REMAP(w) (0x4040 + ((w) << 2))
  173. #define MVPP2_BASE_ADDR_ENABLE 0x4060
  174. /* AXI Bridge Registers */
  175. #define MVPP22_AXI_BM_WR_ATTR_REG 0x4100
  176. #define MVPP22_AXI_BM_RD_ATTR_REG 0x4104
  177. #define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG 0x4110
  178. #define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG 0x4114
  179. #define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG 0x4118
  180. #define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG 0x411c
  181. #define MVPP22_AXI_RX_DATA_WR_ATTR_REG 0x4120
  182. #define MVPP22_AXI_TX_DATA_RD_ATTR_REG 0x4130
  183. #define MVPP22_AXI_RD_NORMAL_CODE_REG 0x4150
  184. #define MVPP22_AXI_RD_SNOOP_CODE_REG 0x4154
  185. #define MVPP22_AXI_WR_NORMAL_CODE_REG 0x4160
  186. #define MVPP22_AXI_WR_SNOOP_CODE_REG 0x4164
  187. /* Values for AXI Bridge registers */
  188. #define MVPP22_AXI_ATTR_CACHE_OFFS 0
  189. #define MVPP22_AXI_ATTR_DOMAIN_OFFS 12
  190. #define MVPP22_AXI_CODE_CACHE_OFFS 0
  191. #define MVPP22_AXI_CODE_DOMAIN_OFFS 4
  192. #define MVPP22_AXI_CODE_CACHE_NON_CACHE 0x3
  193. #define MVPP22_AXI_CODE_CACHE_WR_CACHE 0x7
  194. #define MVPP22_AXI_CODE_CACHE_RD_CACHE 0xb
  195. #define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM 2
  196. #define MVPP22_AXI_CODE_DOMAIN_SYSTEM 3
  197. /* Interrupt Cause and Mask registers */
  198. #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
  199. #define MVPP21_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
  200. #define MVPP22_ISR_RXQ_GROUP_INDEX_REG 0x5400
  201. #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
  202. #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
  203. #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
  204. #define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
  205. #define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK 0x380
  206. #define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG 0x5404
  207. #define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK 0x1f
  208. #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK 0xf00
  209. #define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET 8
  210. #define MVPP2_ISR_ENABLE_REG(port) (0x5420 + 4 * (port))
  211. #define MVPP2_ISR_ENABLE_INTERRUPT(mask) ((mask) & 0xffff)
  212. #define MVPP2_ISR_DISABLE_INTERRUPT(mask) (((mask) << 16) & 0xffff0000)
  213. #define MVPP2_ISR_RX_TX_CAUSE_REG(port) (0x5480 + 4 * (port))
  214. #define MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
  215. #define MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
  216. #define MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK BIT(24)
  217. #define MVPP2_CAUSE_FCS_ERR_MASK BIT(25)
  218. #define MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK BIT(26)
  219. #define MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK BIT(29)
  220. #define MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK BIT(30)
  221. #define MVPP2_CAUSE_MISC_SUM_MASK BIT(31)
  222. #define MVPP2_ISR_RX_TX_MASK_REG(port) (0x54a0 + 4 * (port))
  223. #define MVPP2_ISR_PON_RX_TX_MASK_REG 0x54bc
  224. #define MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK 0xffff
  225. #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
  226. #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
  227. #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
  228. /* Buffer Manager registers */
  229. #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
  230. #define MVPP2_BM_POOL_BASE_ADDR_MASK 0xfffff80
  231. #define MVPP2_BM_POOL_SIZE_REG(pool) (0x6040 + ((pool) * 4))
  232. #define MVPP2_BM_POOL_SIZE_MASK 0xfff0
  233. #define MVPP2_BM_POOL_READ_PTR_REG(pool) (0x6080 + ((pool) * 4))
  234. #define MVPP2_BM_POOL_GET_READ_PTR_MASK 0xfff0
  235. #define MVPP2_BM_POOL_PTRS_NUM_REG(pool) (0x60c0 + ((pool) * 4))
  236. #define MVPP2_BM_POOL_PTRS_NUM_MASK 0xfff0
  237. #define MVPP2_BM_BPPI_READ_PTR_REG(pool) (0x6100 + ((pool) * 4))
  238. #define MVPP2_BM_BPPI_PTRS_NUM_REG(pool) (0x6140 + ((pool) * 4))
  239. #define MVPP2_BM_BPPI_PTR_NUM_MASK 0x7ff
  240. #define MVPP2_BM_BPPI_PREFETCH_FULL_MASK BIT(16)
  241. #define MVPP2_BM_POOL_CTRL_REG(pool) (0x6200 + ((pool) * 4))
  242. #define MVPP2_BM_START_MASK BIT(0)
  243. #define MVPP2_BM_STOP_MASK BIT(1)
  244. #define MVPP2_BM_STATE_MASK BIT(4)
  245. #define MVPP2_BM_LOW_THRESH_OFFS 8
  246. #define MVPP2_BM_LOW_THRESH_MASK 0x7f00
  247. #define MVPP2_BM_LOW_THRESH_VALUE(val) ((val) << \
  248. MVPP2_BM_LOW_THRESH_OFFS)
  249. #define MVPP2_BM_HIGH_THRESH_OFFS 16
  250. #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
  251. #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
  252. MVPP2_BM_HIGH_THRESH_OFFS)
  253. #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
  254. #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
  255. #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
  256. #define MVPP2_BM_BPPE_EMPTY_MASK BIT(2)
  257. #define MVPP2_BM_BPPE_FULL_MASK BIT(3)
  258. #define MVPP2_BM_AVAILABLE_BP_LOW_MASK BIT(4)
  259. #define MVPP2_BM_INTR_MASK_REG(pool) (0x6280 + ((pool) * 4))
  260. #define MVPP2_BM_PHY_ALLOC_REG(pool) (0x6400 + ((pool) * 4))
  261. #define MVPP2_BM_PHY_ALLOC_GRNTD_MASK BIT(0)
  262. #define MVPP2_BM_VIRT_ALLOC_REG 0x6440
  263. #define MVPP2_BM_ADDR_HIGH_ALLOC 0x6444
  264. #define MVPP2_BM_ADDR_HIGH_PHYS_MASK 0xff
  265. #define MVPP2_BM_ADDR_HIGH_VIRT_MASK 0xff00
  266. #define MVPP2_BM_ADDR_HIGH_VIRT_SHIFT 8
  267. #define MVPP2_BM_PHY_RLS_REG(pool) (0x6480 + ((pool) * 4))
  268. #define MVPP2_BM_PHY_RLS_MC_BUFF_MASK BIT(0)
  269. #define MVPP2_BM_PHY_RLS_PRIO_EN_MASK BIT(1)
  270. #define MVPP2_BM_PHY_RLS_GRNTD_MASK BIT(2)
  271. #define MVPP2_BM_VIRT_RLS_REG 0x64c0
  272. #define MVPP21_BM_MC_RLS_REG 0x64c4
  273. #define MVPP2_BM_MC_ID_MASK 0xfff
  274. #define MVPP2_BM_FORCE_RELEASE_MASK BIT(12)
  275. #define MVPP22_BM_ADDR_HIGH_RLS_REG 0x64c4
  276. #define MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK 0xff
  277. #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK 0xff00
  278. #define MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT 8
  279. #define MVPP22_BM_MC_RLS_REG 0x64d4
  280. #define MVPP22_BM_POOL_BASE_HIGH_REG 0x6310
  281. #define MVPP22_BM_POOL_BASE_HIGH_MASK 0xff
  282. /* TX Scheduler registers */
  283. #define MVPP2_TXP_SCHED_PORT_INDEX_REG 0x8000
  284. #define MVPP2_TXP_SCHED_Q_CMD_REG 0x8004
  285. #define MVPP2_TXP_SCHED_ENQ_MASK 0xff
  286. #define MVPP2_TXP_SCHED_DISQ_OFFSET 8
  287. #define MVPP2_TXP_SCHED_CMD_1_REG 0x8010
  288. #define MVPP2_TXP_SCHED_PERIOD_REG 0x8018
  289. #define MVPP2_TXP_SCHED_MTU_REG 0x801c
  290. #define MVPP2_TXP_MTU_MAX 0x7FFFF
  291. #define MVPP2_TXP_SCHED_REFILL_REG 0x8020
  292. #define MVPP2_TXP_REFILL_TOKENS_ALL_MASK 0x7ffff
  293. #define MVPP2_TXP_REFILL_PERIOD_ALL_MASK 0x3ff00000
  294. #define MVPP2_TXP_REFILL_PERIOD_MASK(v) ((v) << 20)
  295. #define MVPP2_TXP_SCHED_TOKEN_SIZE_REG 0x8024
  296. #define MVPP2_TXP_TOKEN_SIZE_MAX 0xffffffff
  297. #define MVPP2_TXQ_SCHED_REFILL_REG(q) (0x8040 + ((q) << 2))
  298. #define MVPP2_TXQ_REFILL_TOKENS_ALL_MASK 0x7ffff
  299. #define MVPP2_TXQ_REFILL_PERIOD_ALL_MASK 0x3ff00000
  300. #define MVPP2_TXQ_REFILL_PERIOD_MASK(v) ((v) << 20)
  301. #define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q) (0x8060 + ((q) << 2))
  302. #define MVPP2_TXQ_TOKEN_SIZE_MAX 0x7fffffff
  303. #define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q) (0x8080 + ((q) << 2))
  304. #define MVPP2_TXQ_TOKEN_CNTR_MAX 0xffffffff
  305. /* TX general registers */
  306. #define MVPP2_TX_SNOOP_REG 0x8800
  307. #define MVPP2_TX_PORT_FLUSH_REG 0x8810
  308. #define MVPP2_TX_PORT_FLUSH_MASK(port) (1 << (port))
  309. /* LMS registers */
  310. #define MVPP2_SRC_ADDR_MIDDLE 0x24
  311. #define MVPP2_SRC_ADDR_HIGH 0x28
  312. #define MVPP2_PHY_AN_CFG0_REG 0x34
  313. #define MVPP2_PHY_AN_STOP_SMI0_MASK BIT(7)
  314. #define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG 0x305c
  315. #define MVPP2_EXT_GLOBAL_CTRL_DEFAULT 0x27
  316. /* Per-port registers */
  317. #define MVPP2_GMAC_CTRL_0_REG 0x0
  318. #define MVPP2_GMAC_PORT_EN_MASK BIT(0)
  319. #define MVPP2_GMAC_PORT_TYPE_MASK BIT(1)
  320. #define MVPP2_GMAC_MAX_RX_SIZE_OFFS 2
  321. #define MVPP2_GMAC_MAX_RX_SIZE_MASK 0x7ffc
  322. #define MVPP2_GMAC_MIB_CNTR_EN_MASK BIT(15)
  323. #define MVPP2_GMAC_CTRL_1_REG 0x4
  324. #define MVPP2_GMAC_PERIODIC_XON_EN_MASK BIT(1)
  325. #define MVPP2_GMAC_GMII_LB_EN_MASK BIT(5)
  326. #define MVPP2_GMAC_PCS_LB_EN_BIT 6
  327. #define MVPP2_GMAC_PCS_LB_EN_MASK BIT(6)
  328. #define MVPP2_GMAC_SA_LOW_OFFS 7
  329. #define MVPP2_GMAC_CTRL_2_REG 0x8
  330. #define MVPP2_GMAC_INBAND_AN_MASK BIT(0)
  331. #define MVPP2_GMAC_SGMII_MODE_MASK BIT(0)
  332. #define MVPP2_GMAC_PCS_ENABLE_MASK BIT(3)
  333. #define MVPP2_GMAC_PORT_RGMII_MASK BIT(4)
  334. #define MVPP2_GMAC_PORT_DIS_PADING_MASK BIT(5)
  335. #define MVPP2_GMAC_PORT_RESET_MASK BIT(6)
  336. #define MVPP2_GMAC_CLK_125_BYPS_EN_MASK BIT(9)
  337. #define MVPP2_GMAC_AUTONEG_CONFIG 0xc
  338. #define MVPP2_GMAC_FORCE_LINK_DOWN BIT(0)
  339. #define MVPP2_GMAC_FORCE_LINK_PASS BIT(1)
  340. #define MVPP2_GMAC_EN_PCS_AN BIT(2)
  341. #define MVPP2_GMAC_AN_BYPASS_EN BIT(3)
  342. #define MVPP2_GMAC_CONFIG_MII_SPEED BIT(5)
  343. #define MVPP2_GMAC_CONFIG_GMII_SPEED BIT(6)
  344. #define MVPP2_GMAC_AN_SPEED_EN BIT(7)
  345. #define MVPP2_GMAC_FC_ADV_EN BIT(9)
  346. #define MVPP2_GMAC_EN_FC_AN BIT(11)
  347. #define MVPP2_GMAC_CONFIG_FULL_DUPLEX BIT(12)
  348. #define MVPP2_GMAC_AN_DUPLEX_EN BIT(13)
  349. #define MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG BIT(15)
  350. #define MVPP2_GMAC_PORT_FIFO_CFG_1_REG 0x1c
  351. #define MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS 6
  352. #define MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK 0x1fc0
  353. #define MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v) (((v) << 6) & \
  354. MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
  355. #define MVPP2_GMAC_CTRL_4_REG 0x90
  356. #define MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK BIT(0)
  357. #define MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK BIT(5)
  358. #define MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK BIT(6)
  359. #define MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK BIT(7)
  360. /*
  361. * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
  362. * relative to port->base.
  363. */
  364. /* Port Mac Control0 */
  365. #define MVPP22_XLG_CTRL0_REG 0x100
  366. #define MVPP22_XLG_PORT_EN BIT(0)
  367. #define MVPP22_XLG_MAC_RESETN BIT(1)
  368. #define MVPP22_XLG_RX_FC_EN BIT(7)
  369. #define MVPP22_XLG_MIBCNT_DIS BIT(13)
  370. /* Port Mac Control1 */
  371. #define MVPP22_XLG_CTRL1_REG 0x104
  372. #define MVPP22_XLG_MAX_RX_SIZE_OFFS 0
  373. #define MVPP22_XLG_MAX_RX_SIZE_MASK 0x1fff
  374. /* Port Interrupt Mask */
  375. #define MVPP22_XLG_INTERRUPT_MASK_REG 0x118
  376. #define MVPP22_XLG_INTERRUPT_LINK_CHANGE BIT(1)
  377. /* Port Mac Control3 */
  378. #define MVPP22_XLG_CTRL3_REG 0x11c
  379. #define MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
  380. #define MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
  381. #define MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC (1 << 13)
  382. /* Port Mac Control4 */
  383. #define MVPP22_XLG_CTRL4_REG 0x184
  384. #define MVPP22_XLG_FORWARD_802_3X_FC_EN BIT(5)
  385. #define MVPP22_XLG_FORWARD_PFC_EN BIT(6)
  386. #define MVPP22_XLG_MODE_DMA_1G BIT(12)
  387. #define MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK BIT(14)
  388. /* XPCS registers */
  389. /* Global Configuration 0 */
  390. #define MVPP22_XPCS_GLOBAL_CFG_0_REG 0x0
  391. #define MVPP22_XPCS_PCSRESET BIT(0)
  392. #define MVPP22_XPCS_PCSMODE_OFFS 3
  393. #define MVPP22_XPCS_PCSMODE_MASK (0x3 << \
  394. MVPP22_XPCS_PCSMODE_OFFS)
  395. #define MVPP22_XPCS_LANEACTIVE_OFFS 5
  396. #define MVPP22_XPCS_LANEACTIVE_MASK (0x3 << \
  397. MVPP22_XPCS_LANEACTIVE_OFFS)
  398. /* MPCS registers */
  399. #define PCS40G_COMMON_CONTROL 0x14
  400. #define FORWARD_ERROR_CORRECTION_MASK BIT(10)
  401. #define PCS_CLOCK_RESET 0x14c
  402. #define TX_SD_CLK_RESET_MASK BIT(0)
  403. #define RX_SD_CLK_RESET_MASK BIT(1)
  404. #define MAC_CLK_RESET_MASK BIT(2)
  405. #define CLK_DIVISION_RATIO_OFFS 4
  406. #define CLK_DIVISION_RATIO_MASK (0x7 << CLK_DIVISION_RATIO_OFFS)
  407. #define CLK_DIV_PHASE_SET_MASK BIT(11)
  408. /* System Soft Reset 1 */
  409. #define GOP_SOFT_RESET_1_REG 0x108
  410. #define NETC_GOP_SOFT_RESET_OFFS 6
  411. #define NETC_GOP_SOFT_RESET_MASK (0x1 << \
  412. NETC_GOP_SOFT_RESET_OFFS)
  413. /* Ports Control 0 */
  414. #define NETCOMP_PORTS_CONTROL_0_REG 0x110
  415. #define NETC_BUS_WIDTH_SELECT_OFFS 1
  416. #define NETC_BUS_WIDTH_SELECT_MASK (0x1 << \
  417. NETC_BUS_WIDTH_SELECT_OFFS)
  418. #define NETC_GIG_RX_DATA_SAMPLE_OFFS 29
  419. #define NETC_GIG_RX_DATA_SAMPLE_MASK (0x1 << \
  420. NETC_GIG_RX_DATA_SAMPLE_OFFS)
  421. #define NETC_CLK_DIV_PHASE_OFFS 31
  422. #define NETC_CLK_DIV_PHASE_MASK (0x1 << NETC_CLK_DIV_PHASE_OFFS)
  423. /* Ports Control 1 */
  424. #define NETCOMP_PORTS_CONTROL_1_REG 0x114
  425. #define NETC_PORTS_ACTIVE_OFFSET(p) (0 + p)
  426. #define NETC_PORTS_ACTIVE_MASK(p) (0x1 << \
  427. NETC_PORTS_ACTIVE_OFFSET(p))
  428. #define NETC_PORT_GIG_RF_RESET_OFFS(p) (28 + p)
  429. #define NETC_PORT_GIG_RF_RESET_MASK(p) (0x1 << \
  430. NETC_PORT_GIG_RF_RESET_OFFS(p))
  431. #define NETCOMP_CONTROL_0_REG 0x120
  432. #define NETC_GBE_PORT0_SGMII_MODE_OFFS 0
  433. #define NETC_GBE_PORT0_SGMII_MODE_MASK (0x1 << \
  434. NETC_GBE_PORT0_SGMII_MODE_OFFS)
  435. #define NETC_GBE_PORT1_SGMII_MODE_OFFS 1
  436. #define NETC_GBE_PORT1_SGMII_MODE_MASK (0x1 << \
  437. NETC_GBE_PORT1_SGMII_MODE_OFFS)
  438. #define NETC_GBE_PORT1_MII_MODE_OFFS 2
  439. #define NETC_GBE_PORT1_MII_MODE_MASK (0x1 << \
  440. NETC_GBE_PORT1_MII_MODE_OFFS)
  441. #define MVPP22_SMI_MISC_CFG_REG (MVPP22_SMI + 0x04)
  442. #define MVPP22_SMI_POLLING_EN BIT(10)
  443. #define MVPP22_SMI_PHY_ADDR_REG(port) (MVPP22_SMI + 0x04 + \
  444. (0x4 * (port)))
  445. #define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
  446. /* Descriptor ring Macros */
  447. #define MVPP2_QUEUE_NEXT_DESC(q, index) \
  448. (((index) < (q)->last_desc) ? ((index) + 1) : 0)
  449. /* SMI: 0xc0054 -> offset 0x54 to lms_base */
  450. #define MVPP21_SMI 0x0054
  451. /* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
  452. #define MVPP22_SMI 0x1200
  453. #define MVPP2_PHY_REG_MASK 0x1f
  454. /* SMI register fields */
  455. #define MVPP2_SMI_DATA_OFFS 0 /* Data */
  456. #define MVPP2_SMI_DATA_MASK (0xffff << MVPP2_SMI_DATA_OFFS)
  457. #define MVPP2_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
  458. #define MVPP2_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
  459. #define MVPP2_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
  460. #define MVPP2_SMI_OPCODE_READ (1 << MVPP2_SMI_OPCODE_OFFS)
  461. #define MVPP2_SMI_READ_VALID (1 << 27) /* Read Valid */
  462. #define MVPP2_SMI_BUSY (1 << 28) /* Busy */
  463. #define MVPP2_PHY_ADDR_MASK 0x1f
  464. #define MVPP2_PHY_REG_MASK 0x1f
  465. /* Additional PPv2.2 offsets */
  466. #define MVPP22_MPCS 0x007000
  467. #define MVPP22_XPCS 0x007400
  468. #define MVPP22_PORT_BASE 0x007e00
  469. #define MVPP22_PORT_OFFSET 0x001000
  470. #define MVPP22_RFU1 0x318000
  471. /* Maximum number of ports */
  472. #define MVPP22_GOP_MAC_NUM 4
  473. /* Sets the field located at the specified in data */
  474. #define MVPP2_RGMII_TX_FIFO_MIN_TH 0x41
  475. #define MVPP2_SGMII_TX_FIFO_MIN_TH 0x5
  476. #define MVPP2_SGMII2_5_TX_FIFO_MIN_TH 0xb
  477. /* Net Complex */
  478. enum mv_netc_topology {
  479. MV_NETC_GE_MAC2_SGMII = BIT(0),
  480. MV_NETC_GE_MAC3_SGMII = BIT(1),
  481. MV_NETC_GE_MAC3_RGMII = BIT(2),
  482. };
  483. enum mv_netc_phase {
  484. MV_NETC_FIRST_PHASE,
  485. MV_NETC_SECOND_PHASE,
  486. };
  487. enum mv_netc_sgmii_xmi_mode {
  488. MV_NETC_GBE_SGMII,
  489. MV_NETC_GBE_XMII,
  490. };
  491. enum mv_netc_mii_mode {
  492. MV_NETC_GBE_RGMII,
  493. MV_NETC_GBE_MII,
  494. };
  495. enum mv_netc_lanes {
  496. MV_NETC_LANE_23,
  497. MV_NETC_LANE_45,
  498. };
  499. /* Various constants */
  500. /* Coalescing */
  501. #define MVPP2_TXDONE_COAL_PKTS_THRESH 15
  502. #define MVPP2_TXDONE_HRTIMER_PERIOD_NS 1000000UL
  503. #define MVPP2_RX_COAL_PKTS 32
  504. #define MVPP2_RX_COAL_USEC 100
  505. /* The two bytes Marvell header. Either contains a special value used
  506. * by Marvell switches when a specific hardware mode is enabled (not
  507. * supported by this driver) or is filled automatically by zeroes on
  508. * the RX side. Those two bytes being at the front of the Ethernet
  509. * header, they allow to have the IP header aligned on a 4 bytes
  510. * boundary automatically: the hardware skips those two bytes on its
  511. * own.
  512. */
  513. #define MVPP2_MH_SIZE 2
  514. #define MVPP2_ETH_TYPE_LEN 2
  515. #define MVPP2_PPPOE_HDR_SIZE 8
  516. #define MVPP2_VLAN_TAG_LEN 4
  517. /* Lbtd 802.3 type */
  518. #define MVPP2_IP_LBDT_TYPE 0xfffa
  519. #define MVPP2_CPU_D_CACHE_LINE_SIZE 32
  520. #define MVPP2_TX_CSUM_MAX_SIZE 9800
  521. /* Timeout constants */
  522. #define MVPP2_TX_DISABLE_TIMEOUT_MSEC 1000
  523. #define MVPP2_TX_PENDING_TIMEOUT_MSEC 1000
  524. #define MVPP2_TX_MTU_MAX 0x7ffff
  525. /* Maximum number of T-CONTs of PON port */
  526. #define MVPP2_MAX_TCONT 16
  527. /* Maximum number of supported ports */
  528. #define MVPP2_MAX_PORTS 4
  529. /* Maximum number of TXQs used by single port */
  530. #define MVPP2_MAX_TXQ 8
  531. /* Default number of TXQs in use */
  532. #define MVPP2_DEFAULT_TXQ 1
  533. /* Dfault number of RXQs in use */
  534. #define MVPP2_DEFAULT_RXQ 1
  535. #define CONFIG_MV_ETH_RXQ 8 /* increment by 8 */
  536. /* Max number of Rx descriptors */
  537. #define MVPP2_MAX_RXD 16
  538. /* Max number of Tx descriptors */
  539. #define MVPP2_MAX_TXD 16
  540. /* Amount of Tx descriptors that can be reserved at once by CPU */
  541. #define MVPP2_CPU_DESC_CHUNK 16
  542. /* Max number of Tx descriptors in each aggregated queue */
  543. #define MVPP2_AGGR_TXQ_SIZE 16
  544. /* Descriptor aligned size */
  545. #define MVPP2_DESC_ALIGNED_SIZE 32
  546. /* Descriptor alignment mask */
  547. #define MVPP2_TX_DESC_ALIGN (MVPP2_DESC_ALIGNED_SIZE - 1)
  548. /* RX FIFO constants */
  549. #define MVPP21_RX_FIFO_PORT_DATA_SIZE 0x2000
  550. #define MVPP21_RX_FIFO_PORT_ATTR_SIZE 0x80
  551. #define MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE 0x8000
  552. #define MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE 0x2000
  553. #define MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE 0x1000
  554. #define MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE 0x200
  555. #define MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE 0x80
  556. #define MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE 0x40
  557. #define MVPP2_RX_FIFO_PORT_MIN_PKT 0x80
  558. /* TX general registers */
  559. #define MVPP22_TX_FIFO_SIZE_REG(eth_tx_port) (0x8860 + ((eth_tx_port) << 2))
  560. #define MVPP22_TX_FIFO_SIZE_MASK 0xf
  561. /* TX FIFO constants */
  562. #define MVPP2_TX_FIFO_DATA_SIZE_10KB 0xa
  563. #define MVPP2_TX_FIFO_DATA_SIZE_3KB 0x3
  564. /* RX buffer constants */
  565. #define MVPP2_SKB_SHINFO_SIZE \
  566. 0
  567. #define MVPP2_RX_PKT_SIZE(mtu) \
  568. ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
  569. ETH_HLEN + ETH_FCS_LEN, MVPP2_CPU_D_CACHE_LINE_SIZE)
  570. #define MVPP2_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
  571. #define MVPP2_RX_TOTAL_SIZE(buf_size) ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
  572. #define MVPP2_RX_MAX_PKT_SIZE(total_size) \
  573. ((total_size) - NET_SKB_PAD - MVPP2_SKB_SHINFO_SIZE)
  574. #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8)
  575. /* IPv6 max L3 address size */
  576. #define MVPP2_MAX_L3_ADDR_SIZE 16
  577. /* Port flags */
  578. #define MVPP2_F_LOOPBACK BIT(0)
  579. /* Marvell tag types */
  580. enum mvpp2_tag_type {
  581. MVPP2_TAG_TYPE_NONE = 0,
  582. MVPP2_TAG_TYPE_MH = 1,
  583. MVPP2_TAG_TYPE_DSA = 2,
  584. MVPP2_TAG_TYPE_EDSA = 3,
  585. MVPP2_TAG_TYPE_VLAN = 4,
  586. MVPP2_TAG_TYPE_LAST = 5
  587. };
  588. /* Parser constants */
  589. #define MVPP2_PRS_TCAM_SRAM_SIZE 256
  590. #define MVPP2_PRS_TCAM_WORDS 6
  591. #define MVPP2_PRS_SRAM_WORDS 4
  592. #define MVPP2_PRS_FLOW_ID_SIZE 64
  593. #define MVPP2_PRS_FLOW_ID_MASK 0x3f
  594. #define MVPP2_PRS_TCAM_ENTRY_INVALID 1
  595. #define MVPP2_PRS_TCAM_DSA_TAGGED_BIT BIT(5)
  596. #define MVPP2_PRS_IPV4_HEAD 0x40
  597. #define MVPP2_PRS_IPV4_HEAD_MASK 0xf0
  598. #define MVPP2_PRS_IPV4_MC 0xe0
  599. #define MVPP2_PRS_IPV4_MC_MASK 0xf0
  600. #define MVPP2_PRS_IPV4_BC_MASK 0xff
  601. #define MVPP2_PRS_IPV4_IHL 0x5
  602. #define MVPP2_PRS_IPV4_IHL_MASK 0xf
  603. #define MVPP2_PRS_IPV6_MC 0xff
  604. #define MVPP2_PRS_IPV6_MC_MASK 0xff
  605. #define MVPP2_PRS_IPV6_HOP_MASK 0xff
  606. #define MVPP2_PRS_TCAM_PROTO_MASK 0xff
  607. #define MVPP2_PRS_TCAM_PROTO_MASK_L 0x3f
  608. #define MVPP2_PRS_DBL_VLANS_MAX 100
  609. /* Tcam structure:
  610. * - lookup ID - 4 bits
  611. * - port ID - 1 byte
  612. * - additional information - 1 byte
  613. * - header data - 8 bytes
  614. * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(5)->(0).
  615. */
  616. #define MVPP2_PRS_AI_BITS 8
  617. #define MVPP2_PRS_PORT_MASK 0xff
  618. #define MVPP2_PRS_LU_MASK 0xf
  619. #define MVPP2_PRS_TCAM_DATA_BYTE(offs) \
  620. (((offs) - ((offs) % 2)) * 2 + ((offs) % 2))
  621. #define MVPP2_PRS_TCAM_DATA_BYTE_EN(offs) \
  622. (((offs) * 2) - ((offs) % 2) + 2)
  623. #define MVPP2_PRS_TCAM_AI_BYTE 16
  624. #define MVPP2_PRS_TCAM_PORT_BYTE 17
  625. #define MVPP2_PRS_TCAM_LU_BYTE 20
  626. #define MVPP2_PRS_TCAM_EN_OFFS(offs) ((offs) + 2)
  627. #define MVPP2_PRS_TCAM_INV_WORD 5
  628. /* Tcam entries ID */
  629. #define MVPP2_PE_DROP_ALL 0
  630. #define MVPP2_PE_FIRST_FREE_TID 1
  631. #define MVPP2_PE_LAST_FREE_TID (MVPP2_PRS_TCAM_SRAM_SIZE - 31)
  632. #define MVPP2_PE_IP6_EXT_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 30)
  633. #define MVPP2_PE_MAC_MC_IP6 (MVPP2_PRS_TCAM_SRAM_SIZE - 29)
  634. #define MVPP2_PE_IP6_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 28)
  635. #define MVPP2_PE_IP4_ADDR_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 27)
  636. #define MVPP2_PE_LAST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 26)
  637. #define MVPP2_PE_FIRST_DEFAULT_FLOW (MVPP2_PRS_TCAM_SRAM_SIZE - 19)
  638. #define MVPP2_PE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 18)
  639. #define MVPP2_PE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 17)
  640. #define MVPP2_PE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 16)
  641. #define MVPP2_PE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 15)
  642. #define MVPP2_PE_ETYPE_EDSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 14)
  643. #define MVPP2_PE_ETYPE_EDSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 13)
  644. #define MVPP2_PE_ETYPE_DSA_TAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 12)
  645. #define MVPP2_PE_ETYPE_DSA_UNTAGGED (MVPP2_PRS_TCAM_SRAM_SIZE - 11)
  646. #define MVPP2_PE_MH_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 10)
  647. #define MVPP2_PE_DSA_DEFAULT (MVPP2_PRS_TCAM_SRAM_SIZE - 9)
  648. #define MVPP2_PE_IP6_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 8)
  649. #define MVPP2_PE_IP4_PROTO_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 7)
  650. #define MVPP2_PE_ETH_TYPE_UN (MVPP2_PRS_TCAM_SRAM_SIZE - 6)
  651. #define MVPP2_PE_VLAN_DBL (MVPP2_PRS_TCAM_SRAM_SIZE - 5)
  652. #define MVPP2_PE_VLAN_NONE (MVPP2_PRS_TCAM_SRAM_SIZE - 4)
  653. #define MVPP2_PE_MAC_MC_ALL (MVPP2_PRS_TCAM_SRAM_SIZE - 3)
  654. #define MVPP2_PE_MAC_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 2)
  655. #define MVPP2_PE_MAC_NON_PROMISCUOUS (MVPP2_PRS_TCAM_SRAM_SIZE - 1)
  656. /* Sram structure
  657. * The fields are represented by MVPP2_PRS_TCAM_DATA_REG(3)->(0).
  658. */
  659. #define MVPP2_PRS_SRAM_RI_OFFS 0
  660. #define MVPP2_PRS_SRAM_RI_WORD 0
  661. #define MVPP2_PRS_SRAM_RI_CTRL_OFFS 32
  662. #define MVPP2_PRS_SRAM_RI_CTRL_WORD 1
  663. #define MVPP2_PRS_SRAM_RI_CTRL_BITS 32
  664. #define MVPP2_PRS_SRAM_SHIFT_OFFS 64
  665. #define MVPP2_PRS_SRAM_SHIFT_SIGN_BIT 72
  666. #define MVPP2_PRS_SRAM_UDF_OFFS 73
  667. #define MVPP2_PRS_SRAM_UDF_BITS 8
  668. #define MVPP2_PRS_SRAM_UDF_MASK 0xff
  669. #define MVPP2_PRS_SRAM_UDF_SIGN_BIT 81
  670. #define MVPP2_PRS_SRAM_UDF_TYPE_OFFS 82
  671. #define MVPP2_PRS_SRAM_UDF_TYPE_MASK 0x7
  672. #define MVPP2_PRS_SRAM_UDF_TYPE_L3 1
  673. #define MVPP2_PRS_SRAM_UDF_TYPE_L4 4
  674. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS 85
  675. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK 0x3
  676. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD 1
  677. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP4_ADD 2
  678. #define MVPP2_PRS_SRAM_OP_SEL_SHIFT_IP6_ADD 3
  679. #define MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS 87
  680. #define MVPP2_PRS_SRAM_OP_SEL_UDF_BITS 2
  681. #define MVPP2_PRS_SRAM_OP_SEL_UDF_MASK 0x3
  682. #define MVPP2_PRS_SRAM_OP_SEL_UDF_ADD 0
  683. #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP4_ADD 2
  684. #define MVPP2_PRS_SRAM_OP_SEL_UDF_IP6_ADD 3
  685. #define MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS 89
  686. #define MVPP2_PRS_SRAM_AI_OFFS 90
  687. #define MVPP2_PRS_SRAM_AI_CTRL_OFFS 98
  688. #define MVPP2_PRS_SRAM_AI_CTRL_BITS 8
  689. #define MVPP2_PRS_SRAM_AI_MASK 0xff
  690. #define MVPP2_PRS_SRAM_NEXT_LU_OFFS 106
  691. #define MVPP2_PRS_SRAM_NEXT_LU_MASK 0xf
  692. #define MVPP2_PRS_SRAM_LU_DONE_BIT 110
  693. #define MVPP2_PRS_SRAM_LU_GEN_BIT 111
  694. /* Sram result info bits assignment */
  695. #define MVPP2_PRS_RI_MAC_ME_MASK 0x1
  696. #define MVPP2_PRS_RI_DSA_MASK 0x2
  697. #define MVPP2_PRS_RI_VLAN_MASK (BIT(2) | BIT(3))
  698. #define MVPP2_PRS_RI_VLAN_NONE 0x0
  699. #define MVPP2_PRS_RI_VLAN_SINGLE BIT(2)
  700. #define MVPP2_PRS_RI_VLAN_DOUBLE BIT(3)
  701. #define MVPP2_PRS_RI_VLAN_TRIPLE (BIT(2) | BIT(3))
  702. #define MVPP2_PRS_RI_CPU_CODE_MASK 0x70
  703. #define MVPP2_PRS_RI_CPU_CODE_RX_SPEC BIT(4)
  704. #define MVPP2_PRS_RI_L2_CAST_MASK (BIT(9) | BIT(10))
  705. #define MVPP2_PRS_RI_L2_UCAST 0x0
  706. #define MVPP2_PRS_RI_L2_MCAST BIT(9)
  707. #define MVPP2_PRS_RI_L2_BCAST BIT(10)
  708. #define MVPP2_PRS_RI_PPPOE_MASK 0x800
  709. #define MVPP2_PRS_RI_L3_PROTO_MASK (BIT(12) | BIT(13) | BIT(14))
  710. #define MVPP2_PRS_RI_L3_UN 0x0
  711. #define MVPP2_PRS_RI_L3_IP4 BIT(12)
  712. #define MVPP2_PRS_RI_L3_IP4_OPT BIT(13)
  713. #define MVPP2_PRS_RI_L3_IP4_OTHER (BIT(12) | BIT(13))
  714. #define MVPP2_PRS_RI_L3_IP6 BIT(14)
  715. #define MVPP2_PRS_RI_L3_IP6_EXT (BIT(12) | BIT(14))
  716. #define MVPP2_PRS_RI_L3_ARP (BIT(13) | BIT(14))
  717. #define MVPP2_PRS_RI_L3_ADDR_MASK (BIT(15) | BIT(16))
  718. #define MVPP2_PRS_RI_L3_UCAST 0x0
  719. #define MVPP2_PRS_RI_L3_MCAST BIT(15)
  720. #define MVPP2_PRS_RI_L3_BCAST (BIT(15) | BIT(16))
  721. #define MVPP2_PRS_RI_IP_FRAG_MASK 0x20000
  722. #define MVPP2_PRS_RI_UDF3_MASK 0x300000
  723. #define MVPP2_PRS_RI_UDF3_RX_SPECIAL BIT(21)
  724. #define MVPP2_PRS_RI_L4_PROTO_MASK 0x1c00000
  725. #define MVPP2_PRS_RI_L4_TCP BIT(22)
  726. #define MVPP2_PRS_RI_L4_UDP BIT(23)
  727. #define MVPP2_PRS_RI_L4_OTHER (BIT(22) | BIT(23))
  728. #define MVPP2_PRS_RI_UDF7_MASK 0x60000000
  729. #define MVPP2_PRS_RI_UDF7_IP6_LITE BIT(29)
  730. #define MVPP2_PRS_RI_DROP_MASK 0x80000000
  731. /* Sram additional info bits assignment */
  732. #define MVPP2_PRS_IPV4_DIP_AI_BIT BIT(0)
  733. #define MVPP2_PRS_IPV6_NO_EXT_AI_BIT BIT(0)
  734. #define MVPP2_PRS_IPV6_EXT_AI_BIT BIT(1)
  735. #define MVPP2_PRS_IPV6_EXT_AH_AI_BIT BIT(2)
  736. #define MVPP2_PRS_IPV6_EXT_AH_LEN_AI_BIT BIT(3)
  737. #define MVPP2_PRS_IPV6_EXT_AH_L4_AI_BIT BIT(4)
  738. #define MVPP2_PRS_SINGLE_VLAN_AI 0
  739. #define MVPP2_PRS_DBL_VLAN_AI_BIT BIT(7)
  740. /* DSA/EDSA type */
  741. #define MVPP2_PRS_TAGGED true
  742. #define MVPP2_PRS_UNTAGGED false
  743. #define MVPP2_PRS_EDSA true
  744. #define MVPP2_PRS_DSA false
  745. /* MAC entries, shadow udf */
  746. enum mvpp2_prs_udf {
  747. MVPP2_PRS_UDF_MAC_DEF,
  748. MVPP2_PRS_UDF_MAC_RANGE,
  749. MVPP2_PRS_UDF_L2_DEF,
  750. MVPP2_PRS_UDF_L2_DEF_COPY,
  751. MVPP2_PRS_UDF_L2_USER,
  752. };
  753. /* Lookup ID */
  754. enum mvpp2_prs_lookup {
  755. MVPP2_PRS_LU_MH,
  756. MVPP2_PRS_LU_MAC,
  757. MVPP2_PRS_LU_DSA,
  758. MVPP2_PRS_LU_VLAN,
  759. MVPP2_PRS_LU_L2,
  760. MVPP2_PRS_LU_PPPOE,
  761. MVPP2_PRS_LU_IP4,
  762. MVPP2_PRS_LU_IP6,
  763. MVPP2_PRS_LU_FLOWS,
  764. MVPP2_PRS_LU_LAST,
  765. };
  766. /* L3 cast enum */
  767. enum mvpp2_prs_l3_cast {
  768. MVPP2_PRS_L3_UNI_CAST,
  769. MVPP2_PRS_L3_MULTI_CAST,
  770. MVPP2_PRS_L3_BROAD_CAST
  771. };
  772. /* Classifier constants */
  773. #define MVPP2_CLS_FLOWS_TBL_SIZE 512
  774. #define MVPP2_CLS_FLOWS_TBL_DATA_WORDS 3
  775. #define MVPP2_CLS_LKP_TBL_SIZE 64
  776. /* BM constants */
  777. #define MVPP2_BM_POOLS_NUM 1
  778. #define MVPP2_BM_LONG_BUF_NUM 16
  779. #define MVPP2_BM_SHORT_BUF_NUM 16
  780. #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
  781. #define MVPP2_BM_POOL_PTR_ALIGN 128
  782. #define MVPP2_BM_SWF_LONG_POOL(port) 0
  783. /* BM cookie (32 bits) definition */
  784. #define MVPP2_BM_COOKIE_POOL_OFFS 8
  785. #define MVPP2_BM_COOKIE_CPU_OFFS 24
  786. /* BM short pool packet size
  787. * These value assure that for SWF the total number
  788. * of bytes allocated for each buffer will be 512
  789. */
  790. #define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(512)
  791. enum mvpp2_bm_type {
  792. MVPP2_BM_FREE,
  793. MVPP2_BM_SWF_LONG,
  794. MVPP2_BM_SWF_SHORT
  795. };
  796. /* Definitions */
  797. /* Shared Packet Processor resources */
  798. struct mvpp2 {
  799. /* Shared registers' base addresses */
  800. void __iomem *base;
  801. void __iomem *lms_base;
  802. void __iomem *iface_base;
  803. void __iomem *mpcs_base;
  804. void __iomem *xpcs_base;
  805. void __iomem *rfu1_base;
  806. u32 netc_config;
  807. /* List of pointers to port structures */
  808. struct mvpp2_port **port_list;
  809. /* Aggregated TXQs */
  810. struct mvpp2_tx_queue *aggr_txqs;
  811. /* BM pools */
  812. struct mvpp2_bm_pool *bm_pools;
  813. /* PRS shadow table */
  814. struct mvpp2_prs_shadow *prs_shadow;
  815. /* PRS auxiliary table for double vlan entries control */
  816. bool *prs_double_vlans;
  817. /* Tclk value */
  818. u32 tclk;
  819. /* HW version */
  820. enum { MVPP21, MVPP22 } hw_version;
  821. /* Maximum number of RXQs per port */
  822. unsigned int max_port_rxqs;
  823. int probe_done;
  824. u8 num_ports;
  825. };
  826. struct mvpp2_pcpu_stats {
  827. u64 rx_packets;
  828. u64 rx_bytes;
  829. u64 tx_packets;
  830. u64 tx_bytes;
  831. };
  832. struct mvpp2_port {
  833. u8 id;
  834. /* Index of the port from the "group of ports" complex point
  835. * of view
  836. */
  837. int gop_id;
  838. int irq;
  839. struct mvpp2 *priv;
  840. /* Per-port registers' base address */
  841. void __iomem *base;
  842. void __iomem *mdio_base;
  843. struct mvpp2_rx_queue **rxqs;
  844. struct mvpp2_tx_queue **txqs;
  845. int pkt_size;
  846. u32 pending_cause_rx;
  847. /* Per-CPU port control */
  848. struct mvpp2_port_pcpu __percpu *pcpu;
  849. /* Flags */
  850. unsigned long flags;
  851. u16 tx_ring_size;
  852. u16 rx_ring_size;
  853. struct mvpp2_pcpu_stats __percpu *stats;
  854. struct phy_device *phy_dev;
  855. phy_interface_t phy_interface;
  856. int phy_node;
  857. int phyaddr;
  858. struct mii_dev *bus;
  859. #ifdef CONFIG_DM_GPIO
  860. struct gpio_desc phy_reset_gpio;
  861. struct gpio_desc phy_tx_disable_gpio;
  862. #endif
  863. int init;
  864. unsigned int link;
  865. unsigned int duplex;
  866. unsigned int speed;
  867. unsigned int phy_speed; /* SGMII 1Gbps vs 2.5Gbps */
  868. struct mvpp2_bm_pool *pool_long;
  869. struct mvpp2_bm_pool *pool_short;
  870. /* Index of first port's physical RXQ */
  871. u8 first_rxq;
  872. u8 dev_addr[ETH_ALEN];
  873. };
  874. /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
  875. * layout of the transmit and reception DMA descriptors, and their
  876. * layout is therefore defined by the hardware design
  877. */
  878. #define MVPP2_TXD_L3_OFF_SHIFT 0
  879. #define MVPP2_TXD_IP_HLEN_SHIFT 8
  880. #define MVPP2_TXD_L4_CSUM_FRAG BIT(13)
  881. #define MVPP2_TXD_L4_CSUM_NOT BIT(14)
  882. #define MVPP2_TXD_IP_CSUM_DISABLE BIT(15)
  883. #define MVPP2_TXD_PADDING_DISABLE BIT(23)
  884. #define MVPP2_TXD_L4_UDP BIT(24)
  885. #define MVPP2_TXD_L3_IP6 BIT(26)
  886. #define MVPP2_TXD_L_DESC BIT(28)
  887. #define MVPP2_TXD_F_DESC BIT(29)
  888. #define MVPP2_RXD_ERR_SUMMARY BIT(15)
  889. #define MVPP2_RXD_ERR_CODE_MASK (BIT(13) | BIT(14))
  890. #define MVPP2_RXD_ERR_CRC 0x0
  891. #define MVPP2_RXD_ERR_OVERRUN BIT(13)
  892. #define MVPP2_RXD_ERR_RESOURCE (BIT(13) | BIT(14))
  893. #define MVPP2_RXD_BM_POOL_ID_OFFS 16
  894. #define MVPP2_RXD_BM_POOL_ID_MASK (BIT(16) | BIT(17) | BIT(18))
  895. #define MVPP2_RXD_HWF_SYNC BIT(21)
  896. #define MVPP2_RXD_L4_CSUM_OK BIT(22)
  897. #define MVPP2_RXD_IP4_HEADER_ERR BIT(24)
  898. #define MVPP2_RXD_L4_TCP BIT(25)
  899. #define MVPP2_RXD_L4_UDP BIT(26)
  900. #define MVPP2_RXD_L3_IP4 BIT(28)
  901. #define MVPP2_RXD_L3_IP6 BIT(30)
  902. #define MVPP2_RXD_BUF_HDR BIT(31)
  903. /* HW TX descriptor for PPv2.1 */
  904. struct mvpp21_tx_desc {
  905. u32 command; /* Options used by HW for packet transmitting.*/
  906. u8 packet_offset; /* the offset from the buffer beginning */
  907. u8 phys_txq; /* destination queue ID */
  908. u16 data_size; /* data size of transmitted packet in bytes */
  909. u32 buf_dma_addr; /* physical addr of transmitted buffer */
  910. u32 buf_cookie; /* cookie for access to TX buffer in tx path */
  911. u32 reserved1[3]; /* hw_cmd (for future use, BM, PON, PNC) */
  912. u32 reserved2; /* reserved (for future use) */
  913. };
  914. /* HW RX descriptor for PPv2.1 */
  915. struct mvpp21_rx_desc {
  916. u32 status; /* info about received packet */
  917. u16 reserved1; /* parser_info (for future use, PnC) */
  918. u16 data_size; /* size of received packet in bytes */
  919. u32 buf_dma_addr; /* physical address of the buffer */
  920. u32 buf_cookie; /* cookie for access to RX buffer in rx path */
  921. u16 reserved2; /* gem_port_id (for future use, PON) */
  922. u16 reserved3; /* csum_l4 (for future use, PnC) */
  923. u8 reserved4; /* bm_qset (for future use, BM) */
  924. u8 reserved5;
  925. u16 reserved6; /* classify_info (for future use, PnC) */
  926. u32 reserved7; /* flow_id (for future use, PnC) */
  927. u32 reserved8;
  928. };
  929. /* HW TX descriptor for PPv2.2 */
  930. struct mvpp22_tx_desc {
  931. u32 command;
  932. u8 packet_offset;
  933. u8 phys_txq;
  934. u16 data_size;
  935. u64 reserved1;
  936. u64 buf_dma_addr_ptp;
  937. u64 buf_cookie_misc;
  938. };
  939. /* HW RX descriptor for PPv2.2 */
  940. struct mvpp22_rx_desc {
  941. u32 status;
  942. u16 reserved1;
  943. u16 data_size;
  944. u32 reserved2;
  945. u32 reserved3;
  946. u64 buf_dma_addr_key_hash;
  947. u64 buf_cookie_misc;
  948. };
  949. /* Opaque type used by the driver to manipulate the HW TX and RX
  950. * descriptors
  951. */
  952. struct mvpp2_tx_desc {
  953. union {
  954. struct mvpp21_tx_desc pp21;
  955. struct mvpp22_tx_desc pp22;
  956. };
  957. };
  958. struct mvpp2_rx_desc {
  959. union {
  960. struct mvpp21_rx_desc pp21;
  961. struct mvpp22_rx_desc pp22;
  962. };
  963. };
  964. /* Per-CPU Tx queue control */
  965. struct mvpp2_txq_pcpu {
  966. int cpu;
  967. /* Number of Tx DMA descriptors in the descriptor ring */
  968. int size;
  969. /* Number of currently used Tx DMA descriptor in the
  970. * descriptor ring
  971. */
  972. int count;
  973. /* Number of Tx DMA descriptors reserved for each CPU */
  974. int reserved_num;
  975. /* Index of last TX DMA descriptor that was inserted */
  976. int txq_put_index;
  977. /* Index of the TX DMA descriptor to be cleaned up */
  978. int txq_get_index;
  979. };
  980. struct mvpp2_tx_queue {
  981. /* Physical number of this Tx queue */
  982. u8 id;
  983. /* Logical number of this Tx queue */
  984. u8 log_id;
  985. /* Number of Tx DMA descriptors in the descriptor ring */
  986. int size;
  987. /* Number of currently used Tx DMA descriptor in the descriptor ring */
  988. int count;
  989. /* Per-CPU control of physical Tx queues */
  990. struct mvpp2_txq_pcpu __percpu *pcpu;
  991. u32 done_pkts_coal;
  992. /* Virtual address of thex Tx DMA descriptors array */
  993. struct mvpp2_tx_desc *descs;
  994. /* DMA address of the Tx DMA descriptors array */
  995. dma_addr_t descs_dma;
  996. /* Index of the last Tx DMA descriptor */
  997. int last_desc;
  998. /* Index of the next Tx DMA descriptor to process */
  999. int next_desc_to_proc;
  1000. };
  1001. struct mvpp2_rx_queue {
  1002. /* RX queue number, in the range 0-31 for physical RXQs */
  1003. u8 id;
  1004. /* Num of rx descriptors in the rx descriptor ring */
  1005. int size;
  1006. u32 pkts_coal;
  1007. u32 time_coal;
  1008. /* Virtual address of the RX DMA descriptors array */
  1009. struct mvpp2_rx_desc *descs;
  1010. /* DMA address of the RX DMA descriptors array */
  1011. dma_addr_t descs_dma;
  1012. /* Index of the last RX DMA descriptor */
  1013. int last_desc;
  1014. /* Index of the next RX DMA descriptor to process */
  1015. int next_desc_to_proc;
  1016. /* ID of port to which physical RXQ is mapped */
  1017. int port;
  1018. /* Port's logic RXQ number to which physical RXQ is mapped */
  1019. int logic_rxq;
  1020. };
  1021. union mvpp2_prs_tcam_entry {
  1022. u32 word[MVPP2_PRS_TCAM_WORDS];
  1023. u8 byte[MVPP2_PRS_TCAM_WORDS * 4];
  1024. };
  1025. union mvpp2_prs_sram_entry {
  1026. u32 word[MVPP2_PRS_SRAM_WORDS];
  1027. u8 byte[MVPP2_PRS_SRAM_WORDS * 4];
  1028. };
  1029. struct mvpp2_prs_entry {
  1030. u32 index;
  1031. union mvpp2_prs_tcam_entry tcam;
  1032. union mvpp2_prs_sram_entry sram;
  1033. };
  1034. struct mvpp2_prs_shadow {
  1035. bool valid;
  1036. bool finish;
  1037. /* Lookup ID */
  1038. int lu;
  1039. /* User defined offset */
  1040. int udf;
  1041. /* Result info */
  1042. u32 ri;
  1043. u32 ri_mask;
  1044. };
  1045. struct mvpp2_cls_flow_entry {
  1046. u32 index;
  1047. u32 data[MVPP2_CLS_FLOWS_TBL_DATA_WORDS];
  1048. };
  1049. struct mvpp2_cls_lookup_entry {
  1050. u32 lkpid;
  1051. u32 way;
  1052. u32 data;
  1053. };
  1054. struct mvpp2_bm_pool {
  1055. /* Pool number in the range 0-7 */
  1056. int id;
  1057. enum mvpp2_bm_type type;
  1058. /* Buffer Pointers Pool External (BPPE) size */
  1059. int size;
  1060. /* Number of buffers for this pool */
  1061. int buf_num;
  1062. /* Pool buffer size */
  1063. int buf_size;
  1064. /* Packet size */
  1065. int pkt_size;
  1066. /* BPPE virtual base address */
  1067. unsigned long *virt_addr;
  1068. /* BPPE DMA base address */
  1069. dma_addr_t dma_addr;
  1070. /* Ports using BM pool */
  1071. u32 port_map;
  1072. };
  1073. /* Static declaractions */
  1074. /* Number of RXQs used by single port */
  1075. static int rxq_number = MVPP2_DEFAULT_RXQ;
  1076. /* Number of TXQs used by single port */
  1077. static int txq_number = MVPP2_DEFAULT_TXQ;
  1078. static int base_id;
  1079. #define MVPP2_DRIVER_NAME "mvpp2"
  1080. #define MVPP2_DRIVER_VERSION "1.0"
  1081. /*
  1082. * U-Boot internal data, mostly uncached buffers for descriptors and data
  1083. */
  1084. struct buffer_location {
  1085. struct mvpp2_tx_desc *aggr_tx_descs;
  1086. struct mvpp2_tx_desc *tx_descs;
  1087. struct mvpp2_rx_desc *rx_descs;
  1088. unsigned long *bm_pool[MVPP2_BM_POOLS_NUM];
  1089. unsigned long *rx_buffer[MVPP2_BM_LONG_BUF_NUM];
  1090. int first_rxq;
  1091. };
  1092. /*
  1093. * All 4 interfaces use the same global buffer, since only one interface
  1094. * can be enabled at once
  1095. */
  1096. static struct buffer_location buffer_loc;
  1097. /*
  1098. * Page table entries are set to 1MB, or multiples of 1MB
  1099. * (not < 1MB). driver uses less bd's so use 1MB bdspace.
  1100. */
  1101. #define BD_SPACE (1 << 20)
  1102. /* Utility/helper methods */
  1103. static void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
  1104. {
  1105. writel(data, priv->base + offset);
  1106. }
  1107. static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
  1108. {
  1109. return readl(priv->base + offset);
  1110. }
  1111. static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
  1112. struct mvpp2_tx_desc *tx_desc,
  1113. dma_addr_t dma_addr)
  1114. {
  1115. if (port->priv->hw_version == MVPP21) {
  1116. tx_desc->pp21.buf_dma_addr = dma_addr;
  1117. } else {
  1118. u64 val = (u64)dma_addr;
  1119. tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
  1120. tx_desc->pp22.buf_dma_addr_ptp |= val;
  1121. }
  1122. }
  1123. static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
  1124. struct mvpp2_tx_desc *tx_desc,
  1125. size_t size)
  1126. {
  1127. if (port->priv->hw_version == MVPP21)
  1128. tx_desc->pp21.data_size = size;
  1129. else
  1130. tx_desc->pp22.data_size = size;
  1131. }
  1132. static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
  1133. struct mvpp2_tx_desc *tx_desc,
  1134. unsigned int txq)
  1135. {
  1136. if (port->priv->hw_version == MVPP21)
  1137. tx_desc->pp21.phys_txq = txq;
  1138. else
  1139. tx_desc->pp22.phys_txq = txq;
  1140. }
  1141. static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
  1142. struct mvpp2_tx_desc *tx_desc,
  1143. unsigned int command)
  1144. {
  1145. if (port->priv->hw_version == MVPP21)
  1146. tx_desc->pp21.command = command;
  1147. else
  1148. tx_desc->pp22.command = command;
  1149. }
  1150. static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
  1151. struct mvpp2_tx_desc *tx_desc,
  1152. unsigned int offset)
  1153. {
  1154. if (port->priv->hw_version == MVPP21)
  1155. tx_desc->pp21.packet_offset = offset;
  1156. else
  1157. tx_desc->pp22.packet_offset = offset;
  1158. }
  1159. static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
  1160. struct mvpp2_rx_desc *rx_desc)
  1161. {
  1162. if (port->priv->hw_version == MVPP21)
  1163. return rx_desc->pp21.buf_dma_addr;
  1164. else
  1165. return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
  1166. }
  1167. static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
  1168. struct mvpp2_rx_desc *rx_desc)
  1169. {
  1170. if (port->priv->hw_version == MVPP21)
  1171. return rx_desc->pp21.buf_cookie;
  1172. else
  1173. return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
  1174. }
  1175. static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
  1176. struct mvpp2_rx_desc *rx_desc)
  1177. {
  1178. if (port->priv->hw_version == MVPP21)
  1179. return rx_desc->pp21.data_size;
  1180. else
  1181. return rx_desc->pp22.data_size;
  1182. }
  1183. static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
  1184. struct mvpp2_rx_desc *rx_desc)
  1185. {
  1186. if (port->priv->hw_version == MVPP21)
  1187. return rx_desc->pp21.status;
  1188. else
  1189. return rx_desc->pp22.status;
  1190. }
  1191. static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
  1192. {
  1193. txq_pcpu->txq_get_index++;
  1194. if (txq_pcpu->txq_get_index == txq_pcpu->size)
  1195. txq_pcpu->txq_get_index = 0;
  1196. }
  1197. /* Get number of physical egress port */
  1198. static inline int mvpp2_egress_port(struct mvpp2_port *port)
  1199. {
  1200. return MVPP2_MAX_TCONT + port->id;
  1201. }
  1202. /* Get number of physical TXQ */
  1203. static inline int mvpp2_txq_phys(int port, int txq)
  1204. {
  1205. return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
  1206. }
  1207. /* Parser configuration routines */
  1208. /* Update parser tcam and sram hw entries */
  1209. static int mvpp2_prs_hw_write(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
  1210. {
  1211. int i;
  1212. if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
  1213. return -EINVAL;
  1214. /* Clear entry invalidation bit */
  1215. pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] &= ~MVPP2_PRS_TCAM_INV_MASK;
  1216. /* Write tcam index - indirect access */
  1217. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
  1218. for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
  1219. mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), pe->tcam.word[i]);
  1220. /* Write sram index - indirect access */
  1221. mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
  1222. for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
  1223. mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), pe->sram.word[i]);
  1224. return 0;
  1225. }
  1226. /* Read tcam entry from hw */
  1227. static int mvpp2_prs_hw_read(struct mvpp2 *priv, struct mvpp2_prs_entry *pe)
  1228. {
  1229. int i;
  1230. if (pe->index > MVPP2_PRS_TCAM_SRAM_SIZE - 1)
  1231. return -EINVAL;
  1232. /* Write tcam index - indirect access */
  1233. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, pe->index);
  1234. pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] = mvpp2_read(priv,
  1235. MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD));
  1236. if (pe->tcam.word[MVPP2_PRS_TCAM_INV_WORD] & MVPP2_PRS_TCAM_INV_MASK)
  1237. return MVPP2_PRS_TCAM_ENTRY_INVALID;
  1238. for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
  1239. pe->tcam.word[i] = mvpp2_read(priv, MVPP2_PRS_TCAM_DATA_REG(i));
  1240. /* Write sram index - indirect access */
  1241. mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, pe->index);
  1242. for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
  1243. pe->sram.word[i] = mvpp2_read(priv, MVPP2_PRS_SRAM_DATA_REG(i));
  1244. return 0;
  1245. }
  1246. /* Invalidate tcam hw entry */
  1247. static void mvpp2_prs_hw_inv(struct mvpp2 *priv, int index)
  1248. {
  1249. /* Write index - indirect access */
  1250. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
  1251. mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(MVPP2_PRS_TCAM_INV_WORD),
  1252. MVPP2_PRS_TCAM_INV_MASK);
  1253. }
  1254. /* Enable shadow table entry and set its lookup ID */
  1255. static void mvpp2_prs_shadow_set(struct mvpp2 *priv, int index, int lu)
  1256. {
  1257. priv->prs_shadow[index].valid = true;
  1258. priv->prs_shadow[index].lu = lu;
  1259. }
  1260. /* Update ri fields in shadow table entry */
  1261. static void mvpp2_prs_shadow_ri_set(struct mvpp2 *priv, int index,
  1262. unsigned int ri, unsigned int ri_mask)
  1263. {
  1264. priv->prs_shadow[index].ri_mask = ri_mask;
  1265. priv->prs_shadow[index].ri = ri;
  1266. }
  1267. /* Update lookup field in tcam sw entry */
  1268. static void mvpp2_prs_tcam_lu_set(struct mvpp2_prs_entry *pe, unsigned int lu)
  1269. {
  1270. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_LU_BYTE);
  1271. pe->tcam.byte[MVPP2_PRS_TCAM_LU_BYTE] = lu;
  1272. pe->tcam.byte[enable_off] = MVPP2_PRS_LU_MASK;
  1273. }
  1274. /* Update mask for single port in tcam sw entry */
  1275. static void mvpp2_prs_tcam_port_set(struct mvpp2_prs_entry *pe,
  1276. unsigned int port, bool add)
  1277. {
  1278. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
  1279. if (add)
  1280. pe->tcam.byte[enable_off] &= ~(1 << port);
  1281. else
  1282. pe->tcam.byte[enable_off] |= 1 << port;
  1283. }
  1284. /* Update port map in tcam sw entry */
  1285. static void mvpp2_prs_tcam_port_map_set(struct mvpp2_prs_entry *pe,
  1286. unsigned int ports)
  1287. {
  1288. unsigned char port_mask = MVPP2_PRS_PORT_MASK;
  1289. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
  1290. pe->tcam.byte[MVPP2_PRS_TCAM_PORT_BYTE] = 0;
  1291. pe->tcam.byte[enable_off] &= ~port_mask;
  1292. pe->tcam.byte[enable_off] |= ~ports & MVPP2_PRS_PORT_MASK;
  1293. }
  1294. /* Obtain port map from tcam sw entry */
  1295. static unsigned int mvpp2_prs_tcam_port_map_get(struct mvpp2_prs_entry *pe)
  1296. {
  1297. int enable_off = MVPP2_PRS_TCAM_EN_OFFS(MVPP2_PRS_TCAM_PORT_BYTE);
  1298. return ~(pe->tcam.byte[enable_off]) & MVPP2_PRS_PORT_MASK;
  1299. }
  1300. /* Set byte of data and its enable bits in tcam sw entry */
  1301. static void mvpp2_prs_tcam_data_byte_set(struct mvpp2_prs_entry *pe,
  1302. unsigned int offs, unsigned char byte,
  1303. unsigned char enable)
  1304. {
  1305. pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)] = byte;
  1306. pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)] = enable;
  1307. }
  1308. /* Get byte of data and its enable bits from tcam sw entry */
  1309. static void mvpp2_prs_tcam_data_byte_get(struct mvpp2_prs_entry *pe,
  1310. unsigned int offs, unsigned char *byte,
  1311. unsigned char *enable)
  1312. {
  1313. *byte = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(offs)];
  1314. *enable = pe->tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(offs)];
  1315. }
  1316. /* Set ethertype in tcam sw entry */
  1317. static void mvpp2_prs_match_etype(struct mvpp2_prs_entry *pe, int offset,
  1318. unsigned short ethertype)
  1319. {
  1320. mvpp2_prs_tcam_data_byte_set(pe, offset + 0, ethertype >> 8, 0xff);
  1321. mvpp2_prs_tcam_data_byte_set(pe, offset + 1, ethertype & 0xff, 0xff);
  1322. }
  1323. /* Set bits in sram sw entry */
  1324. static void mvpp2_prs_sram_bits_set(struct mvpp2_prs_entry *pe, int bit_num,
  1325. int val)
  1326. {
  1327. pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] |= (val << (bit_num % 8));
  1328. }
  1329. /* Clear bits in sram sw entry */
  1330. static void mvpp2_prs_sram_bits_clear(struct mvpp2_prs_entry *pe, int bit_num,
  1331. int val)
  1332. {
  1333. pe->sram.byte[MVPP2_BIT_TO_BYTE(bit_num)] &= ~(val << (bit_num % 8));
  1334. }
  1335. /* Update ri bits in sram sw entry */
  1336. static void mvpp2_prs_sram_ri_update(struct mvpp2_prs_entry *pe,
  1337. unsigned int bits, unsigned int mask)
  1338. {
  1339. unsigned int i;
  1340. for (i = 0; i < MVPP2_PRS_SRAM_RI_CTRL_BITS; i++) {
  1341. int ri_off = MVPP2_PRS_SRAM_RI_OFFS;
  1342. if (!(mask & BIT(i)))
  1343. continue;
  1344. if (bits & BIT(i))
  1345. mvpp2_prs_sram_bits_set(pe, ri_off + i, 1);
  1346. else
  1347. mvpp2_prs_sram_bits_clear(pe, ri_off + i, 1);
  1348. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_RI_CTRL_OFFS + i, 1);
  1349. }
  1350. }
  1351. /* Update ai bits in sram sw entry */
  1352. static void mvpp2_prs_sram_ai_update(struct mvpp2_prs_entry *pe,
  1353. unsigned int bits, unsigned int mask)
  1354. {
  1355. unsigned int i;
  1356. int ai_off = MVPP2_PRS_SRAM_AI_OFFS;
  1357. for (i = 0; i < MVPP2_PRS_SRAM_AI_CTRL_BITS; i++) {
  1358. if (!(mask & BIT(i)))
  1359. continue;
  1360. if (bits & BIT(i))
  1361. mvpp2_prs_sram_bits_set(pe, ai_off + i, 1);
  1362. else
  1363. mvpp2_prs_sram_bits_clear(pe, ai_off + i, 1);
  1364. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_AI_CTRL_OFFS + i, 1);
  1365. }
  1366. }
  1367. /* Read ai bits from sram sw entry */
  1368. static int mvpp2_prs_sram_ai_get(struct mvpp2_prs_entry *pe)
  1369. {
  1370. u8 bits;
  1371. int ai_off = MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_AI_OFFS);
  1372. int ai_en_off = ai_off + 1;
  1373. int ai_shift = MVPP2_PRS_SRAM_AI_OFFS % 8;
  1374. bits = (pe->sram.byte[ai_off] >> ai_shift) |
  1375. (pe->sram.byte[ai_en_off] << (8 - ai_shift));
  1376. return bits;
  1377. }
  1378. /* In sram sw entry set lookup ID field of the tcam key to be used in the next
  1379. * lookup interation
  1380. */
  1381. static void mvpp2_prs_sram_next_lu_set(struct mvpp2_prs_entry *pe,
  1382. unsigned int lu)
  1383. {
  1384. int sram_next_off = MVPP2_PRS_SRAM_NEXT_LU_OFFS;
  1385. mvpp2_prs_sram_bits_clear(pe, sram_next_off,
  1386. MVPP2_PRS_SRAM_NEXT_LU_MASK);
  1387. mvpp2_prs_sram_bits_set(pe, sram_next_off, lu);
  1388. }
  1389. /* In the sram sw entry set sign and value of the next lookup offset
  1390. * and the offset value generated to the classifier
  1391. */
  1392. static void mvpp2_prs_sram_shift_set(struct mvpp2_prs_entry *pe, int shift,
  1393. unsigned int op)
  1394. {
  1395. /* Set sign */
  1396. if (shift < 0) {
  1397. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
  1398. shift = 0 - shift;
  1399. } else {
  1400. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_SHIFT_SIGN_BIT, 1);
  1401. }
  1402. /* Set value */
  1403. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_SHIFT_OFFS)] =
  1404. (unsigned char)shift;
  1405. /* Reset and set operation */
  1406. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS,
  1407. MVPP2_PRS_SRAM_OP_SEL_SHIFT_MASK);
  1408. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_SHIFT_OFFS, op);
  1409. /* Set base offset as current */
  1410. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
  1411. }
  1412. /* In the sram sw entry set sign and value of the user defined offset
  1413. * generated to the classifier
  1414. */
  1415. static void mvpp2_prs_sram_offset_set(struct mvpp2_prs_entry *pe,
  1416. unsigned int type, int offset,
  1417. unsigned int op)
  1418. {
  1419. /* Set sign */
  1420. if (offset < 0) {
  1421. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
  1422. offset = 0 - offset;
  1423. } else {
  1424. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_SIGN_BIT, 1);
  1425. }
  1426. /* Set value */
  1427. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_OFFS,
  1428. MVPP2_PRS_SRAM_UDF_MASK);
  1429. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_OFFS, offset);
  1430. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
  1431. MVPP2_PRS_SRAM_UDF_BITS)] &=
  1432. ~(MVPP2_PRS_SRAM_UDF_MASK >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
  1433. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_UDF_OFFS +
  1434. MVPP2_PRS_SRAM_UDF_BITS)] |=
  1435. (offset >> (8 - (MVPP2_PRS_SRAM_UDF_OFFS % 8)));
  1436. /* Set offset type */
  1437. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS,
  1438. MVPP2_PRS_SRAM_UDF_TYPE_MASK);
  1439. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_UDF_TYPE_OFFS, type);
  1440. /* Set offset operation */
  1441. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS,
  1442. MVPP2_PRS_SRAM_OP_SEL_UDF_MASK);
  1443. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS, op);
  1444. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
  1445. MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] &=
  1446. ~(MVPP2_PRS_SRAM_OP_SEL_UDF_MASK >>
  1447. (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
  1448. pe->sram.byte[MVPP2_BIT_TO_BYTE(MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS +
  1449. MVPP2_PRS_SRAM_OP_SEL_UDF_BITS)] |=
  1450. (op >> (8 - (MVPP2_PRS_SRAM_OP_SEL_UDF_OFFS % 8)));
  1451. /* Set base offset as current */
  1452. mvpp2_prs_sram_bits_clear(pe, MVPP2_PRS_SRAM_OP_SEL_BASE_OFFS, 1);
  1453. }
  1454. /* Find parser flow entry */
  1455. static struct mvpp2_prs_entry *mvpp2_prs_flow_find(struct mvpp2 *priv, int flow)
  1456. {
  1457. struct mvpp2_prs_entry *pe;
  1458. int tid;
  1459. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  1460. if (!pe)
  1461. return NULL;
  1462. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
  1463. /* Go through the all entires with MVPP2_PRS_LU_FLOWS */
  1464. for (tid = MVPP2_PRS_TCAM_SRAM_SIZE - 1; tid >= 0; tid--) {
  1465. u8 bits;
  1466. if (!priv->prs_shadow[tid].valid ||
  1467. priv->prs_shadow[tid].lu != MVPP2_PRS_LU_FLOWS)
  1468. continue;
  1469. pe->index = tid;
  1470. mvpp2_prs_hw_read(priv, pe);
  1471. bits = mvpp2_prs_sram_ai_get(pe);
  1472. /* Sram store classification lookup ID in AI bits [5:0] */
  1473. if ((bits & MVPP2_PRS_FLOW_ID_MASK) == flow)
  1474. return pe;
  1475. }
  1476. kfree(pe);
  1477. return NULL;
  1478. }
  1479. /* Return first free tcam index, seeking from start to end */
  1480. static int mvpp2_prs_tcam_first_free(struct mvpp2 *priv, unsigned char start,
  1481. unsigned char end)
  1482. {
  1483. int tid;
  1484. if (start > end)
  1485. swap(start, end);
  1486. if (end >= MVPP2_PRS_TCAM_SRAM_SIZE)
  1487. end = MVPP2_PRS_TCAM_SRAM_SIZE - 1;
  1488. for (tid = start; tid <= end; tid++) {
  1489. if (!priv->prs_shadow[tid].valid)
  1490. return tid;
  1491. }
  1492. return -EINVAL;
  1493. }
  1494. /* Enable/disable dropping all mac da's */
  1495. static void mvpp2_prs_mac_drop_all_set(struct mvpp2 *priv, int port, bool add)
  1496. {
  1497. struct mvpp2_prs_entry pe;
  1498. if (priv->prs_shadow[MVPP2_PE_DROP_ALL].valid) {
  1499. /* Entry exist - update port only */
  1500. pe.index = MVPP2_PE_DROP_ALL;
  1501. mvpp2_prs_hw_read(priv, &pe);
  1502. } else {
  1503. /* Entry doesn't exist - create new */
  1504. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1505. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1506. pe.index = MVPP2_PE_DROP_ALL;
  1507. /* Non-promiscuous mode for all ports - DROP unknown packets */
  1508. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
  1509. MVPP2_PRS_RI_DROP_MASK);
  1510. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1511. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1512. /* Update shadow table */
  1513. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1514. /* Mask all ports */
  1515. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1516. }
  1517. /* Update port mask */
  1518. mvpp2_prs_tcam_port_set(&pe, port, add);
  1519. mvpp2_prs_hw_write(priv, &pe);
  1520. }
  1521. /* Set port to promiscuous mode */
  1522. static void mvpp2_prs_mac_promisc_set(struct mvpp2 *priv, int port, bool add)
  1523. {
  1524. struct mvpp2_prs_entry pe;
  1525. /* Promiscuous mode - Accept unknown packets */
  1526. if (priv->prs_shadow[MVPP2_PE_MAC_PROMISCUOUS].valid) {
  1527. /* Entry exist - update port only */
  1528. pe.index = MVPP2_PE_MAC_PROMISCUOUS;
  1529. mvpp2_prs_hw_read(priv, &pe);
  1530. } else {
  1531. /* Entry doesn't exist - create new */
  1532. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1533. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1534. pe.index = MVPP2_PE_MAC_PROMISCUOUS;
  1535. /* Continue - set next lookup */
  1536. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
  1537. /* Set result info bits */
  1538. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_UCAST,
  1539. MVPP2_PRS_RI_L2_CAST_MASK);
  1540. /* Shift to ethertype */
  1541. mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
  1542. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1543. /* Mask all ports */
  1544. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1545. /* Update shadow table */
  1546. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1547. }
  1548. /* Update port mask */
  1549. mvpp2_prs_tcam_port_set(&pe, port, add);
  1550. mvpp2_prs_hw_write(priv, &pe);
  1551. }
  1552. /* Accept multicast */
  1553. static void mvpp2_prs_mac_multi_set(struct mvpp2 *priv, int port, int index,
  1554. bool add)
  1555. {
  1556. struct mvpp2_prs_entry pe;
  1557. unsigned char da_mc;
  1558. /* Ethernet multicast address first byte is
  1559. * 0x01 for IPv4 and 0x33 for IPv6
  1560. */
  1561. da_mc = (index == MVPP2_PE_MAC_MC_ALL) ? 0x01 : 0x33;
  1562. if (priv->prs_shadow[index].valid) {
  1563. /* Entry exist - update port only */
  1564. pe.index = index;
  1565. mvpp2_prs_hw_read(priv, &pe);
  1566. } else {
  1567. /* Entry doesn't exist - create new */
  1568. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1569. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1570. pe.index = index;
  1571. /* Continue - set next lookup */
  1572. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_DSA);
  1573. /* Set result info bits */
  1574. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L2_MCAST,
  1575. MVPP2_PRS_RI_L2_CAST_MASK);
  1576. /* Update tcam entry data first byte */
  1577. mvpp2_prs_tcam_data_byte_set(&pe, 0, da_mc, 0xff);
  1578. /* Shift to ethertype */
  1579. mvpp2_prs_sram_shift_set(&pe, 2 * ETH_ALEN,
  1580. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1581. /* Mask all ports */
  1582. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1583. /* Update shadow table */
  1584. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1585. }
  1586. /* Update port mask */
  1587. mvpp2_prs_tcam_port_set(&pe, port, add);
  1588. mvpp2_prs_hw_write(priv, &pe);
  1589. }
  1590. /* Parser per-port initialization */
  1591. static void mvpp2_prs_hw_port_init(struct mvpp2 *priv, int port, int lu_first,
  1592. int lu_max, int offset)
  1593. {
  1594. u32 val;
  1595. /* Set lookup ID */
  1596. val = mvpp2_read(priv, MVPP2_PRS_INIT_LOOKUP_REG);
  1597. val &= ~MVPP2_PRS_PORT_LU_MASK(port);
  1598. val |= MVPP2_PRS_PORT_LU_VAL(port, lu_first);
  1599. mvpp2_write(priv, MVPP2_PRS_INIT_LOOKUP_REG, val);
  1600. /* Set maximum number of loops for packet received from port */
  1601. val = mvpp2_read(priv, MVPP2_PRS_MAX_LOOP_REG(port));
  1602. val &= ~MVPP2_PRS_MAX_LOOP_MASK(port);
  1603. val |= MVPP2_PRS_MAX_LOOP_VAL(port, lu_max);
  1604. mvpp2_write(priv, MVPP2_PRS_MAX_LOOP_REG(port), val);
  1605. /* Set initial offset for packet header extraction for the first
  1606. * searching loop
  1607. */
  1608. val = mvpp2_read(priv, MVPP2_PRS_INIT_OFFS_REG(port));
  1609. val &= ~MVPP2_PRS_INIT_OFF_MASK(port);
  1610. val |= MVPP2_PRS_INIT_OFF_VAL(port, offset);
  1611. mvpp2_write(priv, MVPP2_PRS_INIT_OFFS_REG(port), val);
  1612. }
  1613. /* Default flow entries initialization for all ports */
  1614. static void mvpp2_prs_def_flow_init(struct mvpp2 *priv)
  1615. {
  1616. struct mvpp2_prs_entry pe;
  1617. int port;
  1618. for (port = 0; port < MVPP2_MAX_PORTS; port++) {
  1619. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1620. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1621. pe.index = MVPP2_PE_FIRST_DEFAULT_FLOW - port;
  1622. /* Mask all ports */
  1623. mvpp2_prs_tcam_port_map_set(&pe, 0);
  1624. /* Set flow ID*/
  1625. mvpp2_prs_sram_ai_update(&pe, port, MVPP2_PRS_FLOW_ID_MASK);
  1626. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
  1627. /* Update shadow table and hw entry */
  1628. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_FLOWS);
  1629. mvpp2_prs_hw_write(priv, &pe);
  1630. }
  1631. }
  1632. /* Set default entry for Marvell Header field */
  1633. static void mvpp2_prs_mh_init(struct mvpp2 *priv)
  1634. {
  1635. struct mvpp2_prs_entry pe;
  1636. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1637. pe.index = MVPP2_PE_MH_DEFAULT;
  1638. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MH);
  1639. mvpp2_prs_sram_shift_set(&pe, MVPP2_MH_SIZE,
  1640. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1641. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1642. /* Unmask all ports */
  1643. mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
  1644. /* Update shadow table and hw entry */
  1645. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MH);
  1646. mvpp2_prs_hw_write(priv, &pe);
  1647. }
  1648. /* Set default entires (place holder) for promiscuous, non-promiscuous and
  1649. * multicast MAC addresses
  1650. */
  1651. static void mvpp2_prs_mac_init(struct mvpp2 *priv)
  1652. {
  1653. struct mvpp2_prs_entry pe;
  1654. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1655. /* Non-promiscuous mode for all ports - DROP unknown packets */
  1656. pe.index = MVPP2_PE_MAC_NON_PROMISCUOUS;
  1657. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_MAC);
  1658. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_DROP_MASK,
  1659. MVPP2_PRS_RI_DROP_MASK);
  1660. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1661. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1662. /* Unmask all ports */
  1663. mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
  1664. /* Update shadow table and hw entry */
  1665. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_MAC);
  1666. mvpp2_prs_hw_write(priv, &pe);
  1667. /* place holders only - no ports */
  1668. mvpp2_prs_mac_drop_all_set(priv, 0, false);
  1669. mvpp2_prs_mac_promisc_set(priv, 0, false);
  1670. mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_ALL, 0, false);
  1671. mvpp2_prs_mac_multi_set(priv, MVPP2_PE_MAC_MC_IP6, 0, false);
  1672. }
  1673. /* Match basic ethertypes */
  1674. static int mvpp2_prs_etype_init(struct mvpp2 *priv)
  1675. {
  1676. struct mvpp2_prs_entry pe;
  1677. int tid;
  1678. /* Ethertype: PPPoE */
  1679. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1680. MVPP2_PE_LAST_FREE_TID);
  1681. if (tid < 0)
  1682. return tid;
  1683. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1684. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1685. pe.index = tid;
  1686. mvpp2_prs_match_etype(&pe, 0, PROT_PPP_SES);
  1687. mvpp2_prs_sram_shift_set(&pe, MVPP2_PPPOE_HDR_SIZE,
  1688. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1689. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_PPPOE);
  1690. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_PPPOE_MASK,
  1691. MVPP2_PRS_RI_PPPOE_MASK);
  1692. /* Update shadow table and hw entry */
  1693. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1694. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1695. priv->prs_shadow[pe.index].finish = false;
  1696. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_PPPOE_MASK,
  1697. MVPP2_PRS_RI_PPPOE_MASK);
  1698. mvpp2_prs_hw_write(priv, &pe);
  1699. /* Ethertype: ARP */
  1700. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1701. MVPP2_PE_LAST_FREE_TID);
  1702. if (tid < 0)
  1703. return tid;
  1704. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1705. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1706. pe.index = tid;
  1707. mvpp2_prs_match_etype(&pe, 0, PROT_ARP);
  1708. /* Generate flow in the next iteration*/
  1709. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1710. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1711. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_ARP,
  1712. MVPP2_PRS_RI_L3_PROTO_MASK);
  1713. /* Set L3 offset */
  1714. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1715. MVPP2_ETH_TYPE_LEN,
  1716. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1717. /* Update shadow table and hw entry */
  1718. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1719. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1720. priv->prs_shadow[pe.index].finish = true;
  1721. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_ARP,
  1722. MVPP2_PRS_RI_L3_PROTO_MASK);
  1723. mvpp2_prs_hw_write(priv, &pe);
  1724. /* Ethertype: LBTD */
  1725. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1726. MVPP2_PE_LAST_FREE_TID);
  1727. if (tid < 0)
  1728. return tid;
  1729. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1730. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1731. pe.index = tid;
  1732. mvpp2_prs_match_etype(&pe, 0, MVPP2_IP_LBDT_TYPE);
  1733. /* Generate flow in the next iteration*/
  1734. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1735. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1736. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
  1737. MVPP2_PRS_RI_UDF3_RX_SPECIAL,
  1738. MVPP2_PRS_RI_CPU_CODE_MASK |
  1739. MVPP2_PRS_RI_UDF3_MASK);
  1740. /* Set L3 offset */
  1741. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1742. MVPP2_ETH_TYPE_LEN,
  1743. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1744. /* Update shadow table and hw entry */
  1745. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1746. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1747. priv->prs_shadow[pe.index].finish = true;
  1748. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_CPU_CODE_RX_SPEC |
  1749. MVPP2_PRS_RI_UDF3_RX_SPECIAL,
  1750. MVPP2_PRS_RI_CPU_CODE_MASK |
  1751. MVPP2_PRS_RI_UDF3_MASK);
  1752. mvpp2_prs_hw_write(priv, &pe);
  1753. /* Ethertype: IPv4 without options */
  1754. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1755. MVPP2_PE_LAST_FREE_TID);
  1756. if (tid < 0)
  1757. return tid;
  1758. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1759. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1760. pe.index = tid;
  1761. mvpp2_prs_match_etype(&pe, 0, PROT_IP);
  1762. mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
  1763. MVPP2_PRS_IPV4_HEAD | MVPP2_PRS_IPV4_IHL,
  1764. MVPP2_PRS_IPV4_HEAD_MASK |
  1765. MVPP2_PRS_IPV4_IHL_MASK);
  1766. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP4);
  1767. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4,
  1768. MVPP2_PRS_RI_L3_PROTO_MASK);
  1769. /* Skip eth_type + 4 bytes of IP header */
  1770. mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 4,
  1771. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1772. /* Set L3 offset */
  1773. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1774. MVPP2_ETH_TYPE_LEN,
  1775. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1776. /* Update shadow table and hw entry */
  1777. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1778. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1779. priv->prs_shadow[pe.index].finish = false;
  1780. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4,
  1781. MVPP2_PRS_RI_L3_PROTO_MASK);
  1782. mvpp2_prs_hw_write(priv, &pe);
  1783. /* Ethertype: IPv4 with options */
  1784. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1785. MVPP2_PE_LAST_FREE_TID);
  1786. if (tid < 0)
  1787. return tid;
  1788. pe.index = tid;
  1789. /* Clear tcam data before updating */
  1790. pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE(MVPP2_ETH_TYPE_LEN)] = 0x0;
  1791. pe.tcam.byte[MVPP2_PRS_TCAM_DATA_BYTE_EN(MVPP2_ETH_TYPE_LEN)] = 0x0;
  1792. mvpp2_prs_tcam_data_byte_set(&pe, MVPP2_ETH_TYPE_LEN,
  1793. MVPP2_PRS_IPV4_HEAD,
  1794. MVPP2_PRS_IPV4_HEAD_MASK);
  1795. /* Clear ri before updating */
  1796. pe.sram.word[MVPP2_PRS_SRAM_RI_WORD] = 0x0;
  1797. pe.sram.word[MVPP2_PRS_SRAM_RI_CTRL_WORD] = 0x0;
  1798. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP4_OPT,
  1799. MVPP2_PRS_RI_L3_PROTO_MASK);
  1800. /* Update shadow table and hw entry */
  1801. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1802. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1803. priv->prs_shadow[pe.index].finish = false;
  1804. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP4_OPT,
  1805. MVPP2_PRS_RI_L3_PROTO_MASK);
  1806. mvpp2_prs_hw_write(priv, &pe);
  1807. /* Ethertype: IPv6 without options */
  1808. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1809. MVPP2_PE_LAST_FREE_TID);
  1810. if (tid < 0)
  1811. return tid;
  1812. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1813. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1814. pe.index = tid;
  1815. mvpp2_prs_match_etype(&pe, 0, PROT_IPV6);
  1816. /* Skip DIP of IPV6 header */
  1817. mvpp2_prs_sram_shift_set(&pe, MVPP2_ETH_TYPE_LEN + 8 +
  1818. MVPP2_MAX_L3_ADDR_SIZE,
  1819. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  1820. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_IP6);
  1821. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_IP6,
  1822. MVPP2_PRS_RI_L3_PROTO_MASK);
  1823. /* Set L3 offset */
  1824. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1825. MVPP2_ETH_TYPE_LEN,
  1826. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1827. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1828. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1829. priv->prs_shadow[pe.index].finish = false;
  1830. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_IP6,
  1831. MVPP2_PRS_RI_L3_PROTO_MASK);
  1832. mvpp2_prs_hw_write(priv, &pe);
  1833. /* Default entry for MVPP2_PRS_LU_L2 - Unknown ethtype */
  1834. memset(&pe, 0, sizeof(struct mvpp2_prs_entry));
  1835. mvpp2_prs_tcam_lu_set(&pe, MVPP2_PRS_LU_L2);
  1836. pe.index = MVPP2_PE_ETH_TYPE_UN;
  1837. /* Unmask all ports */
  1838. mvpp2_prs_tcam_port_map_set(&pe, MVPP2_PRS_PORT_MASK);
  1839. /* Generate flow in the next iteration*/
  1840. mvpp2_prs_sram_bits_set(&pe, MVPP2_PRS_SRAM_LU_GEN_BIT, 1);
  1841. mvpp2_prs_sram_next_lu_set(&pe, MVPP2_PRS_LU_FLOWS);
  1842. mvpp2_prs_sram_ri_update(&pe, MVPP2_PRS_RI_L3_UN,
  1843. MVPP2_PRS_RI_L3_PROTO_MASK);
  1844. /* Set L3 offset even it's unknown L3 */
  1845. mvpp2_prs_sram_offset_set(&pe, MVPP2_PRS_SRAM_UDF_TYPE_L3,
  1846. MVPP2_ETH_TYPE_LEN,
  1847. MVPP2_PRS_SRAM_OP_SEL_UDF_ADD);
  1848. /* Update shadow table and hw entry */
  1849. mvpp2_prs_shadow_set(priv, pe.index, MVPP2_PRS_LU_L2);
  1850. priv->prs_shadow[pe.index].udf = MVPP2_PRS_UDF_L2_DEF;
  1851. priv->prs_shadow[pe.index].finish = true;
  1852. mvpp2_prs_shadow_ri_set(priv, pe.index, MVPP2_PRS_RI_L3_UN,
  1853. MVPP2_PRS_RI_L3_PROTO_MASK);
  1854. mvpp2_prs_hw_write(priv, &pe);
  1855. return 0;
  1856. }
  1857. /* Parser default initialization */
  1858. static int mvpp2_prs_default_init(struct udevice *dev,
  1859. struct mvpp2 *priv)
  1860. {
  1861. int err, index, i;
  1862. /* Enable tcam table */
  1863. mvpp2_write(priv, MVPP2_PRS_TCAM_CTRL_REG, MVPP2_PRS_TCAM_EN_MASK);
  1864. /* Clear all tcam and sram entries */
  1865. for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++) {
  1866. mvpp2_write(priv, MVPP2_PRS_TCAM_IDX_REG, index);
  1867. for (i = 0; i < MVPP2_PRS_TCAM_WORDS; i++)
  1868. mvpp2_write(priv, MVPP2_PRS_TCAM_DATA_REG(i), 0);
  1869. mvpp2_write(priv, MVPP2_PRS_SRAM_IDX_REG, index);
  1870. for (i = 0; i < MVPP2_PRS_SRAM_WORDS; i++)
  1871. mvpp2_write(priv, MVPP2_PRS_SRAM_DATA_REG(i), 0);
  1872. }
  1873. /* Invalidate all tcam entries */
  1874. for (index = 0; index < MVPP2_PRS_TCAM_SRAM_SIZE; index++)
  1875. mvpp2_prs_hw_inv(priv, index);
  1876. priv->prs_shadow = devm_kcalloc(dev, MVPP2_PRS_TCAM_SRAM_SIZE,
  1877. sizeof(struct mvpp2_prs_shadow),
  1878. GFP_KERNEL);
  1879. if (!priv->prs_shadow)
  1880. return -ENOMEM;
  1881. /* Always start from lookup = 0 */
  1882. for (index = 0; index < MVPP2_MAX_PORTS; index++)
  1883. mvpp2_prs_hw_port_init(priv, index, MVPP2_PRS_LU_MH,
  1884. MVPP2_PRS_PORT_LU_MAX, 0);
  1885. mvpp2_prs_def_flow_init(priv);
  1886. mvpp2_prs_mh_init(priv);
  1887. mvpp2_prs_mac_init(priv);
  1888. err = mvpp2_prs_etype_init(priv);
  1889. if (err)
  1890. return err;
  1891. return 0;
  1892. }
  1893. /* Compare MAC DA with tcam entry data */
  1894. static bool mvpp2_prs_mac_range_equals(struct mvpp2_prs_entry *pe,
  1895. const u8 *da, unsigned char *mask)
  1896. {
  1897. unsigned char tcam_byte, tcam_mask;
  1898. int index;
  1899. for (index = 0; index < ETH_ALEN; index++) {
  1900. mvpp2_prs_tcam_data_byte_get(pe, index, &tcam_byte, &tcam_mask);
  1901. if (tcam_mask != mask[index])
  1902. return false;
  1903. if ((tcam_mask & tcam_byte) != (da[index] & mask[index]))
  1904. return false;
  1905. }
  1906. return true;
  1907. }
  1908. /* Find tcam entry with matched pair <MAC DA, port> */
  1909. static struct mvpp2_prs_entry *
  1910. mvpp2_prs_mac_da_range_find(struct mvpp2 *priv, int pmap, const u8 *da,
  1911. unsigned char *mask, int udf_type)
  1912. {
  1913. struct mvpp2_prs_entry *pe;
  1914. int tid;
  1915. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  1916. if (!pe)
  1917. return NULL;
  1918. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
  1919. /* Go through the all entires with MVPP2_PRS_LU_MAC */
  1920. for (tid = MVPP2_PE_FIRST_FREE_TID;
  1921. tid <= MVPP2_PE_LAST_FREE_TID; tid++) {
  1922. unsigned int entry_pmap;
  1923. if (!priv->prs_shadow[tid].valid ||
  1924. (priv->prs_shadow[tid].lu != MVPP2_PRS_LU_MAC) ||
  1925. (priv->prs_shadow[tid].udf != udf_type))
  1926. continue;
  1927. pe->index = tid;
  1928. mvpp2_prs_hw_read(priv, pe);
  1929. entry_pmap = mvpp2_prs_tcam_port_map_get(pe);
  1930. if (mvpp2_prs_mac_range_equals(pe, da, mask) &&
  1931. entry_pmap == pmap)
  1932. return pe;
  1933. }
  1934. kfree(pe);
  1935. return NULL;
  1936. }
  1937. /* Update parser's mac da entry */
  1938. static int mvpp2_prs_mac_da_accept(struct mvpp2 *priv, int port,
  1939. const u8 *da, bool add)
  1940. {
  1941. struct mvpp2_prs_entry *pe;
  1942. unsigned int pmap, len, ri;
  1943. unsigned char mask[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
  1944. int tid;
  1945. /* Scan TCAM and see if entry with this <MAC DA, port> already exist */
  1946. pe = mvpp2_prs_mac_da_range_find(priv, (1 << port), da, mask,
  1947. MVPP2_PRS_UDF_MAC_DEF);
  1948. /* No such entry */
  1949. if (!pe) {
  1950. if (!add)
  1951. return 0;
  1952. /* Create new TCAM entry */
  1953. /* Find first range mac entry*/
  1954. for (tid = MVPP2_PE_FIRST_FREE_TID;
  1955. tid <= MVPP2_PE_LAST_FREE_TID; tid++)
  1956. if (priv->prs_shadow[tid].valid &&
  1957. (priv->prs_shadow[tid].lu == MVPP2_PRS_LU_MAC) &&
  1958. (priv->prs_shadow[tid].udf ==
  1959. MVPP2_PRS_UDF_MAC_RANGE))
  1960. break;
  1961. /* Go through the all entries from first to last */
  1962. tid = mvpp2_prs_tcam_first_free(priv, MVPP2_PE_FIRST_FREE_TID,
  1963. tid - 1);
  1964. if (tid < 0)
  1965. return tid;
  1966. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  1967. if (!pe)
  1968. return -1;
  1969. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_MAC);
  1970. pe->index = tid;
  1971. /* Mask all ports */
  1972. mvpp2_prs_tcam_port_map_set(pe, 0);
  1973. }
  1974. /* Update port mask */
  1975. mvpp2_prs_tcam_port_set(pe, port, add);
  1976. /* Invalidate the entry if no ports are left enabled */
  1977. pmap = mvpp2_prs_tcam_port_map_get(pe);
  1978. if (pmap == 0) {
  1979. if (add) {
  1980. kfree(pe);
  1981. return -1;
  1982. }
  1983. mvpp2_prs_hw_inv(priv, pe->index);
  1984. priv->prs_shadow[pe->index].valid = false;
  1985. kfree(pe);
  1986. return 0;
  1987. }
  1988. /* Continue - set next lookup */
  1989. mvpp2_prs_sram_next_lu_set(pe, MVPP2_PRS_LU_DSA);
  1990. /* Set match on DA */
  1991. len = ETH_ALEN;
  1992. while (len--)
  1993. mvpp2_prs_tcam_data_byte_set(pe, len, da[len], 0xff);
  1994. /* Set result info bits */
  1995. ri = MVPP2_PRS_RI_L2_UCAST | MVPP2_PRS_RI_MAC_ME_MASK;
  1996. mvpp2_prs_sram_ri_update(pe, ri, MVPP2_PRS_RI_L2_CAST_MASK |
  1997. MVPP2_PRS_RI_MAC_ME_MASK);
  1998. mvpp2_prs_shadow_ri_set(priv, pe->index, ri, MVPP2_PRS_RI_L2_CAST_MASK |
  1999. MVPP2_PRS_RI_MAC_ME_MASK);
  2000. /* Shift to ethertype */
  2001. mvpp2_prs_sram_shift_set(pe, 2 * ETH_ALEN,
  2002. MVPP2_PRS_SRAM_OP_SEL_SHIFT_ADD);
  2003. /* Update shadow table and hw entry */
  2004. priv->prs_shadow[pe->index].udf = MVPP2_PRS_UDF_MAC_DEF;
  2005. mvpp2_prs_shadow_set(priv, pe->index, MVPP2_PRS_LU_MAC);
  2006. mvpp2_prs_hw_write(priv, pe);
  2007. kfree(pe);
  2008. return 0;
  2009. }
  2010. static int mvpp2_prs_update_mac_da(struct mvpp2_port *port, const u8 *da)
  2011. {
  2012. int err;
  2013. /* Remove old parser entry */
  2014. err = mvpp2_prs_mac_da_accept(port->priv, port->id, port->dev_addr,
  2015. false);
  2016. if (err)
  2017. return err;
  2018. /* Add new parser entry */
  2019. err = mvpp2_prs_mac_da_accept(port->priv, port->id, da, true);
  2020. if (err)
  2021. return err;
  2022. /* Set addr in the device */
  2023. memcpy(port->dev_addr, da, ETH_ALEN);
  2024. return 0;
  2025. }
  2026. /* Set prs flow for the port */
  2027. static int mvpp2_prs_def_flow(struct mvpp2_port *port)
  2028. {
  2029. struct mvpp2_prs_entry *pe;
  2030. int tid;
  2031. pe = mvpp2_prs_flow_find(port->priv, port->id);
  2032. /* Such entry not exist */
  2033. if (!pe) {
  2034. /* Go through the all entires from last to first */
  2035. tid = mvpp2_prs_tcam_first_free(port->priv,
  2036. MVPP2_PE_LAST_FREE_TID,
  2037. MVPP2_PE_FIRST_FREE_TID);
  2038. if (tid < 0)
  2039. return tid;
  2040. pe = kzalloc(sizeof(*pe), GFP_KERNEL);
  2041. if (!pe)
  2042. return -ENOMEM;
  2043. mvpp2_prs_tcam_lu_set(pe, MVPP2_PRS_LU_FLOWS);
  2044. pe->index = tid;
  2045. /* Set flow ID*/
  2046. mvpp2_prs_sram_ai_update(pe, port->id, MVPP2_PRS_FLOW_ID_MASK);
  2047. mvpp2_prs_sram_bits_set(pe, MVPP2_PRS_SRAM_LU_DONE_BIT, 1);
  2048. /* Update shadow table */
  2049. mvpp2_prs_shadow_set(port->priv, pe->index, MVPP2_PRS_LU_FLOWS);
  2050. }
  2051. mvpp2_prs_tcam_port_map_set(pe, (1 << port->id));
  2052. mvpp2_prs_hw_write(port->priv, pe);
  2053. kfree(pe);
  2054. return 0;
  2055. }
  2056. /* Classifier configuration routines */
  2057. /* Update classification flow table registers */
  2058. static void mvpp2_cls_flow_write(struct mvpp2 *priv,
  2059. struct mvpp2_cls_flow_entry *fe)
  2060. {
  2061. mvpp2_write(priv, MVPP2_CLS_FLOW_INDEX_REG, fe->index);
  2062. mvpp2_write(priv, MVPP2_CLS_FLOW_TBL0_REG, fe->data[0]);
  2063. mvpp2_write(priv, MVPP2_CLS_FLOW_TBL1_REG, fe->data[1]);
  2064. mvpp2_write(priv, MVPP2_CLS_FLOW_TBL2_REG, fe->data[2]);
  2065. }
  2066. /* Update classification lookup table register */
  2067. static void mvpp2_cls_lookup_write(struct mvpp2 *priv,
  2068. struct mvpp2_cls_lookup_entry *le)
  2069. {
  2070. u32 val;
  2071. val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid;
  2072. mvpp2_write(priv, MVPP2_CLS_LKP_INDEX_REG, val);
  2073. mvpp2_write(priv, MVPP2_CLS_LKP_TBL_REG, le->data);
  2074. }
  2075. /* Classifier default initialization */
  2076. static void mvpp2_cls_init(struct mvpp2 *priv)
  2077. {
  2078. struct mvpp2_cls_lookup_entry le;
  2079. struct mvpp2_cls_flow_entry fe;
  2080. int index;
  2081. /* Enable classifier */
  2082. mvpp2_write(priv, MVPP2_CLS_MODE_REG, MVPP2_CLS_MODE_ACTIVE_MASK);
  2083. /* Clear classifier flow table */
  2084. memset(&fe.data, 0, MVPP2_CLS_FLOWS_TBL_DATA_WORDS);
  2085. for (index = 0; index < MVPP2_CLS_FLOWS_TBL_SIZE; index++) {
  2086. fe.index = index;
  2087. mvpp2_cls_flow_write(priv, &fe);
  2088. }
  2089. /* Clear classifier lookup table */
  2090. le.data = 0;
  2091. for (index = 0; index < MVPP2_CLS_LKP_TBL_SIZE; index++) {
  2092. le.lkpid = index;
  2093. le.way = 0;
  2094. mvpp2_cls_lookup_write(priv, &le);
  2095. le.way = 1;
  2096. mvpp2_cls_lookup_write(priv, &le);
  2097. }
  2098. }
  2099. static void mvpp2_cls_port_config(struct mvpp2_port *port)
  2100. {
  2101. struct mvpp2_cls_lookup_entry le;
  2102. u32 val;
  2103. /* Set way for the port */
  2104. val = mvpp2_read(port->priv, MVPP2_CLS_PORT_WAY_REG);
  2105. val &= ~MVPP2_CLS_PORT_WAY_MASK(port->id);
  2106. mvpp2_write(port->priv, MVPP2_CLS_PORT_WAY_REG, val);
  2107. /* Pick the entry to be accessed in lookup ID decoding table
  2108. * according to the way and lkpid.
  2109. */
  2110. le.lkpid = port->id;
  2111. le.way = 0;
  2112. le.data = 0;
  2113. /* Set initial CPU queue for receiving packets */
  2114. le.data &= ~MVPP2_CLS_LKP_TBL_RXQ_MASK;
  2115. le.data |= port->first_rxq;
  2116. /* Disable classification engines */
  2117. le.data &= ~MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK;
  2118. /* Update lookup ID table entry */
  2119. mvpp2_cls_lookup_write(port->priv, &le);
  2120. }
  2121. /* Set CPU queue number for oversize packets */
  2122. static void mvpp2_cls_oversize_rxq_set(struct mvpp2_port *port)
  2123. {
  2124. u32 val;
  2125. mvpp2_write(port->priv, MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port->id),
  2126. port->first_rxq & MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK);
  2127. mvpp2_write(port->priv, MVPP2_CLS_SWFWD_P2HQ_REG(port->id),
  2128. (port->first_rxq >> MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS));
  2129. val = mvpp2_read(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG);
  2130. val |= MVPP2_CLS_SWFWD_PCTRL_MASK(port->id);
  2131. mvpp2_write(port->priv, MVPP2_CLS_SWFWD_PCTRL_REG, val);
  2132. }
  2133. /* Buffer Manager configuration routines */
  2134. /* Create pool */
  2135. static int mvpp2_bm_pool_create(struct udevice *dev,
  2136. struct mvpp2 *priv,
  2137. struct mvpp2_bm_pool *bm_pool, int size)
  2138. {
  2139. u32 val;
  2140. /* Number of buffer pointers must be a multiple of 16, as per
  2141. * hardware constraints
  2142. */
  2143. if (!IS_ALIGNED(size, 16))
  2144. return -EINVAL;
  2145. bm_pool->virt_addr = buffer_loc.bm_pool[bm_pool->id];
  2146. bm_pool->dma_addr = (dma_addr_t)buffer_loc.bm_pool[bm_pool->id];
  2147. if (!bm_pool->virt_addr)
  2148. return -ENOMEM;
  2149. if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
  2150. MVPP2_BM_POOL_PTR_ALIGN)) {
  2151. dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
  2152. bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
  2153. return -ENOMEM;
  2154. }
  2155. mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
  2156. lower_32_bits(bm_pool->dma_addr));
  2157. if (priv->hw_version == MVPP22)
  2158. mvpp2_write(priv, MVPP22_BM_POOL_BASE_HIGH_REG,
  2159. (upper_32_bits(bm_pool->dma_addr) &
  2160. MVPP22_BM_POOL_BASE_HIGH_MASK));
  2161. mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
  2162. val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
  2163. val |= MVPP2_BM_START_MASK;
  2164. mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
  2165. bm_pool->type = MVPP2_BM_FREE;
  2166. bm_pool->size = size;
  2167. bm_pool->pkt_size = 0;
  2168. bm_pool->buf_num = 0;
  2169. return 0;
  2170. }
  2171. /* Set pool buffer size */
  2172. static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
  2173. struct mvpp2_bm_pool *bm_pool,
  2174. int buf_size)
  2175. {
  2176. u32 val;
  2177. bm_pool->buf_size = buf_size;
  2178. val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
  2179. mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
  2180. }
  2181. /* Free all buffers from the pool */
  2182. static void mvpp2_bm_bufs_free(struct udevice *dev, struct mvpp2 *priv,
  2183. struct mvpp2_bm_pool *bm_pool)
  2184. {
  2185. int i;
  2186. for (i = 0; i < bm_pool->buf_num; i++) {
  2187. /* Allocate buffer back from the buffer manager */
  2188. mvpp2_read(priv, MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
  2189. }
  2190. bm_pool->buf_num = 0;
  2191. }
  2192. /* Cleanup pool */
  2193. static int mvpp2_bm_pool_destroy(struct udevice *dev,
  2194. struct mvpp2 *priv,
  2195. struct mvpp2_bm_pool *bm_pool)
  2196. {
  2197. u32 val;
  2198. mvpp2_bm_bufs_free(dev, priv, bm_pool);
  2199. if (bm_pool->buf_num) {
  2200. dev_err(dev, "cannot free all buffers in pool %d\n", bm_pool->id);
  2201. return 0;
  2202. }
  2203. val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
  2204. val |= MVPP2_BM_STOP_MASK;
  2205. mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
  2206. return 0;
  2207. }
  2208. static int mvpp2_bm_pools_init(struct udevice *dev,
  2209. struct mvpp2 *priv)
  2210. {
  2211. int i, err, size;
  2212. struct mvpp2_bm_pool *bm_pool;
  2213. /* Create all pools with maximum size */
  2214. size = MVPP2_BM_POOL_SIZE_MAX;
  2215. for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
  2216. bm_pool = &priv->bm_pools[i];
  2217. bm_pool->id = i;
  2218. err = mvpp2_bm_pool_create(dev, priv, bm_pool, size);
  2219. if (err)
  2220. goto err_unroll_pools;
  2221. mvpp2_bm_pool_bufsize_set(priv, bm_pool, RX_BUFFER_SIZE);
  2222. }
  2223. return 0;
  2224. err_unroll_pools:
  2225. dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
  2226. for (i = i - 1; i >= 0; i--)
  2227. mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
  2228. return err;
  2229. }
  2230. static int mvpp2_bm_init(struct udevice *dev, struct mvpp2 *priv)
  2231. {
  2232. int i, err;
  2233. for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
  2234. /* Mask BM all interrupts */
  2235. mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
  2236. /* Clear BM cause register */
  2237. mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
  2238. }
  2239. /* Allocate and initialize BM pools */
  2240. priv->bm_pools = devm_kcalloc(dev, MVPP2_BM_POOLS_NUM,
  2241. sizeof(struct mvpp2_bm_pool), GFP_KERNEL);
  2242. if (!priv->bm_pools)
  2243. return -ENOMEM;
  2244. err = mvpp2_bm_pools_init(dev, priv);
  2245. if (err < 0)
  2246. return err;
  2247. return 0;
  2248. }
  2249. /* Attach long pool to rxq */
  2250. static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
  2251. int lrxq, int long_pool)
  2252. {
  2253. u32 val, mask;
  2254. int prxq;
  2255. /* Get queue physical ID */
  2256. prxq = port->rxqs[lrxq]->id;
  2257. if (port->priv->hw_version == MVPP21)
  2258. mask = MVPP21_RXQ_POOL_LONG_MASK;
  2259. else
  2260. mask = MVPP22_RXQ_POOL_LONG_MASK;
  2261. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
  2262. val &= ~mask;
  2263. val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
  2264. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
  2265. }
  2266. /* Set pool number in a BM cookie */
  2267. static inline u32 mvpp2_bm_cookie_pool_set(u32 cookie, int pool)
  2268. {
  2269. u32 bm;
  2270. bm = cookie & ~(0xFF << MVPP2_BM_COOKIE_POOL_OFFS);
  2271. bm |= ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS);
  2272. return bm;
  2273. }
  2274. /* Get pool number from a BM cookie */
  2275. static inline int mvpp2_bm_cookie_pool_get(unsigned long cookie)
  2276. {
  2277. return (cookie >> MVPP2_BM_COOKIE_POOL_OFFS) & 0xFF;
  2278. }
  2279. /* Release buffer to BM */
  2280. static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
  2281. dma_addr_t buf_dma_addr,
  2282. unsigned long buf_phys_addr)
  2283. {
  2284. if (port->priv->hw_version == MVPP22) {
  2285. u32 val = 0;
  2286. if (sizeof(dma_addr_t) == 8)
  2287. val |= upper_32_bits(buf_dma_addr) &
  2288. MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
  2289. if (sizeof(phys_addr_t) == 8)
  2290. val |= (upper_32_bits(buf_phys_addr)
  2291. << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
  2292. MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
  2293. mvpp2_write(port->priv, MVPP22_BM_ADDR_HIGH_RLS_REG, val);
  2294. }
  2295. /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
  2296. * returned in the "cookie" field of the RX
  2297. * descriptor. Instead of storing the virtual address, we
  2298. * store the physical address
  2299. */
  2300. mvpp2_write(port->priv, MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
  2301. mvpp2_write(port->priv, MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
  2302. }
  2303. /* Refill BM pool */
  2304. static void mvpp2_pool_refill(struct mvpp2_port *port, u32 bm,
  2305. dma_addr_t dma_addr,
  2306. phys_addr_t phys_addr)
  2307. {
  2308. int pool = mvpp2_bm_cookie_pool_get(bm);
  2309. mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
  2310. }
  2311. /* Allocate buffers for the pool */
  2312. static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
  2313. struct mvpp2_bm_pool *bm_pool, int buf_num)
  2314. {
  2315. int i;
  2316. if (buf_num < 0 ||
  2317. (buf_num + bm_pool->buf_num > bm_pool->size)) {
  2318. netdev_err(port->dev,
  2319. "cannot allocate %d buffers for pool %d\n",
  2320. buf_num, bm_pool->id);
  2321. return 0;
  2322. }
  2323. for (i = 0; i < buf_num; i++) {
  2324. mvpp2_bm_pool_put(port, bm_pool->id,
  2325. (dma_addr_t)buffer_loc.rx_buffer[i],
  2326. (unsigned long)buffer_loc.rx_buffer[i]);
  2327. }
  2328. /* Update BM driver with number of buffers added to pool */
  2329. bm_pool->buf_num += i;
  2330. return i;
  2331. }
  2332. /* Notify the driver that BM pool is being used as specific type and return the
  2333. * pool pointer on success
  2334. */
  2335. static struct mvpp2_bm_pool *
  2336. mvpp2_bm_pool_use(struct mvpp2_port *port, int pool, enum mvpp2_bm_type type,
  2337. int pkt_size)
  2338. {
  2339. struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
  2340. int num;
  2341. if (new_pool->type != MVPP2_BM_FREE && new_pool->type != type) {
  2342. netdev_err(port->dev, "mixing pool types is forbidden\n");
  2343. return NULL;
  2344. }
  2345. if (new_pool->type == MVPP2_BM_FREE)
  2346. new_pool->type = type;
  2347. /* Allocate buffers in case BM pool is used as long pool, but packet
  2348. * size doesn't match MTU or BM pool hasn't being used yet
  2349. */
  2350. if (((type == MVPP2_BM_SWF_LONG) && (pkt_size > new_pool->pkt_size)) ||
  2351. (new_pool->pkt_size == 0)) {
  2352. int pkts_num;
  2353. /* Set default buffer number or free all the buffers in case
  2354. * the pool is not empty
  2355. */
  2356. pkts_num = new_pool->buf_num;
  2357. if (pkts_num == 0)
  2358. pkts_num = type == MVPP2_BM_SWF_LONG ?
  2359. MVPP2_BM_LONG_BUF_NUM :
  2360. MVPP2_BM_SHORT_BUF_NUM;
  2361. else
  2362. mvpp2_bm_bufs_free(NULL,
  2363. port->priv, new_pool);
  2364. new_pool->pkt_size = pkt_size;
  2365. /* Allocate buffers for this pool */
  2366. num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
  2367. if (num != pkts_num) {
  2368. dev_err(dev, "pool %d: %d of %d allocated\n",
  2369. new_pool->id, num, pkts_num);
  2370. return NULL;
  2371. }
  2372. }
  2373. return new_pool;
  2374. }
  2375. /* Initialize pools for swf */
  2376. static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
  2377. {
  2378. int rxq;
  2379. if (!port->pool_long) {
  2380. port->pool_long =
  2381. mvpp2_bm_pool_use(port, MVPP2_BM_SWF_LONG_POOL(port->id),
  2382. MVPP2_BM_SWF_LONG,
  2383. port->pkt_size);
  2384. if (!port->pool_long)
  2385. return -ENOMEM;
  2386. port->pool_long->port_map |= (1 << port->id);
  2387. for (rxq = 0; rxq < rxq_number; rxq++)
  2388. mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
  2389. }
  2390. return 0;
  2391. }
  2392. /* Port configuration routines */
  2393. static void mvpp2_port_mii_set(struct mvpp2_port *port)
  2394. {
  2395. u32 val;
  2396. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2397. switch (port->phy_interface) {
  2398. case PHY_INTERFACE_MODE_SGMII:
  2399. val |= MVPP2_GMAC_INBAND_AN_MASK;
  2400. break;
  2401. case PHY_INTERFACE_MODE_RGMII:
  2402. case PHY_INTERFACE_MODE_RGMII_ID:
  2403. val |= MVPP2_GMAC_PORT_RGMII_MASK;
  2404. default:
  2405. val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
  2406. }
  2407. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2408. }
  2409. static void mvpp2_port_fc_adv_enable(struct mvpp2_port *port)
  2410. {
  2411. u32 val;
  2412. val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2413. val |= MVPP2_GMAC_FC_ADV_EN;
  2414. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2415. }
  2416. static void mvpp2_port_enable(struct mvpp2_port *port)
  2417. {
  2418. u32 val;
  2419. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2420. val |= MVPP2_GMAC_PORT_EN_MASK;
  2421. val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
  2422. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2423. }
  2424. static void mvpp2_port_disable(struct mvpp2_port *port)
  2425. {
  2426. u32 val;
  2427. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2428. val &= ~(MVPP2_GMAC_PORT_EN_MASK);
  2429. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2430. }
  2431. /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
  2432. static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
  2433. {
  2434. u32 val;
  2435. val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
  2436. ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
  2437. writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
  2438. }
  2439. /* Configure loopback port */
  2440. static void mvpp2_port_loopback_set(struct mvpp2_port *port)
  2441. {
  2442. u32 val;
  2443. val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
  2444. if (port->speed == 1000)
  2445. val |= MVPP2_GMAC_GMII_LB_EN_MASK;
  2446. else
  2447. val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
  2448. if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
  2449. val |= MVPP2_GMAC_PCS_LB_EN_MASK;
  2450. else
  2451. val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
  2452. writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
  2453. }
  2454. static void mvpp2_port_reset(struct mvpp2_port *port)
  2455. {
  2456. u32 val;
  2457. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
  2458. ~MVPP2_GMAC_PORT_RESET_MASK;
  2459. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2460. while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
  2461. MVPP2_GMAC_PORT_RESET_MASK)
  2462. continue;
  2463. }
  2464. /* Change maximum receive size of the port */
  2465. static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
  2466. {
  2467. u32 val;
  2468. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2469. val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
  2470. val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
  2471. MVPP2_GMAC_MAX_RX_SIZE_OFFS);
  2472. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2473. }
  2474. /* PPv2.2 GoP/GMAC config */
  2475. /* Set the MAC to reset or exit from reset */
  2476. static int gop_gmac_reset(struct mvpp2_port *port, int reset)
  2477. {
  2478. u32 val;
  2479. /* read - modify - write */
  2480. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2481. if (reset)
  2482. val |= MVPP2_GMAC_PORT_RESET_MASK;
  2483. else
  2484. val &= ~MVPP2_GMAC_PORT_RESET_MASK;
  2485. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2486. return 0;
  2487. }
  2488. /*
  2489. * gop_gpcs_mode_cfg
  2490. *
  2491. * Configure port to working with Gig PCS or don't.
  2492. */
  2493. static int gop_gpcs_mode_cfg(struct mvpp2_port *port, int en)
  2494. {
  2495. u32 val;
  2496. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2497. if (en)
  2498. val |= MVPP2_GMAC_PCS_ENABLE_MASK;
  2499. else
  2500. val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
  2501. /* enable / disable PCS on this port */
  2502. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2503. return 0;
  2504. }
  2505. static int gop_bypass_clk_cfg(struct mvpp2_port *port, int en)
  2506. {
  2507. u32 val;
  2508. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2509. if (en)
  2510. val |= MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
  2511. else
  2512. val &= ~MVPP2_GMAC_CLK_125_BYPS_EN_MASK;
  2513. /* enable / disable PCS on this port */
  2514. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2515. return 0;
  2516. }
  2517. static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
  2518. {
  2519. u32 val, thresh;
  2520. /*
  2521. * Configure minimal level of the Tx FIFO before the lower part
  2522. * starts to read a packet
  2523. */
  2524. thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
  2525. val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2526. val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  2527. val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
  2528. writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2529. /* Disable bypass of sync module */
  2530. val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
  2531. val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
  2532. /* configure DP clock select according to mode */
  2533. val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
  2534. /* configure QSGMII bypass according to mode */
  2535. val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
  2536. writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
  2537. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2538. /*
  2539. * Configure GIG MAC to 1000Base-X mode connected to a fiber
  2540. * transceiver
  2541. */
  2542. val |= MVPP2_GMAC_PORT_TYPE_MASK;
  2543. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2544. /* configure AN 0x9268 */
  2545. val = MVPP2_GMAC_EN_PCS_AN |
  2546. MVPP2_GMAC_AN_BYPASS_EN |
  2547. MVPP2_GMAC_CONFIG_MII_SPEED |
  2548. MVPP2_GMAC_CONFIG_GMII_SPEED |
  2549. MVPP2_GMAC_FC_ADV_EN |
  2550. MVPP2_GMAC_CONFIG_FULL_DUPLEX |
  2551. MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
  2552. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2553. }
  2554. static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
  2555. {
  2556. u32 val, thresh;
  2557. /*
  2558. * Configure minimal level of the Tx FIFO before the lower part
  2559. * starts to read a packet
  2560. */
  2561. thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
  2562. val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2563. val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  2564. val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
  2565. writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2566. /* Disable bypass of sync module */
  2567. val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
  2568. val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
  2569. /* configure DP clock select according to mode */
  2570. val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
  2571. /* configure QSGMII bypass according to mode */
  2572. val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
  2573. writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
  2574. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2575. /* configure GIG MAC to SGMII mode */
  2576. val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
  2577. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2578. /* configure AN */
  2579. val = MVPP2_GMAC_EN_PCS_AN |
  2580. MVPP2_GMAC_AN_BYPASS_EN |
  2581. MVPP2_GMAC_AN_SPEED_EN |
  2582. MVPP2_GMAC_EN_FC_AN |
  2583. MVPP2_GMAC_AN_DUPLEX_EN |
  2584. MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
  2585. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2586. }
  2587. static void gop_gmac_rgmii_cfg(struct mvpp2_port *port)
  2588. {
  2589. u32 val, thresh;
  2590. /*
  2591. * Configure minimal level of the Tx FIFO before the lower part
  2592. * starts to read a packet
  2593. */
  2594. thresh = MVPP2_RGMII_TX_FIFO_MIN_TH;
  2595. val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2596. val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  2597. val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
  2598. writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  2599. /* Disable bypass of sync module */
  2600. val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
  2601. val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
  2602. /* configure DP clock select according to mode */
  2603. val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
  2604. val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
  2605. val |= MVPP2_GMAC_CTRL4_EXT_PIN_GMII_SEL_MASK;
  2606. writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
  2607. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2608. /* configure GIG MAC to SGMII mode */
  2609. val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
  2610. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2611. /* configure AN 0xb8e8 */
  2612. val = MVPP2_GMAC_AN_BYPASS_EN |
  2613. MVPP2_GMAC_AN_SPEED_EN |
  2614. MVPP2_GMAC_EN_FC_AN |
  2615. MVPP2_GMAC_AN_DUPLEX_EN |
  2616. MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
  2617. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  2618. }
  2619. /* Set the internal mux's to the required MAC in the GOP */
  2620. static int gop_gmac_mode_cfg(struct mvpp2_port *port)
  2621. {
  2622. u32 val;
  2623. /* Set TX FIFO thresholds */
  2624. switch (port->phy_interface) {
  2625. case PHY_INTERFACE_MODE_SGMII:
  2626. if (port->phy_speed == 2500)
  2627. gop_gmac_sgmii2_5_cfg(port);
  2628. else
  2629. gop_gmac_sgmii_cfg(port);
  2630. break;
  2631. case PHY_INTERFACE_MODE_RGMII:
  2632. case PHY_INTERFACE_MODE_RGMII_ID:
  2633. gop_gmac_rgmii_cfg(port);
  2634. break;
  2635. default:
  2636. return -1;
  2637. }
  2638. /* Jumbo frame support - 0x1400*2= 0x2800 bytes */
  2639. val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
  2640. val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
  2641. val |= 0x1400 << MVPP2_GMAC_MAX_RX_SIZE_OFFS;
  2642. writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
  2643. /* PeriodicXonEn disable */
  2644. val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
  2645. val &= ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
  2646. writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
  2647. return 0;
  2648. }
  2649. static void gop_xlg_2_gig_mac_cfg(struct mvpp2_port *port)
  2650. {
  2651. u32 val;
  2652. /* relevant only for MAC0 (XLG0 and GMAC0) */
  2653. if (port->gop_id > 0)
  2654. return;
  2655. /* configure 1Gig MAC mode */
  2656. val = readl(port->base + MVPP22_XLG_CTRL3_REG);
  2657. val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
  2658. val |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
  2659. writel(val, port->base + MVPP22_XLG_CTRL3_REG);
  2660. }
  2661. static int gop_gpcs_reset(struct mvpp2_port *port, int reset)
  2662. {
  2663. u32 val;
  2664. val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
  2665. if (reset)
  2666. val &= ~MVPP2_GMAC_SGMII_MODE_MASK;
  2667. else
  2668. val |= MVPP2_GMAC_SGMII_MODE_MASK;
  2669. writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
  2670. return 0;
  2671. }
  2672. /* Set the internal mux's to the required PCS in the PI */
  2673. static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
  2674. {
  2675. u32 val;
  2676. int lane;
  2677. switch (num_of_lanes) {
  2678. case 1:
  2679. lane = 0;
  2680. break;
  2681. case 2:
  2682. lane = 1;
  2683. break;
  2684. case 4:
  2685. lane = 2;
  2686. break;
  2687. default:
  2688. return -1;
  2689. }
  2690. /* configure XG MAC mode */
  2691. val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
  2692. val &= ~MVPP22_XPCS_PCSMODE_MASK;
  2693. val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
  2694. val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
  2695. writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
  2696. return 0;
  2697. }
  2698. static int gop_mpcs_mode(struct mvpp2_port *port)
  2699. {
  2700. u32 val;
  2701. /* configure PCS40G COMMON CONTROL */
  2702. val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
  2703. val &= ~FORWARD_ERROR_CORRECTION_MASK;
  2704. writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
  2705. /* configure PCS CLOCK RESET */
  2706. val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
  2707. val &= ~CLK_DIVISION_RATIO_MASK;
  2708. val |= 1 << CLK_DIVISION_RATIO_OFFS;
  2709. writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
  2710. val &= ~CLK_DIV_PHASE_SET_MASK;
  2711. val |= MAC_CLK_RESET_MASK;
  2712. val |= RX_SD_CLK_RESET_MASK;
  2713. val |= TX_SD_CLK_RESET_MASK;
  2714. writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
  2715. return 0;
  2716. }
  2717. /* Set the internal mux's to the required MAC in the GOP */
  2718. static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
  2719. {
  2720. u32 val;
  2721. /* configure 10G MAC mode */
  2722. val = readl(port->base + MVPP22_XLG_CTRL0_REG);
  2723. val |= MVPP22_XLG_RX_FC_EN;
  2724. writel(val, port->base + MVPP22_XLG_CTRL0_REG);
  2725. val = readl(port->base + MVPP22_XLG_CTRL3_REG);
  2726. val &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
  2727. val |= MVPP22_XLG_CTRL3_MACMODESELECT_10GMAC;
  2728. writel(val, port->base + MVPP22_XLG_CTRL3_REG);
  2729. /* read - modify - write */
  2730. val = readl(port->base + MVPP22_XLG_CTRL4_REG);
  2731. val &= ~MVPP22_XLG_MODE_DMA_1G;
  2732. val |= MVPP22_XLG_FORWARD_PFC_EN;
  2733. val |= MVPP22_XLG_FORWARD_802_3X_FC_EN;
  2734. val &= ~MVPP22_XLG_EN_IDLE_CHECK_FOR_LINK;
  2735. writel(val, port->base + MVPP22_XLG_CTRL4_REG);
  2736. /* Jumbo frame support: 0x1400 * 2 = 0x2800 bytes */
  2737. val = readl(port->base + MVPP22_XLG_CTRL1_REG);
  2738. val &= ~MVPP22_XLG_MAX_RX_SIZE_MASK;
  2739. val |= 0x1400 << MVPP22_XLG_MAX_RX_SIZE_OFFS;
  2740. writel(val, port->base + MVPP22_XLG_CTRL1_REG);
  2741. /* unmask link change interrupt */
  2742. val = readl(port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
  2743. val |= MVPP22_XLG_INTERRUPT_LINK_CHANGE;
  2744. val |= 1; /* unmask summary bit */
  2745. writel(val, port->base + MVPP22_XLG_INTERRUPT_MASK_REG);
  2746. return 0;
  2747. }
  2748. /* Set PCS to reset or exit from reset */
  2749. static int gop_xpcs_reset(struct mvpp2_port *port, int reset)
  2750. {
  2751. u32 val;
  2752. /* read - modify - write */
  2753. val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
  2754. if (reset)
  2755. val &= ~MVPP22_XPCS_PCSRESET;
  2756. else
  2757. val |= MVPP22_XPCS_PCSRESET;
  2758. writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
  2759. return 0;
  2760. }
  2761. /* Set the MAC to reset or exit from reset */
  2762. static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset)
  2763. {
  2764. u32 val;
  2765. /* read - modify - write */
  2766. val = readl(port->base + MVPP22_XLG_CTRL0_REG);
  2767. if (reset)
  2768. val &= ~MVPP22_XLG_MAC_RESETN;
  2769. else
  2770. val |= MVPP22_XLG_MAC_RESETN;
  2771. writel(val, port->base + MVPP22_XLG_CTRL0_REG);
  2772. return 0;
  2773. }
  2774. /*
  2775. * gop_port_init
  2776. *
  2777. * Init physical port. Configures the port mode and all it's elements
  2778. * accordingly.
  2779. * Does not verify that the selected mode/port number is valid at the
  2780. * core level.
  2781. */
  2782. static int gop_port_init(struct mvpp2_port *port)
  2783. {
  2784. int mac_num = port->gop_id;
  2785. int num_of_act_lanes;
  2786. if (mac_num >= MVPP22_GOP_MAC_NUM) {
  2787. netdev_err(NULL, "%s: illegal port number %d", __func__,
  2788. mac_num);
  2789. return -1;
  2790. }
  2791. switch (port->phy_interface) {
  2792. case PHY_INTERFACE_MODE_RGMII:
  2793. case PHY_INTERFACE_MODE_RGMII_ID:
  2794. gop_gmac_reset(port, 1);
  2795. /* configure PCS */
  2796. gop_gpcs_mode_cfg(port, 0);
  2797. gop_bypass_clk_cfg(port, 1);
  2798. /* configure MAC */
  2799. gop_gmac_mode_cfg(port);
  2800. /* pcs unreset */
  2801. gop_gpcs_reset(port, 0);
  2802. /* mac unreset */
  2803. gop_gmac_reset(port, 0);
  2804. break;
  2805. case PHY_INTERFACE_MODE_SGMII:
  2806. /* configure PCS */
  2807. gop_gpcs_mode_cfg(port, 1);
  2808. /* configure MAC */
  2809. gop_gmac_mode_cfg(port);
  2810. /* select proper Mac mode */
  2811. gop_xlg_2_gig_mac_cfg(port);
  2812. /* pcs unreset */
  2813. gop_gpcs_reset(port, 0);
  2814. /* mac unreset */
  2815. gop_gmac_reset(port, 0);
  2816. break;
  2817. case PHY_INTERFACE_MODE_SFI:
  2818. num_of_act_lanes = 2;
  2819. mac_num = 0;
  2820. /* configure PCS */
  2821. gop_xpcs_mode(port, num_of_act_lanes);
  2822. gop_mpcs_mode(port);
  2823. /* configure MAC */
  2824. gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
  2825. /* pcs unreset */
  2826. gop_xpcs_reset(port, 0);
  2827. /* mac unreset */
  2828. gop_xlg_mac_reset(port, 0);
  2829. break;
  2830. default:
  2831. netdev_err(NULL, "%s: Requested port mode (%d) not supported\n",
  2832. __func__, port->phy_interface);
  2833. return -1;
  2834. }
  2835. return 0;
  2836. }
  2837. static void gop_xlg_mac_port_enable(struct mvpp2_port *port, int enable)
  2838. {
  2839. u32 val;
  2840. val = readl(port->base + MVPP22_XLG_CTRL0_REG);
  2841. if (enable) {
  2842. /* Enable port and MIB counters update */
  2843. val |= MVPP22_XLG_PORT_EN;
  2844. val &= ~MVPP22_XLG_MIBCNT_DIS;
  2845. } else {
  2846. /* Disable port */
  2847. val &= ~MVPP22_XLG_PORT_EN;
  2848. }
  2849. writel(val, port->base + MVPP22_XLG_CTRL0_REG);
  2850. }
  2851. static void gop_port_enable(struct mvpp2_port *port, int enable)
  2852. {
  2853. switch (port->phy_interface) {
  2854. case PHY_INTERFACE_MODE_RGMII:
  2855. case PHY_INTERFACE_MODE_RGMII_ID:
  2856. case PHY_INTERFACE_MODE_SGMII:
  2857. if (enable)
  2858. mvpp2_port_enable(port);
  2859. else
  2860. mvpp2_port_disable(port);
  2861. break;
  2862. case PHY_INTERFACE_MODE_SFI:
  2863. gop_xlg_mac_port_enable(port, enable);
  2864. break;
  2865. default:
  2866. netdev_err(NULL, "%s: Wrong port mode (%d)\n", __func__,
  2867. port->phy_interface);
  2868. return;
  2869. }
  2870. }
  2871. /* RFU1 functions */
  2872. static inline u32 gop_rfu1_read(struct mvpp2 *priv, u32 offset)
  2873. {
  2874. return readl(priv->rfu1_base + offset);
  2875. }
  2876. static inline void gop_rfu1_write(struct mvpp2 *priv, u32 offset, u32 data)
  2877. {
  2878. writel(data, priv->rfu1_base + offset);
  2879. }
  2880. static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
  2881. {
  2882. u32 val = 0;
  2883. if (gop_id == 2) {
  2884. if (phy_type == PHY_INTERFACE_MODE_SGMII)
  2885. val |= MV_NETC_GE_MAC2_SGMII;
  2886. }
  2887. if (gop_id == 3) {
  2888. if (phy_type == PHY_INTERFACE_MODE_SGMII)
  2889. val |= MV_NETC_GE_MAC3_SGMII;
  2890. else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
  2891. phy_type == PHY_INTERFACE_MODE_RGMII_ID)
  2892. val |= MV_NETC_GE_MAC3_RGMII;
  2893. }
  2894. return val;
  2895. }
  2896. static void gop_netc_active_port(struct mvpp2 *priv, int gop_id, u32 val)
  2897. {
  2898. u32 reg;
  2899. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
  2900. reg &= ~(NETC_PORTS_ACTIVE_MASK(gop_id));
  2901. val <<= NETC_PORTS_ACTIVE_OFFSET(gop_id);
  2902. val &= NETC_PORTS_ACTIVE_MASK(gop_id);
  2903. reg |= val;
  2904. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
  2905. }
  2906. static void gop_netc_mii_mode(struct mvpp2 *priv, int gop_id, u32 val)
  2907. {
  2908. u32 reg;
  2909. reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
  2910. reg &= ~NETC_GBE_PORT1_MII_MODE_MASK;
  2911. val <<= NETC_GBE_PORT1_MII_MODE_OFFS;
  2912. val &= NETC_GBE_PORT1_MII_MODE_MASK;
  2913. reg |= val;
  2914. gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
  2915. }
  2916. static void gop_netc_gop_reset(struct mvpp2 *priv, u32 val)
  2917. {
  2918. u32 reg;
  2919. reg = gop_rfu1_read(priv, GOP_SOFT_RESET_1_REG);
  2920. reg &= ~NETC_GOP_SOFT_RESET_MASK;
  2921. val <<= NETC_GOP_SOFT_RESET_OFFS;
  2922. val &= NETC_GOP_SOFT_RESET_MASK;
  2923. reg |= val;
  2924. gop_rfu1_write(priv, GOP_SOFT_RESET_1_REG, reg);
  2925. }
  2926. static void gop_netc_gop_clock_logic_set(struct mvpp2 *priv, u32 val)
  2927. {
  2928. u32 reg;
  2929. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
  2930. reg &= ~NETC_CLK_DIV_PHASE_MASK;
  2931. val <<= NETC_CLK_DIV_PHASE_OFFS;
  2932. val &= NETC_CLK_DIV_PHASE_MASK;
  2933. reg |= val;
  2934. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
  2935. }
  2936. static void gop_netc_port_rf_reset(struct mvpp2 *priv, int gop_id, u32 val)
  2937. {
  2938. u32 reg;
  2939. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_1_REG);
  2940. reg &= ~(NETC_PORT_GIG_RF_RESET_MASK(gop_id));
  2941. val <<= NETC_PORT_GIG_RF_RESET_OFFS(gop_id);
  2942. val &= NETC_PORT_GIG_RF_RESET_MASK(gop_id);
  2943. reg |= val;
  2944. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_1_REG, reg);
  2945. }
  2946. static void gop_netc_gbe_sgmii_mode_select(struct mvpp2 *priv, int gop_id,
  2947. u32 val)
  2948. {
  2949. u32 reg, mask, offset;
  2950. if (gop_id == 2) {
  2951. mask = NETC_GBE_PORT0_SGMII_MODE_MASK;
  2952. offset = NETC_GBE_PORT0_SGMII_MODE_OFFS;
  2953. } else {
  2954. mask = NETC_GBE_PORT1_SGMII_MODE_MASK;
  2955. offset = NETC_GBE_PORT1_SGMII_MODE_OFFS;
  2956. }
  2957. reg = gop_rfu1_read(priv, NETCOMP_CONTROL_0_REG);
  2958. reg &= ~mask;
  2959. val <<= offset;
  2960. val &= mask;
  2961. reg |= val;
  2962. gop_rfu1_write(priv, NETCOMP_CONTROL_0_REG, reg);
  2963. }
  2964. static void gop_netc_bus_width_select(struct mvpp2 *priv, u32 val)
  2965. {
  2966. u32 reg;
  2967. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
  2968. reg &= ~NETC_BUS_WIDTH_SELECT_MASK;
  2969. val <<= NETC_BUS_WIDTH_SELECT_OFFS;
  2970. val &= NETC_BUS_WIDTH_SELECT_MASK;
  2971. reg |= val;
  2972. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
  2973. }
  2974. static void gop_netc_sample_stages_timing(struct mvpp2 *priv, u32 val)
  2975. {
  2976. u32 reg;
  2977. reg = gop_rfu1_read(priv, NETCOMP_PORTS_CONTROL_0_REG);
  2978. reg &= ~NETC_GIG_RX_DATA_SAMPLE_MASK;
  2979. val <<= NETC_GIG_RX_DATA_SAMPLE_OFFS;
  2980. val &= NETC_GIG_RX_DATA_SAMPLE_MASK;
  2981. reg |= val;
  2982. gop_rfu1_write(priv, NETCOMP_PORTS_CONTROL_0_REG, reg);
  2983. }
  2984. static void gop_netc_mac_to_xgmii(struct mvpp2 *priv, int gop_id,
  2985. enum mv_netc_phase phase)
  2986. {
  2987. switch (phase) {
  2988. case MV_NETC_FIRST_PHASE:
  2989. /* Set Bus Width to HB mode = 1 */
  2990. gop_netc_bus_width_select(priv, 1);
  2991. /* Select RGMII mode */
  2992. gop_netc_gbe_sgmii_mode_select(priv, gop_id, MV_NETC_GBE_XMII);
  2993. break;
  2994. case MV_NETC_SECOND_PHASE:
  2995. /* De-assert the relevant port HB reset */
  2996. gop_netc_port_rf_reset(priv, gop_id, 1);
  2997. break;
  2998. }
  2999. }
  3000. static void gop_netc_mac_to_sgmii(struct mvpp2 *priv, int gop_id,
  3001. enum mv_netc_phase phase)
  3002. {
  3003. switch (phase) {
  3004. case MV_NETC_FIRST_PHASE:
  3005. /* Set Bus Width to HB mode = 1 */
  3006. gop_netc_bus_width_select(priv, 1);
  3007. /* Select SGMII mode */
  3008. if (gop_id >= 1) {
  3009. gop_netc_gbe_sgmii_mode_select(priv, gop_id,
  3010. MV_NETC_GBE_SGMII);
  3011. }
  3012. /* Configure the sample stages */
  3013. gop_netc_sample_stages_timing(priv, 0);
  3014. /* Configure the ComPhy Selector */
  3015. /* gop_netc_com_phy_selector_config(netComplex); */
  3016. break;
  3017. case MV_NETC_SECOND_PHASE:
  3018. /* De-assert the relevant port HB reset */
  3019. gop_netc_port_rf_reset(priv, gop_id, 1);
  3020. break;
  3021. }
  3022. }
  3023. static int gop_netc_init(struct mvpp2 *priv, enum mv_netc_phase phase)
  3024. {
  3025. u32 c = priv->netc_config;
  3026. if (c & MV_NETC_GE_MAC2_SGMII)
  3027. gop_netc_mac_to_sgmii(priv, 2, phase);
  3028. else
  3029. gop_netc_mac_to_xgmii(priv, 2, phase);
  3030. if (c & MV_NETC_GE_MAC3_SGMII) {
  3031. gop_netc_mac_to_sgmii(priv, 3, phase);
  3032. } else {
  3033. gop_netc_mac_to_xgmii(priv, 3, phase);
  3034. if (c & MV_NETC_GE_MAC3_RGMII)
  3035. gop_netc_mii_mode(priv, 3, MV_NETC_GBE_RGMII);
  3036. else
  3037. gop_netc_mii_mode(priv, 3, MV_NETC_GBE_MII);
  3038. }
  3039. /* Activate gop ports 0, 2, 3 */
  3040. gop_netc_active_port(priv, 0, 1);
  3041. gop_netc_active_port(priv, 2, 1);
  3042. gop_netc_active_port(priv, 3, 1);
  3043. if (phase == MV_NETC_SECOND_PHASE) {
  3044. /* Enable the GOP internal clock logic */
  3045. gop_netc_gop_clock_logic_set(priv, 1);
  3046. /* De-assert GOP unit reset */
  3047. gop_netc_gop_reset(priv, 1);
  3048. }
  3049. return 0;
  3050. }
  3051. /* Set defaults to the MVPP2 port */
  3052. static void mvpp2_defaults_set(struct mvpp2_port *port)
  3053. {
  3054. int tx_port_num, val, queue, ptxq, lrxq;
  3055. if (port->priv->hw_version == MVPP21) {
  3056. /* Configure port to loopback if needed */
  3057. if (port->flags & MVPP2_F_LOOPBACK)
  3058. mvpp2_port_loopback_set(port);
  3059. /* Update TX FIFO MIN Threshold */
  3060. val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  3061. val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
  3062. /* Min. TX threshold must be less than minimal packet length */
  3063. val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
  3064. writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
  3065. }
  3066. /* Disable Legacy WRR, Disable EJP, Release from reset */
  3067. tx_port_num = mvpp2_egress_port(port);
  3068. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
  3069. tx_port_num);
  3070. mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
  3071. /* Close bandwidth for all queues */
  3072. for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
  3073. ptxq = mvpp2_txq_phys(port->id, queue);
  3074. mvpp2_write(port->priv,
  3075. MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
  3076. }
  3077. /* Set refill period to 1 usec, refill tokens
  3078. * and bucket size to maximum
  3079. */
  3080. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG, 0xc8);
  3081. val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
  3082. val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
  3083. val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
  3084. val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
  3085. mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
  3086. val = MVPP2_TXP_TOKEN_SIZE_MAX;
  3087. mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
  3088. /* Set MaximumLowLatencyPacketSize value to 256 */
  3089. mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
  3090. MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
  3091. MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
  3092. /* Enable Rx cache snoop */
  3093. for (lrxq = 0; lrxq < rxq_number; lrxq++) {
  3094. queue = port->rxqs[lrxq]->id;
  3095. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
  3096. val |= MVPP2_SNOOP_PKT_SIZE_MASK |
  3097. MVPP2_SNOOP_BUF_HDR_MASK;
  3098. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
  3099. }
  3100. }
  3101. /* Enable/disable receiving packets */
  3102. static void mvpp2_ingress_enable(struct mvpp2_port *port)
  3103. {
  3104. u32 val;
  3105. int lrxq, queue;
  3106. for (lrxq = 0; lrxq < rxq_number; lrxq++) {
  3107. queue = port->rxqs[lrxq]->id;
  3108. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
  3109. val &= ~MVPP2_RXQ_DISABLE_MASK;
  3110. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
  3111. }
  3112. }
  3113. static void mvpp2_ingress_disable(struct mvpp2_port *port)
  3114. {
  3115. u32 val;
  3116. int lrxq, queue;
  3117. for (lrxq = 0; lrxq < rxq_number; lrxq++) {
  3118. queue = port->rxqs[lrxq]->id;
  3119. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
  3120. val |= MVPP2_RXQ_DISABLE_MASK;
  3121. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
  3122. }
  3123. }
  3124. /* Enable transmit via physical egress queue
  3125. * - HW starts take descriptors from DRAM
  3126. */
  3127. static void mvpp2_egress_enable(struct mvpp2_port *port)
  3128. {
  3129. u32 qmap;
  3130. int queue;
  3131. int tx_port_num = mvpp2_egress_port(port);
  3132. /* Enable all initialized TXs. */
  3133. qmap = 0;
  3134. for (queue = 0; queue < txq_number; queue++) {
  3135. struct mvpp2_tx_queue *txq = port->txqs[queue];
  3136. if (txq->descs != NULL)
  3137. qmap |= (1 << queue);
  3138. }
  3139. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  3140. mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
  3141. }
  3142. /* Disable transmit via physical egress queue
  3143. * - HW doesn't take descriptors from DRAM
  3144. */
  3145. static void mvpp2_egress_disable(struct mvpp2_port *port)
  3146. {
  3147. u32 reg_data;
  3148. int delay;
  3149. int tx_port_num = mvpp2_egress_port(port);
  3150. /* Issue stop command for active channels only */
  3151. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  3152. reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
  3153. MVPP2_TXP_SCHED_ENQ_MASK;
  3154. if (reg_data != 0)
  3155. mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
  3156. (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
  3157. /* Wait for all Tx activity to terminate. */
  3158. delay = 0;
  3159. do {
  3160. if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
  3161. netdev_warn(port->dev,
  3162. "Tx stop timed out, status=0x%08x\n",
  3163. reg_data);
  3164. break;
  3165. }
  3166. mdelay(1);
  3167. delay++;
  3168. /* Check port TX Command register that all
  3169. * Tx queues are stopped
  3170. */
  3171. reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
  3172. } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
  3173. }
  3174. /* Rx descriptors helper methods */
  3175. /* Get number of Rx descriptors occupied by received packets */
  3176. static inline int
  3177. mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
  3178. {
  3179. u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
  3180. return val & MVPP2_RXQ_OCCUPIED_MASK;
  3181. }
  3182. /* Update Rx queue status with the number of occupied and available
  3183. * Rx descriptor slots.
  3184. */
  3185. static inline void
  3186. mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
  3187. int used_count, int free_count)
  3188. {
  3189. /* Decrement the number of used descriptors and increment count
  3190. * increment the number of free descriptors.
  3191. */
  3192. u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
  3193. mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
  3194. }
  3195. /* Get pointer to next RX descriptor to be processed by SW */
  3196. static inline struct mvpp2_rx_desc *
  3197. mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
  3198. {
  3199. int rx_desc = rxq->next_desc_to_proc;
  3200. rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
  3201. prefetch(rxq->descs + rxq->next_desc_to_proc);
  3202. return rxq->descs + rx_desc;
  3203. }
  3204. /* Set rx queue offset */
  3205. static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
  3206. int prxq, int offset)
  3207. {
  3208. u32 val;
  3209. /* Convert offset from bytes to units of 32 bytes */
  3210. offset = offset >> 5;
  3211. val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
  3212. val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
  3213. /* Offset is in */
  3214. val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
  3215. MVPP2_RXQ_PACKET_OFFSET_MASK);
  3216. mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
  3217. }
  3218. /* Obtain BM cookie information from descriptor */
  3219. static u32 mvpp2_bm_cookie_build(struct mvpp2_port *port,
  3220. struct mvpp2_rx_desc *rx_desc)
  3221. {
  3222. int cpu = smp_processor_id();
  3223. int pool;
  3224. pool = (mvpp2_rxdesc_status_get(port, rx_desc) &
  3225. MVPP2_RXD_BM_POOL_ID_MASK) >>
  3226. MVPP2_RXD_BM_POOL_ID_OFFS;
  3227. return ((pool & 0xFF) << MVPP2_BM_COOKIE_POOL_OFFS) |
  3228. ((cpu & 0xFF) << MVPP2_BM_COOKIE_CPU_OFFS);
  3229. }
  3230. /* Tx descriptors helper methods */
  3231. /* Get number of Tx descriptors waiting to be transmitted by HW */
  3232. static int mvpp2_txq_pend_desc_num_get(struct mvpp2_port *port,
  3233. struct mvpp2_tx_queue *txq)
  3234. {
  3235. u32 val;
  3236. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  3237. val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
  3238. return val & MVPP2_TXQ_PENDING_MASK;
  3239. }
  3240. /* Get pointer to next Tx descriptor to be processed (send) by HW */
  3241. static struct mvpp2_tx_desc *
  3242. mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
  3243. {
  3244. int tx_desc = txq->next_desc_to_proc;
  3245. txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
  3246. return txq->descs + tx_desc;
  3247. }
  3248. /* Update HW with number of aggregated Tx descriptors to be sent */
  3249. static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
  3250. {
  3251. /* aggregated access - relevant TXQ number is written in TX desc */
  3252. mvpp2_write(port->priv, MVPP2_AGGR_TXQ_UPDATE_REG, pending);
  3253. }
  3254. /* Get number of sent descriptors and decrement counter.
  3255. * The number of sent descriptors is returned.
  3256. * Per-CPU access
  3257. */
  3258. static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
  3259. struct mvpp2_tx_queue *txq)
  3260. {
  3261. u32 val;
  3262. /* Reading status reg resets transmitted descriptor counter */
  3263. val = mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(txq->id));
  3264. return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
  3265. MVPP2_TRANSMITTED_COUNT_OFFSET;
  3266. }
  3267. static void mvpp2_txq_sent_counter_clear(void *arg)
  3268. {
  3269. struct mvpp2_port *port = arg;
  3270. int queue;
  3271. for (queue = 0; queue < txq_number; queue++) {
  3272. int id = port->txqs[queue]->id;
  3273. mvpp2_read(port->priv, MVPP2_TXQ_SENT_REG(id));
  3274. }
  3275. }
  3276. /* Set max sizes for Tx queues */
  3277. static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
  3278. {
  3279. u32 val, size, mtu;
  3280. int txq, tx_port_num;
  3281. mtu = port->pkt_size * 8;
  3282. if (mtu > MVPP2_TXP_MTU_MAX)
  3283. mtu = MVPP2_TXP_MTU_MAX;
  3284. /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
  3285. mtu = 3 * mtu;
  3286. /* Indirect access to registers */
  3287. tx_port_num = mvpp2_egress_port(port);
  3288. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  3289. /* Set MTU */
  3290. val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
  3291. val &= ~MVPP2_TXP_MTU_MAX;
  3292. val |= mtu;
  3293. mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
  3294. /* TXP token size and all TXQs token size must be larger that MTU */
  3295. val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
  3296. size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
  3297. if (size < mtu) {
  3298. size = mtu;
  3299. val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
  3300. val |= size;
  3301. mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
  3302. }
  3303. for (txq = 0; txq < txq_number; txq++) {
  3304. val = mvpp2_read(port->priv,
  3305. MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
  3306. size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
  3307. if (size < mtu) {
  3308. size = mtu;
  3309. val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
  3310. val |= size;
  3311. mvpp2_write(port->priv,
  3312. MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
  3313. val);
  3314. }
  3315. }
  3316. }
  3317. /* Free Tx queue skbuffs */
  3318. static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
  3319. struct mvpp2_tx_queue *txq,
  3320. struct mvpp2_txq_pcpu *txq_pcpu, int num)
  3321. {
  3322. int i;
  3323. for (i = 0; i < num; i++)
  3324. mvpp2_txq_inc_get(txq_pcpu);
  3325. }
  3326. static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
  3327. u32 cause)
  3328. {
  3329. int queue = fls(cause) - 1;
  3330. return port->rxqs[queue];
  3331. }
  3332. static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
  3333. u32 cause)
  3334. {
  3335. int queue = fls(cause) - 1;
  3336. return port->txqs[queue];
  3337. }
  3338. /* Rx/Tx queue initialization/cleanup methods */
  3339. /* Allocate and initialize descriptors for aggr TXQ */
  3340. static int mvpp2_aggr_txq_init(struct udevice *dev,
  3341. struct mvpp2_tx_queue *aggr_txq,
  3342. int desc_num, int cpu,
  3343. struct mvpp2 *priv)
  3344. {
  3345. u32 txq_dma;
  3346. /* Allocate memory for TX descriptors */
  3347. aggr_txq->descs = buffer_loc.aggr_tx_descs;
  3348. aggr_txq->descs_dma = (dma_addr_t)buffer_loc.aggr_tx_descs;
  3349. if (!aggr_txq->descs)
  3350. return -ENOMEM;
  3351. /* Make sure descriptor address is cache line size aligned */
  3352. BUG_ON(aggr_txq->descs !=
  3353. PTR_ALIGN(aggr_txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
  3354. aggr_txq->last_desc = aggr_txq->size - 1;
  3355. /* Aggr TXQ no reset WA */
  3356. aggr_txq->next_desc_to_proc = mvpp2_read(priv,
  3357. MVPP2_AGGR_TXQ_INDEX_REG(cpu));
  3358. /* Set Tx descriptors queue starting address indirect
  3359. * access
  3360. */
  3361. if (priv->hw_version == MVPP21)
  3362. txq_dma = aggr_txq->descs_dma;
  3363. else
  3364. txq_dma = aggr_txq->descs_dma >>
  3365. MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
  3366. mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
  3367. mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
  3368. return 0;
  3369. }
  3370. /* Create a specified Rx queue */
  3371. static int mvpp2_rxq_init(struct mvpp2_port *port,
  3372. struct mvpp2_rx_queue *rxq)
  3373. {
  3374. u32 rxq_dma;
  3375. rxq->size = port->rx_ring_size;
  3376. /* Allocate memory for RX descriptors */
  3377. rxq->descs = buffer_loc.rx_descs;
  3378. rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
  3379. if (!rxq->descs)
  3380. return -ENOMEM;
  3381. BUG_ON(rxq->descs !=
  3382. PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
  3383. rxq->last_desc = rxq->size - 1;
  3384. /* Zero occupied and non-occupied counters - direct access */
  3385. mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
  3386. /* Set Rx descriptors queue starting address - indirect access */
  3387. mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
  3388. if (port->priv->hw_version == MVPP21)
  3389. rxq_dma = rxq->descs_dma;
  3390. else
  3391. rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
  3392. mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
  3393. mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
  3394. mvpp2_write(port->priv, MVPP2_RXQ_INDEX_REG, 0);
  3395. /* Set Offset */
  3396. mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
  3397. /* Add number of descriptors ready for receiving packets */
  3398. mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
  3399. return 0;
  3400. }
  3401. /* Push packets received by the RXQ to BM pool */
  3402. static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
  3403. struct mvpp2_rx_queue *rxq)
  3404. {
  3405. int rx_received, i;
  3406. rx_received = mvpp2_rxq_received(port, rxq->id);
  3407. if (!rx_received)
  3408. return;
  3409. for (i = 0; i < rx_received; i++) {
  3410. struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
  3411. u32 bm = mvpp2_bm_cookie_build(port, rx_desc);
  3412. mvpp2_pool_refill(port, bm,
  3413. mvpp2_rxdesc_dma_addr_get(port, rx_desc),
  3414. mvpp2_rxdesc_cookie_get(port, rx_desc));
  3415. }
  3416. mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
  3417. }
  3418. /* Cleanup Rx queue */
  3419. static void mvpp2_rxq_deinit(struct mvpp2_port *port,
  3420. struct mvpp2_rx_queue *rxq)
  3421. {
  3422. mvpp2_rxq_drop_pkts(port, rxq);
  3423. rxq->descs = NULL;
  3424. rxq->last_desc = 0;
  3425. rxq->next_desc_to_proc = 0;
  3426. rxq->descs_dma = 0;
  3427. /* Clear Rx descriptors queue starting address and size;
  3428. * free descriptor number
  3429. */
  3430. mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
  3431. mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
  3432. mvpp2_write(port->priv, MVPP2_RXQ_DESC_ADDR_REG, 0);
  3433. mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, 0);
  3434. }
  3435. /* Create and initialize a Tx queue */
  3436. static int mvpp2_txq_init(struct mvpp2_port *port,
  3437. struct mvpp2_tx_queue *txq)
  3438. {
  3439. u32 val;
  3440. int cpu, desc, desc_per_txq, tx_port_num;
  3441. struct mvpp2_txq_pcpu *txq_pcpu;
  3442. txq->size = port->tx_ring_size;
  3443. /* Allocate memory for Tx descriptors */
  3444. txq->descs = buffer_loc.tx_descs;
  3445. txq->descs_dma = (dma_addr_t)buffer_loc.tx_descs;
  3446. if (!txq->descs)
  3447. return -ENOMEM;
  3448. /* Make sure descriptor address is cache line size aligned */
  3449. BUG_ON(txq->descs !=
  3450. PTR_ALIGN(txq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
  3451. txq->last_desc = txq->size - 1;
  3452. /* Set Tx descriptors queue starting address - indirect access */
  3453. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  3454. mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, txq->descs_dma);
  3455. mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, txq->size &
  3456. MVPP2_TXQ_DESC_SIZE_MASK);
  3457. mvpp2_write(port->priv, MVPP2_TXQ_INDEX_REG, 0);
  3458. mvpp2_write(port->priv, MVPP2_TXQ_RSVD_CLR_REG,
  3459. txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
  3460. val = mvpp2_read(port->priv, MVPP2_TXQ_PENDING_REG);
  3461. val &= ~MVPP2_TXQ_PENDING_MASK;
  3462. mvpp2_write(port->priv, MVPP2_TXQ_PENDING_REG, val);
  3463. /* Calculate base address in prefetch buffer. We reserve 16 descriptors
  3464. * for each existing TXQ.
  3465. * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
  3466. * GBE ports assumed to be continious from 0 to MVPP2_MAX_PORTS
  3467. */
  3468. desc_per_txq = 16;
  3469. desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
  3470. (txq->log_id * desc_per_txq);
  3471. mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG,
  3472. MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
  3473. MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
  3474. /* WRR / EJP configuration - indirect access */
  3475. tx_port_num = mvpp2_egress_port(port);
  3476. mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
  3477. val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
  3478. val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
  3479. val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
  3480. val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
  3481. mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
  3482. val = MVPP2_TXQ_TOKEN_SIZE_MAX;
  3483. mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
  3484. val);
  3485. for_each_present_cpu(cpu) {
  3486. txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
  3487. txq_pcpu->size = txq->size;
  3488. }
  3489. return 0;
  3490. }
  3491. /* Free allocated TXQ resources */
  3492. static void mvpp2_txq_deinit(struct mvpp2_port *port,
  3493. struct mvpp2_tx_queue *txq)
  3494. {
  3495. txq->descs = NULL;
  3496. txq->last_desc = 0;
  3497. txq->next_desc_to_proc = 0;
  3498. txq->descs_dma = 0;
  3499. /* Set minimum bandwidth for disabled TXQs */
  3500. mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
  3501. /* Set Tx descriptors queue starting address and size */
  3502. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  3503. mvpp2_write(port->priv, MVPP2_TXQ_DESC_ADDR_REG, 0);
  3504. mvpp2_write(port->priv, MVPP2_TXQ_DESC_SIZE_REG, 0);
  3505. }
  3506. /* Cleanup Tx ports */
  3507. static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
  3508. {
  3509. struct mvpp2_txq_pcpu *txq_pcpu;
  3510. int delay, pending, cpu;
  3511. u32 val;
  3512. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  3513. val = mvpp2_read(port->priv, MVPP2_TXQ_PREF_BUF_REG);
  3514. val |= MVPP2_TXQ_DRAIN_EN_MASK;
  3515. mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
  3516. /* The napi queue has been stopped so wait for all packets
  3517. * to be transmitted.
  3518. */
  3519. delay = 0;
  3520. do {
  3521. if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
  3522. netdev_warn(port->dev,
  3523. "port %d: cleaning queue %d timed out\n",
  3524. port->id, txq->log_id);
  3525. break;
  3526. }
  3527. mdelay(1);
  3528. delay++;
  3529. pending = mvpp2_txq_pend_desc_num_get(port, txq);
  3530. } while (pending);
  3531. val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
  3532. mvpp2_write(port->priv, MVPP2_TXQ_PREF_BUF_REG, val);
  3533. for_each_present_cpu(cpu) {
  3534. txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
  3535. /* Release all packets */
  3536. mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
  3537. /* Reset queue */
  3538. txq_pcpu->count = 0;
  3539. txq_pcpu->txq_put_index = 0;
  3540. txq_pcpu->txq_get_index = 0;
  3541. }
  3542. }
  3543. /* Cleanup all Tx queues */
  3544. static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
  3545. {
  3546. struct mvpp2_tx_queue *txq;
  3547. int queue;
  3548. u32 val;
  3549. val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
  3550. /* Reset Tx ports and delete Tx queues */
  3551. val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
  3552. mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
  3553. for (queue = 0; queue < txq_number; queue++) {
  3554. txq = port->txqs[queue];
  3555. mvpp2_txq_clean(port, txq);
  3556. mvpp2_txq_deinit(port, txq);
  3557. }
  3558. mvpp2_txq_sent_counter_clear(port);
  3559. val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
  3560. mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
  3561. }
  3562. /* Cleanup all Rx queues */
  3563. static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
  3564. {
  3565. int queue;
  3566. for (queue = 0; queue < rxq_number; queue++)
  3567. mvpp2_rxq_deinit(port, port->rxqs[queue]);
  3568. }
  3569. /* Init all Rx queues for port */
  3570. static int mvpp2_setup_rxqs(struct mvpp2_port *port)
  3571. {
  3572. int queue, err;
  3573. for (queue = 0; queue < rxq_number; queue++) {
  3574. err = mvpp2_rxq_init(port, port->rxqs[queue]);
  3575. if (err)
  3576. goto err_cleanup;
  3577. }
  3578. return 0;
  3579. err_cleanup:
  3580. mvpp2_cleanup_rxqs(port);
  3581. return err;
  3582. }
  3583. /* Init all tx queues for port */
  3584. static int mvpp2_setup_txqs(struct mvpp2_port *port)
  3585. {
  3586. struct mvpp2_tx_queue *txq;
  3587. int queue, err;
  3588. for (queue = 0; queue < txq_number; queue++) {
  3589. txq = port->txqs[queue];
  3590. err = mvpp2_txq_init(port, txq);
  3591. if (err)
  3592. goto err_cleanup;
  3593. }
  3594. mvpp2_txq_sent_counter_clear(port);
  3595. return 0;
  3596. err_cleanup:
  3597. mvpp2_cleanup_txqs(port);
  3598. return err;
  3599. }
  3600. /* Adjust link */
  3601. static void mvpp2_link_event(struct mvpp2_port *port)
  3602. {
  3603. struct phy_device *phydev = port->phy_dev;
  3604. int status_change = 0;
  3605. u32 val;
  3606. if (phydev->link) {
  3607. if ((port->speed != phydev->speed) ||
  3608. (port->duplex != phydev->duplex)) {
  3609. u32 val;
  3610. val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  3611. val &= ~(MVPP2_GMAC_CONFIG_MII_SPEED |
  3612. MVPP2_GMAC_CONFIG_GMII_SPEED |
  3613. MVPP2_GMAC_CONFIG_FULL_DUPLEX |
  3614. MVPP2_GMAC_AN_SPEED_EN |
  3615. MVPP2_GMAC_AN_DUPLEX_EN);
  3616. if (phydev->duplex)
  3617. val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
  3618. if (phydev->speed == SPEED_1000)
  3619. val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
  3620. else if (phydev->speed == SPEED_100)
  3621. val |= MVPP2_GMAC_CONFIG_MII_SPEED;
  3622. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  3623. port->duplex = phydev->duplex;
  3624. port->speed = phydev->speed;
  3625. }
  3626. }
  3627. if (phydev->link != port->link) {
  3628. if (!phydev->link) {
  3629. port->duplex = -1;
  3630. port->speed = 0;
  3631. }
  3632. port->link = phydev->link;
  3633. status_change = 1;
  3634. }
  3635. if (status_change) {
  3636. if (phydev->link) {
  3637. val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  3638. val |= (MVPP2_GMAC_FORCE_LINK_PASS |
  3639. MVPP2_GMAC_FORCE_LINK_DOWN);
  3640. writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
  3641. mvpp2_egress_enable(port);
  3642. mvpp2_ingress_enable(port);
  3643. } else {
  3644. mvpp2_ingress_disable(port);
  3645. mvpp2_egress_disable(port);
  3646. }
  3647. }
  3648. }
  3649. /* Main RX/TX processing routines */
  3650. /* Display more error info */
  3651. static void mvpp2_rx_error(struct mvpp2_port *port,
  3652. struct mvpp2_rx_desc *rx_desc)
  3653. {
  3654. u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
  3655. size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
  3656. switch (status & MVPP2_RXD_ERR_CODE_MASK) {
  3657. case MVPP2_RXD_ERR_CRC:
  3658. netdev_err(port->dev, "bad rx status %08x (crc error), size=%zu\n",
  3659. status, sz);
  3660. break;
  3661. case MVPP2_RXD_ERR_OVERRUN:
  3662. netdev_err(port->dev, "bad rx status %08x (overrun error), size=%zu\n",
  3663. status, sz);
  3664. break;
  3665. case MVPP2_RXD_ERR_RESOURCE:
  3666. netdev_err(port->dev, "bad rx status %08x (resource error), size=%zu\n",
  3667. status, sz);
  3668. break;
  3669. }
  3670. }
  3671. /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
  3672. static int mvpp2_rx_refill(struct mvpp2_port *port,
  3673. struct mvpp2_bm_pool *bm_pool,
  3674. u32 bm, dma_addr_t dma_addr)
  3675. {
  3676. mvpp2_pool_refill(port, bm, dma_addr, (unsigned long)dma_addr);
  3677. return 0;
  3678. }
  3679. /* Set hw internals when starting port */
  3680. static void mvpp2_start_dev(struct mvpp2_port *port)
  3681. {
  3682. switch (port->phy_interface) {
  3683. case PHY_INTERFACE_MODE_RGMII:
  3684. case PHY_INTERFACE_MODE_RGMII_ID:
  3685. case PHY_INTERFACE_MODE_SGMII:
  3686. mvpp2_gmac_max_rx_size_set(port);
  3687. default:
  3688. break;
  3689. }
  3690. mvpp2_txp_max_tx_size_set(port);
  3691. if (port->priv->hw_version == MVPP21)
  3692. mvpp2_port_enable(port);
  3693. else
  3694. gop_port_enable(port, 1);
  3695. }
  3696. /* Set hw internals when stopping port */
  3697. static void mvpp2_stop_dev(struct mvpp2_port *port)
  3698. {
  3699. /* Stop new packets from arriving to RXQs */
  3700. mvpp2_ingress_disable(port);
  3701. mvpp2_egress_disable(port);
  3702. if (port->priv->hw_version == MVPP21)
  3703. mvpp2_port_disable(port);
  3704. else
  3705. gop_port_enable(port, 0);
  3706. }
  3707. static int mvpp2_phy_connect(struct udevice *dev, struct mvpp2_port *port)
  3708. {
  3709. struct phy_device *phy_dev;
  3710. if (!port->init || port->link == 0) {
  3711. phy_dev = phy_connect(port->bus, port->phyaddr, dev,
  3712. port->phy_interface);
  3713. port->phy_dev = phy_dev;
  3714. if (!phy_dev) {
  3715. netdev_err(port->dev, "cannot connect to phy\n");
  3716. return -ENODEV;
  3717. }
  3718. phy_dev->supported &= PHY_GBIT_FEATURES;
  3719. phy_dev->advertising = phy_dev->supported;
  3720. port->phy_dev = phy_dev;
  3721. port->link = 0;
  3722. port->duplex = 0;
  3723. port->speed = 0;
  3724. phy_config(phy_dev);
  3725. phy_startup(phy_dev);
  3726. if (!phy_dev->link) {
  3727. printf("%s: No link\n", phy_dev->dev->name);
  3728. return -1;
  3729. }
  3730. port->init = 1;
  3731. } else {
  3732. mvpp2_egress_enable(port);
  3733. mvpp2_ingress_enable(port);
  3734. }
  3735. return 0;
  3736. }
  3737. static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
  3738. {
  3739. unsigned char mac_bcast[ETH_ALEN] = {
  3740. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
  3741. int err;
  3742. err = mvpp2_prs_mac_da_accept(port->priv, port->id, mac_bcast, true);
  3743. if (err) {
  3744. netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
  3745. return err;
  3746. }
  3747. err = mvpp2_prs_mac_da_accept(port->priv, port->id,
  3748. port->dev_addr, true);
  3749. if (err) {
  3750. netdev_err(dev, "mvpp2_prs_mac_da_accept MC failed\n");
  3751. return err;
  3752. }
  3753. err = mvpp2_prs_def_flow(port);
  3754. if (err) {
  3755. netdev_err(dev, "mvpp2_prs_def_flow failed\n");
  3756. return err;
  3757. }
  3758. /* Allocate the Rx/Tx queues */
  3759. err = mvpp2_setup_rxqs(port);
  3760. if (err) {
  3761. netdev_err(port->dev, "cannot allocate Rx queues\n");
  3762. return err;
  3763. }
  3764. err = mvpp2_setup_txqs(port);
  3765. if (err) {
  3766. netdev_err(port->dev, "cannot allocate Tx queues\n");
  3767. return err;
  3768. }
  3769. if (port->phy_node) {
  3770. err = mvpp2_phy_connect(dev, port);
  3771. if (err < 0)
  3772. return err;
  3773. mvpp2_link_event(port);
  3774. } else {
  3775. mvpp2_egress_enable(port);
  3776. mvpp2_ingress_enable(port);
  3777. }
  3778. mvpp2_start_dev(port);
  3779. return 0;
  3780. }
  3781. /* No Device ops here in U-Boot */
  3782. /* Driver initialization */
  3783. static void mvpp2_port_power_up(struct mvpp2_port *port)
  3784. {
  3785. struct mvpp2 *priv = port->priv;
  3786. /* On PPv2.2 the GoP / interface configuration has already been done */
  3787. if (priv->hw_version == MVPP21)
  3788. mvpp2_port_mii_set(port);
  3789. mvpp2_port_periodic_xon_disable(port);
  3790. if (priv->hw_version == MVPP21)
  3791. mvpp2_port_fc_adv_enable(port);
  3792. mvpp2_port_reset(port);
  3793. }
  3794. /* Initialize port HW */
  3795. static int mvpp2_port_init(struct udevice *dev, struct mvpp2_port *port)
  3796. {
  3797. struct mvpp2 *priv = port->priv;
  3798. struct mvpp2_txq_pcpu *txq_pcpu;
  3799. int queue, cpu, err;
  3800. if (port->first_rxq + rxq_number >
  3801. MVPP2_MAX_PORTS * priv->max_port_rxqs)
  3802. return -EINVAL;
  3803. /* Disable port */
  3804. mvpp2_egress_disable(port);
  3805. if (priv->hw_version == MVPP21)
  3806. mvpp2_port_disable(port);
  3807. else
  3808. gop_port_enable(port, 0);
  3809. port->txqs = devm_kcalloc(dev, txq_number, sizeof(*port->txqs),
  3810. GFP_KERNEL);
  3811. if (!port->txqs)
  3812. return -ENOMEM;
  3813. /* Associate physical Tx queues to this port and initialize.
  3814. * The mapping is predefined.
  3815. */
  3816. for (queue = 0; queue < txq_number; queue++) {
  3817. int queue_phy_id = mvpp2_txq_phys(port->id, queue);
  3818. struct mvpp2_tx_queue *txq;
  3819. txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
  3820. if (!txq)
  3821. return -ENOMEM;
  3822. txq->pcpu = devm_kzalloc(dev, sizeof(struct mvpp2_txq_pcpu),
  3823. GFP_KERNEL);
  3824. if (!txq->pcpu)
  3825. return -ENOMEM;
  3826. txq->id = queue_phy_id;
  3827. txq->log_id = queue;
  3828. txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
  3829. for_each_present_cpu(cpu) {
  3830. txq_pcpu = per_cpu_ptr(txq->pcpu, cpu);
  3831. txq_pcpu->cpu = cpu;
  3832. }
  3833. port->txqs[queue] = txq;
  3834. }
  3835. port->rxqs = devm_kcalloc(dev, rxq_number, sizeof(*port->rxqs),
  3836. GFP_KERNEL);
  3837. if (!port->rxqs)
  3838. return -ENOMEM;
  3839. /* Allocate and initialize Rx queue for this port */
  3840. for (queue = 0; queue < rxq_number; queue++) {
  3841. struct mvpp2_rx_queue *rxq;
  3842. /* Map physical Rx queue to port's logical Rx queue */
  3843. rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
  3844. if (!rxq)
  3845. return -ENOMEM;
  3846. /* Map this Rx queue to a physical queue */
  3847. rxq->id = port->first_rxq + queue;
  3848. rxq->port = port->id;
  3849. rxq->logic_rxq = queue;
  3850. port->rxqs[queue] = rxq;
  3851. }
  3852. /* Create Rx descriptor rings */
  3853. for (queue = 0; queue < rxq_number; queue++) {
  3854. struct mvpp2_rx_queue *rxq = port->rxqs[queue];
  3855. rxq->size = port->rx_ring_size;
  3856. rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
  3857. rxq->time_coal = MVPP2_RX_COAL_USEC;
  3858. }
  3859. mvpp2_ingress_disable(port);
  3860. /* Port default configuration */
  3861. mvpp2_defaults_set(port);
  3862. /* Port's classifier configuration */
  3863. mvpp2_cls_oversize_rxq_set(port);
  3864. mvpp2_cls_port_config(port);
  3865. /* Provide an initial Rx packet size */
  3866. port->pkt_size = MVPP2_RX_PKT_SIZE(PKTSIZE_ALIGN);
  3867. /* Initialize pools for swf */
  3868. err = mvpp2_swf_bm_pool_init(port);
  3869. if (err)
  3870. return err;
  3871. return 0;
  3872. }
  3873. static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
  3874. {
  3875. int port_node = dev_of_offset(dev);
  3876. const char *phy_mode_str;
  3877. int phy_node;
  3878. u32 id;
  3879. u32 phyaddr = 0;
  3880. int phy_mode = -1;
  3881. /* Default mdio_base from the same eth base */
  3882. if (port->priv->hw_version == MVPP21)
  3883. port->mdio_base = port->priv->lms_base + MVPP21_SMI;
  3884. else
  3885. port->mdio_base = port->priv->iface_base + MVPP22_SMI;
  3886. phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
  3887. if (phy_node > 0) {
  3888. ofnode phy_ofnode;
  3889. fdt_addr_t phy_base;
  3890. phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
  3891. if (phyaddr < 0) {
  3892. dev_err(&pdev->dev, "could not find phy address\n");
  3893. return -1;
  3894. }
  3895. phy_ofnode = ofnode_get_parent(offset_to_ofnode(phy_node));
  3896. phy_base = ofnode_get_addr(phy_ofnode);
  3897. port->mdio_base = (void *)phy_base;
  3898. if (port->mdio_base < 0) {
  3899. dev_err(&pdev->dev, "could not find mdio base address\n");
  3900. return -1;
  3901. }
  3902. } else {
  3903. phy_node = 0;
  3904. }
  3905. phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
  3906. if (phy_mode_str)
  3907. phy_mode = phy_get_interface_by_name(phy_mode_str);
  3908. if (phy_mode == -1) {
  3909. dev_err(&pdev->dev, "incorrect phy mode\n");
  3910. return -EINVAL;
  3911. }
  3912. id = fdtdec_get_int(gd->fdt_blob, port_node, "port-id", -1);
  3913. if (id == -1) {
  3914. dev_err(&pdev->dev, "missing port-id value\n");
  3915. return -EINVAL;
  3916. }
  3917. #ifdef CONFIG_DM_GPIO
  3918. gpio_request_by_name(dev, "phy-reset-gpios", 0,
  3919. &port->phy_reset_gpio, GPIOD_IS_OUT);
  3920. gpio_request_by_name(dev, "marvell,sfp-tx-disable-gpio", 0,
  3921. &port->phy_tx_disable_gpio, GPIOD_IS_OUT);
  3922. #endif
  3923. /*
  3924. * ToDo:
  3925. * Not sure if this DT property "phy-speed" will get accepted, so
  3926. * this might change later
  3927. */
  3928. /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */
  3929. port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
  3930. "phy-speed", 1000);
  3931. port->id = id;
  3932. if (port->priv->hw_version == MVPP21)
  3933. port->first_rxq = port->id * rxq_number;
  3934. else
  3935. port->first_rxq = port->id * port->priv->max_port_rxqs;
  3936. port->phy_node = phy_node;
  3937. port->phy_interface = phy_mode;
  3938. port->phyaddr = phyaddr;
  3939. return 0;
  3940. }
  3941. #ifdef CONFIG_DM_GPIO
  3942. /* Port GPIO initialization */
  3943. static void mvpp2_gpio_init(struct mvpp2_port *port)
  3944. {
  3945. if (dm_gpio_is_valid(&port->phy_reset_gpio)) {
  3946. dm_gpio_set_value(&port->phy_reset_gpio, 1);
  3947. mdelay(10);
  3948. dm_gpio_set_value(&port->phy_reset_gpio, 0);
  3949. }
  3950. if (dm_gpio_is_valid(&port->phy_tx_disable_gpio))
  3951. dm_gpio_set_value(&port->phy_tx_disable_gpio, 0);
  3952. }
  3953. #endif
  3954. /* Ports initialization */
  3955. static int mvpp2_port_probe(struct udevice *dev,
  3956. struct mvpp2_port *port,
  3957. int port_node,
  3958. struct mvpp2 *priv)
  3959. {
  3960. int err;
  3961. port->tx_ring_size = MVPP2_MAX_TXD;
  3962. port->rx_ring_size = MVPP2_MAX_RXD;
  3963. err = mvpp2_port_init(dev, port);
  3964. if (err < 0) {
  3965. dev_err(&pdev->dev, "failed to init port %d\n", port->id);
  3966. return err;
  3967. }
  3968. mvpp2_port_power_up(port);
  3969. #ifdef CONFIG_DM_GPIO
  3970. mvpp2_gpio_init(port);
  3971. #endif
  3972. priv->port_list[port->id] = port;
  3973. priv->num_ports++;
  3974. return 0;
  3975. }
  3976. /* Initialize decoding windows */
  3977. static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
  3978. struct mvpp2 *priv)
  3979. {
  3980. u32 win_enable;
  3981. int i;
  3982. for (i = 0; i < 6; i++) {
  3983. mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
  3984. mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
  3985. if (i < 4)
  3986. mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
  3987. }
  3988. win_enable = 0;
  3989. for (i = 0; i < dram->num_cs; i++) {
  3990. const struct mbus_dram_window *cs = dram->cs + i;
  3991. mvpp2_write(priv, MVPP2_WIN_BASE(i),
  3992. (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
  3993. dram->mbus_dram_target_id);
  3994. mvpp2_write(priv, MVPP2_WIN_SIZE(i),
  3995. (cs->size - 1) & 0xffff0000);
  3996. win_enable |= (1 << i);
  3997. }
  3998. mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
  3999. }
  4000. /* Initialize Rx FIFO's */
  4001. static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
  4002. {
  4003. int port;
  4004. for (port = 0; port < MVPP2_MAX_PORTS; port++) {
  4005. if (priv->hw_version == MVPP22) {
  4006. if (port == 0) {
  4007. mvpp2_write(priv,
  4008. MVPP2_RX_DATA_FIFO_SIZE_REG(port),
  4009. MVPP22_RX_FIFO_10GB_PORT_DATA_SIZE);
  4010. mvpp2_write(priv,
  4011. MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
  4012. MVPP22_RX_FIFO_10GB_PORT_ATTR_SIZE);
  4013. } else if (port == 1) {
  4014. mvpp2_write(priv,
  4015. MVPP2_RX_DATA_FIFO_SIZE_REG(port),
  4016. MVPP22_RX_FIFO_2_5GB_PORT_DATA_SIZE);
  4017. mvpp2_write(priv,
  4018. MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
  4019. MVPP22_RX_FIFO_2_5GB_PORT_ATTR_SIZE);
  4020. } else {
  4021. mvpp2_write(priv,
  4022. MVPP2_RX_DATA_FIFO_SIZE_REG(port),
  4023. MVPP22_RX_FIFO_1GB_PORT_DATA_SIZE);
  4024. mvpp2_write(priv,
  4025. MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
  4026. MVPP22_RX_FIFO_1GB_PORT_ATTR_SIZE);
  4027. }
  4028. } else {
  4029. mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
  4030. MVPP21_RX_FIFO_PORT_DATA_SIZE);
  4031. mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
  4032. MVPP21_RX_FIFO_PORT_ATTR_SIZE);
  4033. }
  4034. }
  4035. mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
  4036. MVPP2_RX_FIFO_PORT_MIN_PKT);
  4037. mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
  4038. }
  4039. /* Initialize Tx FIFO's */
  4040. static void mvpp2_tx_fifo_init(struct mvpp2 *priv)
  4041. {
  4042. int port, val;
  4043. for (port = 0; port < MVPP2_MAX_PORTS; port++) {
  4044. /* Port 0 supports 10KB TX FIFO */
  4045. if (port == 0) {
  4046. val = MVPP2_TX_FIFO_DATA_SIZE_10KB &
  4047. MVPP22_TX_FIFO_SIZE_MASK;
  4048. } else {
  4049. val = MVPP2_TX_FIFO_DATA_SIZE_3KB &
  4050. MVPP22_TX_FIFO_SIZE_MASK;
  4051. }
  4052. mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), val);
  4053. }
  4054. }
  4055. static void mvpp2_axi_init(struct mvpp2 *priv)
  4056. {
  4057. u32 val, rdval, wrval;
  4058. mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
  4059. /* AXI Bridge Configuration */
  4060. rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
  4061. << MVPP22_AXI_ATTR_CACHE_OFFS;
  4062. rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
  4063. << MVPP22_AXI_ATTR_DOMAIN_OFFS;
  4064. wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
  4065. << MVPP22_AXI_ATTR_CACHE_OFFS;
  4066. wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
  4067. << MVPP22_AXI_ATTR_DOMAIN_OFFS;
  4068. /* BM */
  4069. mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
  4070. mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
  4071. /* Descriptors */
  4072. mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
  4073. mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
  4074. mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
  4075. mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
  4076. /* Buffer Data */
  4077. mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
  4078. mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
  4079. val = MVPP22_AXI_CODE_CACHE_NON_CACHE
  4080. << MVPP22_AXI_CODE_CACHE_OFFS;
  4081. val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
  4082. << MVPP22_AXI_CODE_DOMAIN_OFFS;
  4083. mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
  4084. mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
  4085. val = MVPP22_AXI_CODE_CACHE_RD_CACHE
  4086. << MVPP22_AXI_CODE_CACHE_OFFS;
  4087. val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
  4088. << MVPP22_AXI_CODE_DOMAIN_OFFS;
  4089. mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
  4090. val = MVPP22_AXI_CODE_CACHE_WR_CACHE
  4091. << MVPP22_AXI_CODE_CACHE_OFFS;
  4092. val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
  4093. << MVPP22_AXI_CODE_DOMAIN_OFFS;
  4094. mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
  4095. }
  4096. /* Initialize network controller common part HW */
  4097. static int mvpp2_init(struct udevice *dev, struct mvpp2 *priv)
  4098. {
  4099. const struct mbus_dram_target_info *dram_target_info;
  4100. int err, i;
  4101. u32 val;
  4102. /* Checks for hardware constraints (U-Boot uses only one rxq) */
  4103. if ((rxq_number > priv->max_port_rxqs) ||
  4104. (txq_number > MVPP2_MAX_TXQ)) {
  4105. dev_err(&pdev->dev, "invalid queue size parameter\n");
  4106. return -EINVAL;
  4107. }
  4108. if (priv->hw_version == MVPP22)
  4109. mvpp2_axi_init(priv);
  4110. else {
  4111. /* MBUS windows configuration */
  4112. dram_target_info = mvebu_mbus_dram_info();
  4113. if (dram_target_info)
  4114. mvpp2_conf_mbus_windows(dram_target_info, priv);
  4115. }
  4116. if (priv->hw_version == MVPP21) {
  4117. /* Disable HW PHY polling */
  4118. val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
  4119. val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
  4120. writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
  4121. } else {
  4122. /* Enable HW PHY polling */
  4123. val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
  4124. val |= MVPP22_SMI_POLLING_EN;
  4125. writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
  4126. }
  4127. /* Allocate and initialize aggregated TXQs */
  4128. priv->aggr_txqs = devm_kcalloc(dev, num_present_cpus(),
  4129. sizeof(struct mvpp2_tx_queue),
  4130. GFP_KERNEL);
  4131. if (!priv->aggr_txqs)
  4132. return -ENOMEM;
  4133. for_each_present_cpu(i) {
  4134. priv->aggr_txqs[i].id = i;
  4135. priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
  4136. err = mvpp2_aggr_txq_init(dev, &priv->aggr_txqs[i],
  4137. MVPP2_AGGR_TXQ_SIZE, i, priv);
  4138. if (err < 0)
  4139. return err;
  4140. }
  4141. /* Rx Fifo Init */
  4142. mvpp2_rx_fifo_init(priv);
  4143. /* Tx Fifo Init */
  4144. if (priv->hw_version == MVPP22)
  4145. mvpp2_tx_fifo_init(priv);
  4146. if (priv->hw_version == MVPP21)
  4147. writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
  4148. priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
  4149. /* Allow cache snoop when transmiting packets */
  4150. mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
  4151. /* Buffer Manager initialization */
  4152. err = mvpp2_bm_init(dev, priv);
  4153. if (err < 0)
  4154. return err;
  4155. /* Parser default initialization */
  4156. err = mvpp2_prs_default_init(dev, priv);
  4157. if (err < 0)
  4158. return err;
  4159. /* Classifier default initialization */
  4160. mvpp2_cls_init(priv);
  4161. return 0;
  4162. }
  4163. /* SMI / MDIO functions */
  4164. static int smi_wait_ready(struct mvpp2_port *priv)
  4165. {
  4166. u32 timeout = MVPP2_SMI_TIMEOUT;
  4167. u32 smi_reg;
  4168. /* wait till the SMI is not busy */
  4169. do {
  4170. /* read smi register */
  4171. smi_reg = readl(priv->mdio_base);
  4172. if (timeout-- == 0) {
  4173. printf("Error: SMI busy timeout\n");
  4174. return -EFAULT;
  4175. }
  4176. } while (smi_reg & MVPP2_SMI_BUSY);
  4177. return 0;
  4178. }
  4179. /*
  4180. * mpp2_mdio_read - miiphy_read callback function.
  4181. *
  4182. * Returns 16bit phy register value, or 0xffff on error
  4183. */
  4184. static int mpp2_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  4185. {
  4186. struct mvpp2_port *priv = bus->priv;
  4187. u32 smi_reg;
  4188. u32 timeout;
  4189. /* check parameters */
  4190. if (addr > MVPP2_PHY_ADDR_MASK) {
  4191. printf("Error: Invalid PHY address %d\n", addr);
  4192. return -EFAULT;
  4193. }
  4194. if (reg > MVPP2_PHY_REG_MASK) {
  4195. printf("Err: Invalid register offset %d\n", reg);
  4196. return -EFAULT;
  4197. }
  4198. /* wait till the SMI is not busy */
  4199. if (smi_wait_ready(priv) < 0)
  4200. return -EFAULT;
  4201. /* fill the phy address and regiser offset and read opcode */
  4202. smi_reg = (addr << MVPP2_SMI_DEV_ADDR_OFFS)
  4203. | (reg << MVPP2_SMI_REG_ADDR_OFFS)
  4204. | MVPP2_SMI_OPCODE_READ;
  4205. /* write the smi register */
  4206. writel(smi_reg, priv->mdio_base);
  4207. /* wait till read value is ready */
  4208. timeout = MVPP2_SMI_TIMEOUT;
  4209. do {
  4210. /* read smi register */
  4211. smi_reg = readl(priv->mdio_base);
  4212. if (timeout-- == 0) {
  4213. printf("Err: SMI read ready timeout\n");
  4214. return -EFAULT;
  4215. }
  4216. } while (!(smi_reg & MVPP2_SMI_READ_VALID));
  4217. /* Wait for the data to update in the SMI register */
  4218. for (timeout = 0; timeout < MVPP2_SMI_TIMEOUT; timeout++)
  4219. ;
  4220. return readl(priv->mdio_base) & MVPP2_SMI_DATA_MASK;
  4221. }
  4222. /*
  4223. * mpp2_mdio_write - miiphy_write callback function.
  4224. *
  4225. * Returns 0 if write succeed, -EINVAL on bad parameters
  4226. * -ETIME on timeout
  4227. */
  4228. static int mpp2_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  4229. u16 value)
  4230. {
  4231. struct mvpp2_port *priv = bus->priv;
  4232. u32 smi_reg;
  4233. /* check parameters */
  4234. if (addr > MVPP2_PHY_ADDR_MASK) {
  4235. printf("Error: Invalid PHY address %d\n", addr);
  4236. return -EFAULT;
  4237. }
  4238. if (reg > MVPP2_PHY_REG_MASK) {
  4239. printf("Err: Invalid register offset %d\n", reg);
  4240. return -EFAULT;
  4241. }
  4242. /* wait till the SMI is not busy */
  4243. if (smi_wait_ready(priv) < 0)
  4244. return -EFAULT;
  4245. /* fill the phy addr and reg offset and write opcode and data */
  4246. smi_reg = value << MVPP2_SMI_DATA_OFFS;
  4247. smi_reg |= (addr << MVPP2_SMI_DEV_ADDR_OFFS)
  4248. | (reg << MVPP2_SMI_REG_ADDR_OFFS);
  4249. smi_reg &= ~MVPP2_SMI_OPCODE_READ;
  4250. /* write the smi register */
  4251. writel(smi_reg, priv->mdio_base);
  4252. return 0;
  4253. }
  4254. static int mvpp2_recv(struct udevice *dev, int flags, uchar **packetp)
  4255. {
  4256. struct mvpp2_port *port = dev_get_priv(dev);
  4257. struct mvpp2_rx_desc *rx_desc;
  4258. struct mvpp2_bm_pool *bm_pool;
  4259. dma_addr_t dma_addr;
  4260. u32 bm, rx_status;
  4261. int pool, rx_bytes, err;
  4262. int rx_received;
  4263. struct mvpp2_rx_queue *rxq;
  4264. u8 *data;
  4265. /* Process RX packets */
  4266. rxq = port->rxqs[0];
  4267. /* Get number of received packets and clamp the to-do */
  4268. rx_received = mvpp2_rxq_received(port, rxq->id);
  4269. /* Return if no packets are received */
  4270. if (!rx_received)
  4271. return 0;
  4272. rx_desc = mvpp2_rxq_next_desc_get(rxq);
  4273. rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
  4274. rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
  4275. rx_bytes -= MVPP2_MH_SIZE;
  4276. dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
  4277. bm = mvpp2_bm_cookie_build(port, rx_desc);
  4278. pool = mvpp2_bm_cookie_pool_get(bm);
  4279. bm_pool = &port->priv->bm_pools[pool];
  4280. /* In case of an error, release the requested buffer pointer
  4281. * to the Buffer Manager. This request process is controlled
  4282. * by the hardware, and the information about the buffer is
  4283. * comprised by the RX descriptor.
  4284. */
  4285. if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
  4286. mvpp2_rx_error(port, rx_desc);
  4287. /* Return the buffer to the pool */
  4288. mvpp2_pool_refill(port, bm, dma_addr, dma_addr);
  4289. return 0;
  4290. }
  4291. err = mvpp2_rx_refill(port, bm_pool, bm, dma_addr);
  4292. if (err) {
  4293. netdev_err(port->dev, "failed to refill BM pools\n");
  4294. return 0;
  4295. }
  4296. /* Update Rx queue management counters */
  4297. mb();
  4298. mvpp2_rxq_status_update(port, rxq->id, 1, 1);
  4299. /* give packet to stack - skip on first n bytes */
  4300. data = (u8 *)dma_addr + 2 + 32;
  4301. if (rx_bytes <= 0)
  4302. return 0;
  4303. /*
  4304. * No cache invalidation needed here, since the rx_buffer's are
  4305. * located in a uncached memory region
  4306. */
  4307. *packetp = data;
  4308. return rx_bytes;
  4309. }
  4310. static int mvpp2_send(struct udevice *dev, void *packet, int length)
  4311. {
  4312. struct mvpp2_port *port = dev_get_priv(dev);
  4313. struct mvpp2_tx_queue *txq, *aggr_txq;
  4314. struct mvpp2_tx_desc *tx_desc;
  4315. int tx_done;
  4316. int timeout;
  4317. txq = port->txqs[0];
  4318. aggr_txq = &port->priv->aggr_txqs[smp_processor_id()];
  4319. /* Get a descriptor for the first part of the packet */
  4320. tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
  4321. mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
  4322. mvpp2_txdesc_size_set(port, tx_desc, length);
  4323. mvpp2_txdesc_offset_set(port, tx_desc,
  4324. (dma_addr_t)packet & MVPP2_TX_DESC_ALIGN);
  4325. mvpp2_txdesc_dma_addr_set(port, tx_desc,
  4326. (dma_addr_t)packet & ~MVPP2_TX_DESC_ALIGN);
  4327. /* First and Last descriptor */
  4328. mvpp2_txdesc_cmd_set(port, tx_desc,
  4329. MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE
  4330. | MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC);
  4331. /* Flush tx data */
  4332. flush_dcache_range((unsigned long)packet,
  4333. (unsigned long)packet + ALIGN(length, PKTALIGN));
  4334. /* Enable transmit */
  4335. mb();
  4336. mvpp2_aggr_txq_pend_desc_add(port, 1);
  4337. mvpp2_write(port->priv, MVPP2_TXQ_NUM_REG, txq->id);
  4338. timeout = 0;
  4339. do {
  4340. if (timeout++ > 10000) {
  4341. printf("timeout: packet not sent from aggregated to phys TXQ\n");
  4342. return 0;
  4343. }
  4344. tx_done = mvpp2_txq_pend_desc_num_get(port, txq);
  4345. } while (tx_done);
  4346. timeout = 0;
  4347. do {
  4348. if (timeout++ > 10000) {
  4349. printf("timeout: packet not sent\n");
  4350. return 0;
  4351. }
  4352. tx_done = mvpp2_txq_sent_desc_proc(port, txq);
  4353. } while (!tx_done);
  4354. return 0;
  4355. }
  4356. static int mvpp2_start(struct udevice *dev)
  4357. {
  4358. struct eth_pdata *pdata = dev_get_platdata(dev);
  4359. struct mvpp2_port *port = dev_get_priv(dev);
  4360. /* Load current MAC address */
  4361. memcpy(port->dev_addr, pdata->enetaddr, ETH_ALEN);
  4362. /* Reconfigure parser accept the original MAC address */
  4363. mvpp2_prs_update_mac_da(port, port->dev_addr);
  4364. switch (port->phy_interface) {
  4365. case PHY_INTERFACE_MODE_RGMII:
  4366. case PHY_INTERFACE_MODE_RGMII_ID:
  4367. case PHY_INTERFACE_MODE_SGMII:
  4368. mvpp2_port_power_up(port);
  4369. default:
  4370. break;
  4371. }
  4372. mvpp2_open(dev, port);
  4373. return 0;
  4374. }
  4375. static void mvpp2_stop(struct udevice *dev)
  4376. {
  4377. struct mvpp2_port *port = dev_get_priv(dev);
  4378. mvpp2_stop_dev(port);
  4379. mvpp2_cleanup_rxqs(port);
  4380. mvpp2_cleanup_txqs(port);
  4381. }
  4382. static int mvpp2_write_hwaddr(struct udevice *dev)
  4383. {
  4384. struct mvpp2_port *port = dev_get_priv(dev);
  4385. return mvpp2_prs_update_mac_da(port, port->dev_addr);
  4386. }
  4387. static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
  4388. {
  4389. writel(port->phyaddr, port->priv->iface_base +
  4390. MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
  4391. return 0;
  4392. }
  4393. static int mvpp2_base_probe(struct udevice *dev)
  4394. {
  4395. struct mvpp2 *priv = dev_get_priv(dev);
  4396. void *bd_space;
  4397. u32 size = 0;
  4398. int i;
  4399. /* Save hw-version */
  4400. priv->hw_version = dev_get_driver_data(dev);
  4401. /*
  4402. * U-Boot special buffer handling:
  4403. *
  4404. * Allocate buffer area for descs and rx_buffers. This is only
  4405. * done once for all interfaces. As only one interface can
  4406. * be active. Make this area DMA-safe by disabling the D-cache
  4407. */
  4408. /* Align buffer area for descs and rx_buffers to 1MiB */
  4409. bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
  4410. mmu_set_region_dcache_behaviour((unsigned long)bd_space,
  4411. BD_SPACE, DCACHE_OFF);
  4412. buffer_loc.aggr_tx_descs = (struct mvpp2_tx_desc *)bd_space;
  4413. size += MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE;
  4414. buffer_loc.tx_descs =
  4415. (struct mvpp2_tx_desc *)((unsigned long)bd_space + size);
  4416. size += MVPP2_MAX_TXD * MVPP2_DESC_ALIGNED_SIZE;
  4417. buffer_loc.rx_descs =
  4418. (struct mvpp2_rx_desc *)((unsigned long)bd_space + size);
  4419. size += MVPP2_MAX_RXD * MVPP2_DESC_ALIGNED_SIZE;
  4420. for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
  4421. buffer_loc.bm_pool[i] =
  4422. (unsigned long *)((unsigned long)bd_space + size);
  4423. if (priv->hw_version == MVPP21)
  4424. size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u32);
  4425. else
  4426. size += MVPP2_BM_POOL_SIZE_MAX * 2 * sizeof(u64);
  4427. }
  4428. for (i = 0; i < MVPP2_BM_LONG_BUF_NUM; i++) {
  4429. buffer_loc.rx_buffer[i] =
  4430. (unsigned long *)((unsigned long)bd_space + size);
  4431. size += RX_BUFFER_SIZE;
  4432. }
  4433. /* Clear the complete area so that all descriptors are cleared */
  4434. memset(bd_space, 0, size);
  4435. /* Save base addresses for later use */
  4436. priv->base = (void *)devfdt_get_addr_index(dev, 0);
  4437. if (IS_ERR(priv->base))
  4438. return PTR_ERR(priv->base);
  4439. if (priv->hw_version == MVPP21) {
  4440. priv->lms_base = (void *)devfdt_get_addr_index(dev, 1);
  4441. if (IS_ERR(priv->lms_base))
  4442. return PTR_ERR(priv->lms_base);
  4443. } else {
  4444. priv->iface_base = (void *)devfdt_get_addr_index(dev, 1);
  4445. if (IS_ERR(priv->iface_base))
  4446. return PTR_ERR(priv->iface_base);
  4447. /* Store common base addresses for all ports */
  4448. priv->mpcs_base = priv->iface_base + MVPP22_MPCS;
  4449. priv->xpcs_base = priv->iface_base + MVPP22_XPCS;
  4450. priv->rfu1_base = priv->iface_base + MVPP22_RFU1;
  4451. }
  4452. if (priv->hw_version == MVPP21)
  4453. priv->max_port_rxqs = 8;
  4454. else
  4455. priv->max_port_rxqs = 32;
  4456. return 0;
  4457. }
  4458. static int mvpp2_probe(struct udevice *dev)
  4459. {
  4460. struct mvpp2_port *port = dev_get_priv(dev);
  4461. struct mvpp2 *priv = dev_get_priv(dev->parent);
  4462. struct mii_dev *bus;
  4463. int err;
  4464. /* Only call the probe function for the parent once */
  4465. if (!priv->probe_done)
  4466. err = mvpp2_base_probe(dev->parent);
  4467. port->priv = dev_get_priv(dev->parent);
  4468. /* Create and register the MDIO bus driver */
  4469. bus = mdio_alloc();
  4470. if (!bus) {
  4471. printf("Failed to allocate MDIO bus\n");
  4472. return -ENOMEM;
  4473. }
  4474. bus->read = mpp2_mdio_read;
  4475. bus->write = mpp2_mdio_write;
  4476. snprintf(bus->name, sizeof(bus->name), dev->name);
  4477. bus->priv = (void *)port;
  4478. port->bus = bus;
  4479. err = mdio_register(bus);
  4480. if (err)
  4481. return err;
  4482. err = phy_info_parse(dev, port);
  4483. if (err)
  4484. return err;
  4485. /*
  4486. * We need the port specific io base addresses at this stage, since
  4487. * gop_port_init() accesses these registers
  4488. */
  4489. if (priv->hw_version == MVPP21) {
  4490. int priv_common_regs_num = 2;
  4491. port->base = (void __iomem *)devfdt_get_addr_index(
  4492. dev->parent, priv_common_regs_num + port->id);
  4493. if (IS_ERR(port->base))
  4494. return PTR_ERR(port->base);
  4495. } else {
  4496. port->gop_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  4497. "gop-port-id", -1);
  4498. if (port->id == -1) {
  4499. dev_err(&pdev->dev, "missing gop-port-id value\n");
  4500. return -EINVAL;
  4501. }
  4502. port->base = priv->iface_base + MVPP22_PORT_BASE +
  4503. port->gop_id * MVPP22_PORT_OFFSET;
  4504. /* Set phy address of the port */
  4505. if(port->phy_node)
  4506. mvpp22_smi_phy_addr_cfg(port);
  4507. /* GoP Init */
  4508. gop_port_init(port);
  4509. }
  4510. if (!priv->probe_done) {
  4511. /* Initialize network controller */
  4512. err = mvpp2_init(dev, priv);
  4513. if (err < 0) {
  4514. dev_err(&pdev->dev, "failed to initialize controller\n");
  4515. return err;
  4516. }
  4517. priv->num_ports = 0;
  4518. priv->probe_done = 1;
  4519. }
  4520. err = mvpp2_port_probe(dev, port, dev_of_offset(dev), priv);
  4521. if (err)
  4522. return err;
  4523. if (priv->hw_version == MVPP22) {
  4524. priv->netc_config |= mvpp2_netc_cfg_create(port->gop_id,
  4525. port->phy_interface);
  4526. /* Netcomplex configurations for all ports */
  4527. gop_netc_init(priv, MV_NETC_FIRST_PHASE);
  4528. gop_netc_init(priv, MV_NETC_SECOND_PHASE);
  4529. }
  4530. return 0;
  4531. }
  4532. /*
  4533. * Empty BM pool and stop its activity before the OS is started
  4534. */
  4535. static int mvpp2_remove(struct udevice *dev)
  4536. {
  4537. struct mvpp2_port *port = dev_get_priv(dev);
  4538. struct mvpp2 *priv = port->priv;
  4539. int i;
  4540. priv->num_ports--;
  4541. if (priv->num_ports)
  4542. return 0;
  4543. for (i = 0; i < MVPP2_BM_POOLS_NUM; i++)
  4544. mvpp2_bm_pool_destroy(dev, priv, &priv->bm_pools[i]);
  4545. return 0;
  4546. }
  4547. static const struct eth_ops mvpp2_ops = {
  4548. .start = mvpp2_start,
  4549. .send = mvpp2_send,
  4550. .recv = mvpp2_recv,
  4551. .stop = mvpp2_stop,
  4552. .write_hwaddr = mvpp2_write_hwaddr
  4553. };
  4554. static struct driver mvpp2_driver = {
  4555. .name = "mvpp2",
  4556. .id = UCLASS_ETH,
  4557. .probe = mvpp2_probe,
  4558. .remove = mvpp2_remove,
  4559. .ops = &mvpp2_ops,
  4560. .priv_auto_alloc_size = sizeof(struct mvpp2_port),
  4561. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  4562. .flags = DM_FLAG_ACTIVE_DMA,
  4563. };
  4564. /*
  4565. * Use a MISC device to bind the n instances (child nodes) of the
  4566. * network base controller in UCLASS_ETH.
  4567. */
  4568. static int mvpp2_base_bind(struct udevice *parent)
  4569. {
  4570. const void *blob = gd->fdt_blob;
  4571. int node = dev_of_offset(parent);
  4572. struct uclass_driver *drv;
  4573. struct udevice *dev;
  4574. struct eth_pdata *plat;
  4575. char *name;
  4576. int subnode;
  4577. u32 id;
  4578. int base_id_add;
  4579. /* Lookup eth driver */
  4580. drv = lists_uclass_lookup(UCLASS_ETH);
  4581. if (!drv) {
  4582. puts("Cannot find eth driver\n");
  4583. return -ENOENT;
  4584. }
  4585. base_id_add = base_id;
  4586. fdt_for_each_subnode(subnode, blob, node) {
  4587. /* Increment base_id for all subnodes, also the disabled ones */
  4588. base_id++;
  4589. /* Skip disabled ports */
  4590. if (!fdtdec_get_is_enabled(blob, subnode))
  4591. continue;
  4592. plat = calloc(1, sizeof(*plat));
  4593. if (!plat)
  4594. return -ENOMEM;
  4595. id = fdtdec_get_int(blob, subnode, "port-id", -1);
  4596. id += base_id_add;
  4597. name = calloc(1, 16);
  4598. if (!name) {
  4599. free(plat);
  4600. return -ENOMEM;
  4601. }
  4602. sprintf(name, "mvpp2-%d", id);
  4603. /* Create child device UCLASS_ETH and bind it */
  4604. device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
  4605. dev_set_of_offset(dev, subnode);
  4606. }
  4607. return 0;
  4608. }
  4609. static const struct udevice_id mvpp2_ids[] = {
  4610. {
  4611. .compatible = "marvell,armada-375-pp2",
  4612. .data = MVPP21,
  4613. },
  4614. {
  4615. .compatible = "marvell,armada-7k-pp22",
  4616. .data = MVPP22,
  4617. },
  4618. { }
  4619. };
  4620. U_BOOT_DRIVER(mvpp2_base) = {
  4621. .name = "mvpp2_base",
  4622. .id = UCLASS_MISC,
  4623. .of_match = mvpp2_ids,
  4624. .bind = mvpp2_base_bind,
  4625. .priv_auto_alloc_size = sizeof(struct mvpp2),
  4626. };