mvneta.c 51 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
  4. *
  5. * U-Boot version:
  6. * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
  7. *
  8. * Based on the Linux version which is:
  9. * Copyright (C) 2012 Marvell
  10. *
  11. * Rami Rosen <rosenr@marvell.com>
  12. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  13. */
  14. #include <common.h>
  15. #include <dm.h>
  16. #include <net.h>
  17. #include <netdev.h>
  18. #include <config.h>
  19. #include <malloc.h>
  20. #include <asm/io.h>
  21. #include <linux/errno.h>
  22. #include <phy.h>
  23. #include <miiphy.h>
  24. #include <watchdog.h>
  25. #include <asm/arch/cpu.h>
  26. #include <asm/arch/soc.h>
  27. #include <linux/compat.h>
  28. #include <linux/mbus.h>
  29. #include <asm-generic/gpio.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #if !defined(CONFIG_PHYLIB)
  32. # error Marvell mvneta requires PHYLIB
  33. #endif
  34. #define CONFIG_NR_CPUS 1
  35. #define ETH_HLEN 14 /* Total octets in header */
  36. /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
  37. #define WRAP (2 + ETH_HLEN + 4 + 32)
  38. #define MTU 1500
  39. #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
  40. #define MVNETA_SMI_TIMEOUT 10000
  41. /* Registers */
  42. #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
  43. #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
  44. #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
  45. #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
  46. #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
  47. #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
  48. #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
  49. #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
  50. #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
  51. #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
  52. #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
  53. #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
  54. #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
  55. #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
  56. #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
  57. #define MVNETA_PORT_RX_RESET 0x1cc0
  58. #define MVNETA_PORT_RX_DMA_RESET BIT(0)
  59. #define MVNETA_PHY_ADDR 0x2000
  60. #define MVNETA_PHY_ADDR_MASK 0x1f
  61. #define MVNETA_SMI 0x2004
  62. #define MVNETA_PHY_REG_MASK 0x1f
  63. /* SMI register fields */
  64. #define MVNETA_SMI_DATA_OFFS 0 /* Data */
  65. #define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS)
  66. #define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
  67. #define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
  68. #define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
  69. #define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS)
  70. #define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */
  71. #define MVNETA_SMI_BUSY (1 << 28) /* Busy */
  72. #define MVNETA_MBUS_RETRY 0x2010
  73. #define MVNETA_UNIT_INTR_CAUSE 0x2080
  74. #define MVNETA_UNIT_CONTROL 0x20B0
  75. #define MVNETA_PHY_POLLING_ENABLE BIT(1)
  76. #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
  77. #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
  78. #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
  79. #define MVNETA_WIN_SIZE_MASK (0xffff0000)
  80. #define MVNETA_BASE_ADDR_ENABLE 0x2290
  81. #define MVNETA_BASE_ADDR_ENABLE_BIT 0x1
  82. #define MVNETA_PORT_ACCESS_PROTECT 0x2294
  83. #define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3
  84. #define MVNETA_PORT_CONFIG 0x2400
  85. #define MVNETA_UNI_PROMISC_MODE BIT(0)
  86. #define MVNETA_DEF_RXQ(q) ((q) << 1)
  87. #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
  88. #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
  89. #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
  90. #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
  91. #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
  92. #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
  93. #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
  94. MVNETA_DEF_RXQ_ARP(q) | \
  95. MVNETA_DEF_RXQ_TCP(q) | \
  96. MVNETA_DEF_RXQ_UDP(q) | \
  97. MVNETA_DEF_RXQ_BPDU(q) | \
  98. MVNETA_TX_UNSET_ERR_SUM | \
  99. MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
  100. #define MVNETA_PORT_CONFIG_EXTEND 0x2404
  101. #define MVNETA_MAC_ADDR_LOW 0x2414
  102. #define MVNETA_MAC_ADDR_HIGH 0x2418
  103. #define MVNETA_SDMA_CONFIG 0x241c
  104. #define MVNETA_SDMA_BRST_SIZE_16 4
  105. #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
  106. #define MVNETA_RX_NO_DATA_SWAP BIT(4)
  107. #define MVNETA_TX_NO_DATA_SWAP BIT(5)
  108. #define MVNETA_DESC_SWAP BIT(6)
  109. #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
  110. #define MVNETA_PORT_STATUS 0x2444
  111. #define MVNETA_TX_IN_PRGRS BIT(1)
  112. #define MVNETA_TX_FIFO_EMPTY BIT(8)
  113. #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
  114. #define MVNETA_SERDES_CFG 0x24A0
  115. #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
  116. #define MVNETA_QSGMII_SERDES_PROTO 0x0667
  117. #define MVNETA_TYPE_PRIO 0x24bc
  118. #define MVNETA_FORCE_UNI BIT(21)
  119. #define MVNETA_TXQ_CMD_1 0x24e4
  120. #define MVNETA_TXQ_CMD 0x2448
  121. #define MVNETA_TXQ_DISABLE_SHIFT 8
  122. #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
  123. #define MVNETA_ACC_MODE 0x2500
  124. #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
  125. #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
  126. #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
  127. #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
  128. /* Exception Interrupt Port/Queue Cause register */
  129. #define MVNETA_INTR_NEW_CAUSE 0x25a0
  130. #define MVNETA_INTR_NEW_MASK 0x25a4
  131. /* bits 0..7 = TXQ SENT, one bit per queue.
  132. * bits 8..15 = RXQ OCCUP, one bit per queue.
  133. * bits 16..23 = RXQ FREE, one bit per queue.
  134. * bit 29 = OLD_REG_SUM, see old reg ?
  135. * bit 30 = TX_ERR_SUM, one bit for 4 ports
  136. * bit 31 = MISC_SUM, one bit for 4 ports
  137. */
  138. #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
  139. #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
  140. #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
  141. #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
  142. #define MVNETA_INTR_OLD_CAUSE 0x25a8
  143. #define MVNETA_INTR_OLD_MASK 0x25ac
  144. /* Data Path Port/Queue Cause Register */
  145. #define MVNETA_INTR_MISC_CAUSE 0x25b0
  146. #define MVNETA_INTR_MISC_MASK 0x25b4
  147. #define MVNETA_INTR_ENABLE 0x25b8
  148. #define MVNETA_RXQ_CMD 0x2680
  149. #define MVNETA_RXQ_DISABLE_SHIFT 8
  150. #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
  151. #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
  152. #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
  153. #define MVNETA_GMAC_CTRL_0 0x2c00
  154. #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
  155. #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
  156. #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
  157. #define MVNETA_GMAC_CTRL_2 0x2c08
  158. #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
  159. #define MVNETA_GMAC2_PORT_RGMII BIT(4)
  160. #define MVNETA_GMAC2_PORT_RESET BIT(6)
  161. #define MVNETA_GMAC_STATUS 0x2c10
  162. #define MVNETA_GMAC_LINK_UP BIT(0)
  163. #define MVNETA_GMAC_SPEED_1000 BIT(1)
  164. #define MVNETA_GMAC_SPEED_100 BIT(2)
  165. #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
  166. #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
  167. #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
  168. #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
  169. #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
  170. #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
  171. #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
  172. #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
  173. #define MVNETA_GMAC_FORCE_LINK_UP (BIT(0) | BIT(1))
  174. #define MVNETA_GMAC_IB_BYPASS_AN_EN BIT(3)
  175. #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
  176. #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
  177. #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
  178. #define MVNETA_GMAC_SET_FC_EN BIT(8)
  179. #define MVNETA_GMAC_ADVERT_FC_EN BIT(9)
  180. #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
  181. #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
  182. #define MVNETA_GMAC_SAMPLE_TX_CFG_EN BIT(15)
  183. #define MVNETA_MIB_COUNTERS_BASE 0x3080
  184. #define MVNETA_MIB_LATE_COLLISION 0x7c
  185. #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
  186. #define MVNETA_DA_FILT_OTH_MCAST 0x3500
  187. #define MVNETA_DA_FILT_UCAST_BASE 0x3600
  188. #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
  189. #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
  190. #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
  191. #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
  192. #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
  193. #define MVNETA_TXQ_DEC_SENT_SHIFT 16
  194. #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
  195. #define MVNETA_TXQ_SENT_DESC_SHIFT 16
  196. #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
  197. #define MVNETA_PORT_TX_RESET 0x3cf0
  198. #define MVNETA_PORT_TX_DMA_RESET BIT(0)
  199. #define MVNETA_TX_MTU 0x3e0c
  200. #define MVNETA_TX_TOKEN_SIZE 0x3e14
  201. #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
  202. #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
  203. #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
  204. /* Descriptor ring Macros */
  205. #define MVNETA_QUEUE_NEXT_DESC(q, index) \
  206. (((index) < (q)->last_desc) ? ((index) + 1) : 0)
  207. /* Various constants */
  208. /* Coalescing */
  209. #define MVNETA_TXDONE_COAL_PKTS 16
  210. #define MVNETA_RX_COAL_PKTS 32
  211. #define MVNETA_RX_COAL_USEC 100
  212. /* The two bytes Marvell header. Either contains a special value used
  213. * by Marvell switches when a specific hardware mode is enabled (not
  214. * supported by this driver) or is filled automatically by zeroes on
  215. * the RX side. Those two bytes being at the front of the Ethernet
  216. * header, they allow to have the IP header aligned on a 4 bytes
  217. * boundary automatically: the hardware skips those two bytes on its
  218. * own.
  219. */
  220. #define MVNETA_MH_SIZE 2
  221. #define MVNETA_VLAN_TAG_LEN 4
  222. #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
  223. #define MVNETA_TX_CSUM_MAX_SIZE 9800
  224. #define MVNETA_ACC_MODE_EXT 1
  225. /* Timeout constants */
  226. #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
  227. #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
  228. #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
  229. #define MVNETA_TX_MTU_MAX 0x3ffff
  230. /* Max number of Rx descriptors */
  231. #define MVNETA_MAX_RXD 16
  232. /* Max number of Tx descriptors */
  233. #define MVNETA_MAX_TXD 16
  234. /* descriptor aligned size */
  235. #define MVNETA_DESC_ALIGNED_SIZE 32
  236. struct mvneta_port {
  237. void __iomem *base;
  238. struct mvneta_rx_queue *rxqs;
  239. struct mvneta_tx_queue *txqs;
  240. u8 mcast_count[256];
  241. u16 tx_ring_size;
  242. u16 rx_ring_size;
  243. phy_interface_t phy_interface;
  244. unsigned int link;
  245. unsigned int duplex;
  246. unsigned int speed;
  247. int init;
  248. int phyaddr;
  249. struct phy_device *phydev;
  250. #ifdef CONFIG_DM_GPIO
  251. struct gpio_desc phy_reset_gpio;
  252. #endif
  253. struct mii_dev *bus;
  254. };
  255. /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
  256. * layout of the transmit and reception DMA descriptors, and their
  257. * layout is therefore defined by the hardware design
  258. */
  259. #define MVNETA_TX_L3_OFF_SHIFT 0
  260. #define MVNETA_TX_IP_HLEN_SHIFT 8
  261. #define MVNETA_TX_L4_UDP BIT(16)
  262. #define MVNETA_TX_L3_IP6 BIT(17)
  263. #define MVNETA_TXD_IP_CSUM BIT(18)
  264. #define MVNETA_TXD_Z_PAD BIT(19)
  265. #define MVNETA_TXD_L_DESC BIT(20)
  266. #define MVNETA_TXD_F_DESC BIT(21)
  267. #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
  268. MVNETA_TXD_L_DESC | \
  269. MVNETA_TXD_F_DESC)
  270. #define MVNETA_TX_L4_CSUM_FULL BIT(30)
  271. #define MVNETA_TX_L4_CSUM_NOT BIT(31)
  272. #define MVNETA_RXD_ERR_CRC 0x0
  273. #define MVNETA_RXD_ERR_SUMMARY BIT(16)
  274. #define MVNETA_RXD_ERR_OVERRUN BIT(17)
  275. #define MVNETA_RXD_ERR_LEN BIT(18)
  276. #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
  277. #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
  278. #define MVNETA_RXD_L3_IP4 BIT(25)
  279. #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
  280. #define MVNETA_RXD_L4_CSUM_OK BIT(30)
  281. struct mvneta_tx_desc {
  282. u32 command; /* Options used by HW for packet transmitting.*/
  283. u16 reserverd1; /* csum_l4 (for future use) */
  284. u16 data_size; /* Data size of transmitted packet in bytes */
  285. u32 buf_phys_addr; /* Physical addr of transmitted buffer */
  286. u32 reserved2; /* hw_cmd - (for future use, PMT) */
  287. u32 reserved3[4]; /* Reserved - (for future use) */
  288. };
  289. struct mvneta_rx_desc {
  290. u32 status; /* Info about received packet */
  291. u16 reserved1; /* pnc_info - (for future use, PnC) */
  292. u16 data_size; /* Size of received packet in bytes */
  293. u32 buf_phys_addr; /* Physical address of the buffer */
  294. u32 reserved2; /* pnc_flow_id (for future use, PnC) */
  295. u32 buf_cookie; /* cookie for access to RX buffer in rx path */
  296. u16 reserved3; /* prefetch_cmd, for future use */
  297. u16 reserved4; /* csum_l4 - (for future use, PnC) */
  298. u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
  299. u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
  300. };
  301. struct mvneta_tx_queue {
  302. /* Number of this TX queue, in the range 0-7 */
  303. u8 id;
  304. /* Number of TX DMA descriptors in the descriptor ring */
  305. int size;
  306. /* Index of last TX DMA descriptor that was inserted */
  307. int txq_put_index;
  308. /* Index of the TX DMA descriptor to be cleaned up */
  309. int txq_get_index;
  310. /* Virtual address of the TX DMA descriptors array */
  311. struct mvneta_tx_desc *descs;
  312. /* DMA address of the TX DMA descriptors array */
  313. dma_addr_t descs_phys;
  314. /* Index of the last TX DMA descriptor */
  315. int last_desc;
  316. /* Index of the next TX DMA descriptor to process */
  317. int next_desc_to_proc;
  318. };
  319. struct mvneta_rx_queue {
  320. /* rx queue number, in the range 0-7 */
  321. u8 id;
  322. /* num of rx descriptors in the rx descriptor ring */
  323. int size;
  324. /* Virtual address of the RX DMA descriptors array */
  325. struct mvneta_rx_desc *descs;
  326. /* DMA address of the RX DMA descriptors array */
  327. dma_addr_t descs_phys;
  328. /* Index of the last RX DMA descriptor */
  329. int last_desc;
  330. /* Index of the next RX DMA descriptor to process */
  331. int next_desc_to_proc;
  332. };
  333. /* U-Boot doesn't use the queues, so set the number to 1 */
  334. static int rxq_number = 1;
  335. static int txq_number = 1;
  336. static int rxq_def;
  337. struct buffer_location {
  338. struct mvneta_tx_desc *tx_descs;
  339. struct mvneta_rx_desc *rx_descs;
  340. u32 rx_buffers;
  341. };
  342. /*
  343. * All 4 interfaces use the same global buffer, since only one interface
  344. * can be enabled at once
  345. */
  346. static struct buffer_location buffer_loc;
  347. /*
  348. * Page table entries are set to 1MB, or multiples of 1MB
  349. * (not < 1MB). driver uses less bd's so use 1MB bdspace.
  350. */
  351. #define BD_SPACE (1 << 20)
  352. /*
  353. * Dummy implementation that can be overwritten by a board
  354. * specific function
  355. */
  356. __weak int board_network_enable(struct mii_dev *bus)
  357. {
  358. return 0;
  359. }
  360. /* Utility/helper methods */
  361. /* Write helper method */
  362. static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
  363. {
  364. writel(data, pp->base + offset);
  365. }
  366. /* Read helper method */
  367. static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
  368. {
  369. return readl(pp->base + offset);
  370. }
  371. /* Clear all MIB counters */
  372. static void mvneta_mib_counters_clear(struct mvneta_port *pp)
  373. {
  374. int i;
  375. /* Perform dummy reads from MIB counters */
  376. for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
  377. mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
  378. }
  379. /* Rx descriptors helper methods */
  380. /* Checks whether the RX descriptor having this status is both the first
  381. * and the last descriptor for the RX packet. Each RX packet is currently
  382. * received through a single RX descriptor, so not having each RX
  383. * descriptor with its first and last bits set is an error
  384. */
  385. static int mvneta_rxq_desc_is_first_last(u32 status)
  386. {
  387. return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
  388. MVNETA_RXD_FIRST_LAST_DESC;
  389. }
  390. /* Add number of descriptors ready to receive new packets */
  391. static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
  392. struct mvneta_rx_queue *rxq,
  393. int ndescs)
  394. {
  395. /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
  396. * be added at once
  397. */
  398. while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
  399. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
  400. (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
  401. MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
  402. ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
  403. }
  404. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
  405. (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
  406. }
  407. /* Get number of RX descriptors occupied by received packets */
  408. static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
  409. struct mvneta_rx_queue *rxq)
  410. {
  411. u32 val;
  412. val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
  413. return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
  414. }
  415. /* Update num of rx desc called upon return from rx path or
  416. * from mvneta_rxq_drop_pkts().
  417. */
  418. static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
  419. struct mvneta_rx_queue *rxq,
  420. int rx_done, int rx_filled)
  421. {
  422. u32 val;
  423. if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
  424. val = rx_done |
  425. (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
  426. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
  427. return;
  428. }
  429. /* Only 255 descriptors can be added at once */
  430. while ((rx_done > 0) || (rx_filled > 0)) {
  431. if (rx_done <= 0xff) {
  432. val = rx_done;
  433. rx_done = 0;
  434. } else {
  435. val = 0xff;
  436. rx_done -= 0xff;
  437. }
  438. if (rx_filled <= 0xff) {
  439. val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
  440. rx_filled = 0;
  441. } else {
  442. val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
  443. rx_filled -= 0xff;
  444. }
  445. mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
  446. }
  447. }
  448. /* Get pointer to next RX descriptor to be processed by SW */
  449. static struct mvneta_rx_desc *
  450. mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
  451. {
  452. int rx_desc = rxq->next_desc_to_proc;
  453. rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
  454. return rxq->descs + rx_desc;
  455. }
  456. /* Tx descriptors helper methods */
  457. /* Update HW with number of TX descriptors to be sent */
  458. static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
  459. struct mvneta_tx_queue *txq,
  460. int pend_desc)
  461. {
  462. u32 val;
  463. /* Only 255 descriptors can be added at once ; Assume caller
  464. * process TX descriptors in quanta less than 256
  465. */
  466. val = pend_desc;
  467. mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
  468. }
  469. /* Get pointer to next TX descriptor to be processed (send) by HW */
  470. static struct mvneta_tx_desc *
  471. mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
  472. {
  473. int tx_desc = txq->next_desc_to_proc;
  474. txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
  475. return txq->descs + tx_desc;
  476. }
  477. /* Set rxq buf size */
  478. static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
  479. struct mvneta_rx_queue *rxq,
  480. int buf_size)
  481. {
  482. u32 val;
  483. val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
  484. val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
  485. val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
  486. mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
  487. }
  488. static int mvneta_port_is_fixed_link(struct mvneta_port *pp)
  489. {
  490. /* phy_addr is set to invalid value for fixed link */
  491. return pp->phyaddr > PHY_MAX_ADDR;
  492. }
  493. /* Start the Ethernet port RX and TX activity */
  494. static void mvneta_port_up(struct mvneta_port *pp)
  495. {
  496. int queue;
  497. u32 q_map;
  498. /* Enable all initialized TXs. */
  499. mvneta_mib_counters_clear(pp);
  500. q_map = 0;
  501. for (queue = 0; queue < txq_number; queue++) {
  502. struct mvneta_tx_queue *txq = &pp->txqs[queue];
  503. if (txq->descs != NULL)
  504. q_map |= (1 << queue);
  505. }
  506. mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
  507. /* Enable all initialized RXQs. */
  508. q_map = 0;
  509. for (queue = 0; queue < rxq_number; queue++) {
  510. struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
  511. if (rxq->descs != NULL)
  512. q_map |= (1 << queue);
  513. }
  514. mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
  515. }
  516. /* Stop the Ethernet port activity */
  517. static void mvneta_port_down(struct mvneta_port *pp)
  518. {
  519. u32 val;
  520. int count;
  521. /* Stop Rx port activity. Check port Rx activity. */
  522. val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
  523. /* Issue stop command for active channels only */
  524. if (val != 0)
  525. mvreg_write(pp, MVNETA_RXQ_CMD,
  526. val << MVNETA_RXQ_DISABLE_SHIFT);
  527. /* Wait for all Rx activity to terminate. */
  528. count = 0;
  529. do {
  530. if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
  531. netdev_warn(pp->dev,
  532. "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
  533. val);
  534. break;
  535. }
  536. mdelay(1);
  537. val = mvreg_read(pp, MVNETA_RXQ_CMD);
  538. } while (val & 0xff);
  539. /* Stop Tx port activity. Check port Tx activity. Issue stop
  540. * command for active channels only
  541. */
  542. val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
  543. if (val != 0)
  544. mvreg_write(pp, MVNETA_TXQ_CMD,
  545. (val << MVNETA_TXQ_DISABLE_SHIFT));
  546. /* Wait for all Tx activity to terminate. */
  547. count = 0;
  548. do {
  549. if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
  550. netdev_warn(pp->dev,
  551. "TIMEOUT for TX stopped status=0x%08x\n",
  552. val);
  553. break;
  554. }
  555. mdelay(1);
  556. /* Check TX Command reg that all Txqs are stopped */
  557. val = mvreg_read(pp, MVNETA_TXQ_CMD);
  558. } while (val & 0xff);
  559. /* Double check to verify that TX FIFO is empty */
  560. count = 0;
  561. do {
  562. if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
  563. netdev_warn(pp->dev,
  564. "TX FIFO empty timeout status=0x08%x\n",
  565. val);
  566. break;
  567. }
  568. mdelay(1);
  569. val = mvreg_read(pp, MVNETA_PORT_STATUS);
  570. } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
  571. (val & MVNETA_TX_IN_PRGRS));
  572. udelay(200);
  573. }
  574. /* Enable the port by setting the port enable bit of the MAC control register */
  575. static void mvneta_port_enable(struct mvneta_port *pp)
  576. {
  577. u32 val;
  578. /* Enable port */
  579. val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
  580. val |= MVNETA_GMAC0_PORT_ENABLE;
  581. mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
  582. }
  583. /* Disable the port and wait for about 200 usec before retuning */
  584. static void mvneta_port_disable(struct mvneta_port *pp)
  585. {
  586. u32 val;
  587. /* Reset the Enable bit in the Serial Control Register */
  588. val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
  589. val &= ~MVNETA_GMAC0_PORT_ENABLE;
  590. mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
  591. udelay(200);
  592. }
  593. /* Multicast tables methods */
  594. /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
  595. static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
  596. {
  597. int offset;
  598. u32 val;
  599. if (queue == -1) {
  600. val = 0;
  601. } else {
  602. val = 0x1 | (queue << 1);
  603. val |= (val << 24) | (val << 16) | (val << 8);
  604. }
  605. for (offset = 0; offset <= 0xc; offset += 4)
  606. mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
  607. }
  608. /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
  609. static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
  610. {
  611. int offset;
  612. u32 val;
  613. if (queue == -1) {
  614. val = 0;
  615. } else {
  616. val = 0x1 | (queue << 1);
  617. val |= (val << 24) | (val << 16) | (val << 8);
  618. }
  619. for (offset = 0; offset <= 0xfc; offset += 4)
  620. mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
  621. }
  622. /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
  623. static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
  624. {
  625. int offset;
  626. u32 val;
  627. if (queue == -1) {
  628. memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
  629. val = 0;
  630. } else {
  631. memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
  632. val = 0x1 | (queue << 1);
  633. val |= (val << 24) | (val << 16) | (val << 8);
  634. }
  635. for (offset = 0; offset <= 0xfc; offset += 4)
  636. mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
  637. }
  638. /* This method sets defaults to the NETA port:
  639. * Clears interrupt Cause and Mask registers.
  640. * Clears all MAC tables.
  641. * Sets defaults to all registers.
  642. * Resets RX and TX descriptor rings.
  643. * Resets PHY.
  644. * This method can be called after mvneta_port_down() to return the port
  645. * settings to defaults.
  646. */
  647. static void mvneta_defaults_set(struct mvneta_port *pp)
  648. {
  649. int cpu;
  650. int queue;
  651. u32 val;
  652. /* Clear all Cause registers */
  653. mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
  654. mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
  655. mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
  656. /* Mask all interrupts */
  657. mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
  658. mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
  659. mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
  660. mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
  661. /* Enable MBUS Retry bit16 */
  662. mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
  663. /* Set CPU queue access map - all CPUs have access to all RX
  664. * queues and to all TX queues
  665. */
  666. for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
  667. mvreg_write(pp, MVNETA_CPU_MAP(cpu),
  668. (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
  669. MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
  670. /* Reset RX and TX DMAs */
  671. mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
  672. mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
  673. /* Disable Legacy WRR, Disable EJP, Release from reset */
  674. mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
  675. for (queue = 0; queue < txq_number; queue++) {
  676. mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
  677. mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
  678. }
  679. mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
  680. mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
  681. /* Set Port Acceleration Mode */
  682. val = MVNETA_ACC_MODE_EXT;
  683. mvreg_write(pp, MVNETA_ACC_MODE, val);
  684. /* Update val of portCfg register accordingly with all RxQueue types */
  685. val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
  686. mvreg_write(pp, MVNETA_PORT_CONFIG, val);
  687. val = 0;
  688. mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
  689. mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
  690. /* Build PORT_SDMA_CONFIG_REG */
  691. val = 0;
  692. /* Default burst size */
  693. val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
  694. val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
  695. val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
  696. /* Assign port SDMA configuration */
  697. mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
  698. /* Enable PHY polling in hardware if not in fixed-link mode */
  699. if (!mvneta_port_is_fixed_link(pp)) {
  700. val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
  701. val |= MVNETA_PHY_POLLING_ENABLE;
  702. mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
  703. }
  704. mvneta_set_ucast_table(pp, -1);
  705. mvneta_set_special_mcast_table(pp, -1);
  706. mvneta_set_other_mcast_table(pp, -1);
  707. }
  708. /* Set unicast address */
  709. static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
  710. int queue)
  711. {
  712. unsigned int unicast_reg;
  713. unsigned int tbl_offset;
  714. unsigned int reg_offset;
  715. /* Locate the Unicast table entry */
  716. last_nibble = (0xf & last_nibble);
  717. /* offset from unicast tbl base */
  718. tbl_offset = (last_nibble / 4) * 4;
  719. /* offset within the above reg */
  720. reg_offset = last_nibble % 4;
  721. unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
  722. if (queue == -1) {
  723. /* Clear accepts frame bit at specified unicast DA tbl entry */
  724. unicast_reg &= ~(0xff << (8 * reg_offset));
  725. } else {
  726. unicast_reg &= ~(0xff << (8 * reg_offset));
  727. unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
  728. }
  729. mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
  730. }
  731. /* Set mac address */
  732. static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
  733. int queue)
  734. {
  735. unsigned int mac_h;
  736. unsigned int mac_l;
  737. if (queue != -1) {
  738. mac_l = (addr[4] << 8) | (addr[5]);
  739. mac_h = (addr[0] << 24) | (addr[1] << 16) |
  740. (addr[2] << 8) | (addr[3] << 0);
  741. mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
  742. mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
  743. }
  744. /* Accept frames of this address */
  745. mvneta_set_ucast_addr(pp, addr[5], queue);
  746. }
  747. static int mvneta_write_hwaddr(struct udevice *dev)
  748. {
  749. mvneta_mac_addr_set(dev_get_priv(dev),
  750. ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr,
  751. rxq_def);
  752. return 0;
  753. }
  754. /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
  755. static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
  756. u32 phys_addr, u32 cookie)
  757. {
  758. rx_desc->buf_cookie = cookie;
  759. rx_desc->buf_phys_addr = phys_addr;
  760. }
  761. /* Decrement sent descriptors counter */
  762. static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
  763. struct mvneta_tx_queue *txq,
  764. int sent_desc)
  765. {
  766. u32 val;
  767. /* Only 255 TX descriptors can be updated at once */
  768. while (sent_desc > 0xff) {
  769. val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
  770. mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
  771. sent_desc = sent_desc - 0xff;
  772. }
  773. val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
  774. mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
  775. }
  776. /* Get number of TX descriptors already sent by HW */
  777. static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
  778. struct mvneta_tx_queue *txq)
  779. {
  780. u32 val;
  781. int sent_desc;
  782. val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
  783. sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
  784. MVNETA_TXQ_SENT_DESC_SHIFT;
  785. return sent_desc;
  786. }
  787. /* Display more error info */
  788. static void mvneta_rx_error(struct mvneta_port *pp,
  789. struct mvneta_rx_desc *rx_desc)
  790. {
  791. u32 status = rx_desc->status;
  792. if (!mvneta_rxq_desc_is_first_last(status)) {
  793. netdev_err(pp->dev,
  794. "bad rx status %08x (buffer oversize), size=%d\n",
  795. status, rx_desc->data_size);
  796. return;
  797. }
  798. switch (status & MVNETA_RXD_ERR_CODE_MASK) {
  799. case MVNETA_RXD_ERR_CRC:
  800. netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
  801. status, rx_desc->data_size);
  802. break;
  803. case MVNETA_RXD_ERR_OVERRUN:
  804. netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
  805. status, rx_desc->data_size);
  806. break;
  807. case MVNETA_RXD_ERR_LEN:
  808. netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
  809. status, rx_desc->data_size);
  810. break;
  811. case MVNETA_RXD_ERR_RESOURCE:
  812. netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
  813. status, rx_desc->data_size);
  814. break;
  815. }
  816. }
  817. static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp,
  818. int rxq)
  819. {
  820. return &pp->rxqs[rxq];
  821. }
  822. /* Drop packets received by the RXQ and free buffers */
  823. static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
  824. struct mvneta_rx_queue *rxq)
  825. {
  826. int rx_done;
  827. rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
  828. if (rx_done)
  829. mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
  830. }
  831. /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
  832. static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
  833. int num)
  834. {
  835. int i;
  836. for (i = 0; i < num; i++) {
  837. u32 addr;
  838. /* U-Boot special: Fill in the rx buffer addresses */
  839. addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE);
  840. mvneta_rx_desc_fill(rxq->descs + i, addr, addr);
  841. }
  842. /* Add this number of RX descriptors as non occupied (ready to
  843. * get packets)
  844. */
  845. mvneta_rxq_non_occup_desc_add(pp, rxq, i);
  846. return 0;
  847. }
  848. /* Rx/Tx queue initialization/cleanup methods */
  849. /* Create a specified RX queue */
  850. static int mvneta_rxq_init(struct mvneta_port *pp,
  851. struct mvneta_rx_queue *rxq)
  852. {
  853. rxq->size = pp->rx_ring_size;
  854. /* Allocate memory for RX descriptors */
  855. rxq->descs_phys = (dma_addr_t)rxq->descs;
  856. if (rxq->descs == NULL)
  857. return -ENOMEM;
  858. WARN_ON(rxq->descs != PTR_ALIGN(rxq->descs, ARCH_DMA_MINALIGN));
  859. rxq->last_desc = rxq->size - 1;
  860. /* Set Rx descriptors queue starting address */
  861. mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
  862. mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
  863. /* Fill RXQ with buffers from RX pool */
  864. mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE);
  865. mvneta_rxq_fill(pp, rxq, rxq->size);
  866. return 0;
  867. }
  868. /* Cleanup Rx queue */
  869. static void mvneta_rxq_deinit(struct mvneta_port *pp,
  870. struct mvneta_rx_queue *rxq)
  871. {
  872. mvneta_rxq_drop_pkts(pp, rxq);
  873. rxq->descs = NULL;
  874. rxq->last_desc = 0;
  875. rxq->next_desc_to_proc = 0;
  876. rxq->descs_phys = 0;
  877. }
  878. /* Create and initialize a tx queue */
  879. static int mvneta_txq_init(struct mvneta_port *pp,
  880. struct mvneta_tx_queue *txq)
  881. {
  882. txq->size = pp->tx_ring_size;
  883. /* Allocate memory for TX descriptors */
  884. txq->descs_phys = (dma_addr_t)txq->descs;
  885. if (txq->descs == NULL)
  886. return -ENOMEM;
  887. WARN_ON(txq->descs != PTR_ALIGN(txq->descs, ARCH_DMA_MINALIGN));
  888. txq->last_desc = txq->size - 1;
  889. /* Set maximum bandwidth for enabled TXQs */
  890. mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
  891. mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
  892. /* Set Tx descriptors queue starting address */
  893. mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
  894. mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
  895. return 0;
  896. }
  897. /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
  898. static void mvneta_txq_deinit(struct mvneta_port *pp,
  899. struct mvneta_tx_queue *txq)
  900. {
  901. txq->descs = NULL;
  902. txq->last_desc = 0;
  903. txq->next_desc_to_proc = 0;
  904. txq->descs_phys = 0;
  905. /* Set minimum bandwidth for disabled TXQs */
  906. mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
  907. mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
  908. /* Set Tx descriptors queue starting address and size */
  909. mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
  910. mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
  911. }
  912. /* Cleanup all Tx queues */
  913. static void mvneta_cleanup_txqs(struct mvneta_port *pp)
  914. {
  915. int queue;
  916. for (queue = 0; queue < txq_number; queue++)
  917. mvneta_txq_deinit(pp, &pp->txqs[queue]);
  918. }
  919. /* Cleanup all Rx queues */
  920. static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
  921. {
  922. int queue;
  923. for (queue = 0; queue < rxq_number; queue++)
  924. mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
  925. }
  926. /* Init all Rx queues */
  927. static int mvneta_setup_rxqs(struct mvneta_port *pp)
  928. {
  929. int queue;
  930. for (queue = 0; queue < rxq_number; queue++) {
  931. int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
  932. if (err) {
  933. netdev_err(pp->dev, "%s: can't create rxq=%d\n",
  934. __func__, queue);
  935. mvneta_cleanup_rxqs(pp);
  936. return err;
  937. }
  938. }
  939. return 0;
  940. }
  941. /* Init all tx queues */
  942. static int mvneta_setup_txqs(struct mvneta_port *pp)
  943. {
  944. int queue;
  945. for (queue = 0; queue < txq_number; queue++) {
  946. int err = mvneta_txq_init(pp, &pp->txqs[queue]);
  947. if (err) {
  948. netdev_err(pp->dev, "%s: can't create txq=%d\n",
  949. __func__, queue);
  950. mvneta_cleanup_txqs(pp);
  951. return err;
  952. }
  953. }
  954. return 0;
  955. }
  956. static void mvneta_start_dev(struct mvneta_port *pp)
  957. {
  958. /* start the Rx/Tx activity */
  959. mvneta_port_enable(pp);
  960. }
  961. static void mvneta_adjust_link(struct udevice *dev)
  962. {
  963. struct mvneta_port *pp = dev_get_priv(dev);
  964. struct phy_device *phydev = pp->phydev;
  965. int status_change = 0;
  966. if (mvneta_port_is_fixed_link(pp)) {
  967. debug("Using fixed link, skip link adjust\n");
  968. return;
  969. }
  970. if (phydev->link) {
  971. if ((pp->speed != phydev->speed) ||
  972. (pp->duplex != phydev->duplex)) {
  973. u32 val;
  974. val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
  975. val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
  976. MVNETA_GMAC_CONFIG_GMII_SPEED |
  977. MVNETA_GMAC_CONFIG_FULL_DUPLEX |
  978. MVNETA_GMAC_AN_SPEED_EN |
  979. MVNETA_GMAC_AN_DUPLEX_EN);
  980. if (phydev->duplex)
  981. val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
  982. if (phydev->speed == SPEED_1000)
  983. val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
  984. else
  985. val |= MVNETA_GMAC_CONFIG_MII_SPEED;
  986. mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  987. pp->duplex = phydev->duplex;
  988. pp->speed = phydev->speed;
  989. }
  990. }
  991. if (phydev->link != pp->link) {
  992. if (!phydev->link) {
  993. pp->duplex = -1;
  994. pp->speed = 0;
  995. }
  996. pp->link = phydev->link;
  997. status_change = 1;
  998. }
  999. if (status_change) {
  1000. if (phydev->link) {
  1001. u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
  1002. val |= (MVNETA_GMAC_FORCE_LINK_PASS |
  1003. MVNETA_GMAC_FORCE_LINK_DOWN);
  1004. mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  1005. mvneta_port_up(pp);
  1006. } else {
  1007. mvneta_port_down(pp);
  1008. }
  1009. }
  1010. }
  1011. static int mvneta_open(struct udevice *dev)
  1012. {
  1013. struct mvneta_port *pp = dev_get_priv(dev);
  1014. int ret;
  1015. ret = mvneta_setup_rxqs(pp);
  1016. if (ret)
  1017. return ret;
  1018. ret = mvneta_setup_txqs(pp);
  1019. if (ret)
  1020. return ret;
  1021. mvneta_adjust_link(dev);
  1022. mvneta_start_dev(pp);
  1023. return 0;
  1024. }
  1025. /* Initialize hw */
  1026. static int mvneta_init2(struct mvneta_port *pp)
  1027. {
  1028. int queue;
  1029. /* Disable port */
  1030. mvneta_port_disable(pp);
  1031. /* Set port default values */
  1032. mvneta_defaults_set(pp);
  1033. pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
  1034. GFP_KERNEL);
  1035. if (!pp->txqs)
  1036. return -ENOMEM;
  1037. /* U-Boot special: use preallocated area */
  1038. pp->txqs[0].descs = buffer_loc.tx_descs;
  1039. /* Initialize TX descriptor rings */
  1040. for (queue = 0; queue < txq_number; queue++) {
  1041. struct mvneta_tx_queue *txq = &pp->txqs[queue];
  1042. txq->id = queue;
  1043. txq->size = pp->tx_ring_size;
  1044. }
  1045. pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
  1046. GFP_KERNEL);
  1047. if (!pp->rxqs) {
  1048. kfree(pp->txqs);
  1049. return -ENOMEM;
  1050. }
  1051. /* U-Boot special: use preallocated area */
  1052. pp->rxqs[0].descs = buffer_loc.rx_descs;
  1053. /* Create Rx descriptor rings */
  1054. for (queue = 0; queue < rxq_number; queue++) {
  1055. struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
  1056. rxq->id = queue;
  1057. rxq->size = pp->rx_ring_size;
  1058. }
  1059. return 0;
  1060. }
  1061. /* platform glue : initialize decoding windows */
  1062. /*
  1063. * Not like A380, in Armada3700, there are two layers of decode windows for GBE:
  1064. * First layer is: GbE Address window that resides inside the GBE unit,
  1065. * Second layer is: Fabric address window which is located in the NIC400
  1066. * (South Fabric).
  1067. * To simplify the address decode configuration for Armada3700, we bypass the
  1068. * first layer of GBE decode window by setting the first window to 4GB.
  1069. */
  1070. static void mvneta_bypass_mbus_windows(struct mvneta_port *pp)
  1071. {
  1072. /*
  1073. * Set window size to 4GB, to bypass GBE address decode, leave the
  1074. * work to MBUS decode window
  1075. */
  1076. mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK);
  1077. /* Enable GBE address decode window 0 by set bit 0 to 0 */
  1078. clrbits_le32(pp->base + MVNETA_BASE_ADDR_ENABLE,
  1079. MVNETA_BASE_ADDR_ENABLE_BIT);
  1080. /* Set GBE address decode window 0 to full Access (read or write) */
  1081. setbits_le32(pp->base + MVNETA_PORT_ACCESS_PROTECT,
  1082. MVNETA_PORT_ACCESS_PROTECT_WIN0_RW);
  1083. }
  1084. static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
  1085. {
  1086. const struct mbus_dram_target_info *dram;
  1087. u32 win_enable;
  1088. u32 win_protect;
  1089. int i;
  1090. dram = mvebu_mbus_dram_info();
  1091. for (i = 0; i < 6; i++) {
  1092. mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
  1093. mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
  1094. if (i < 4)
  1095. mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
  1096. }
  1097. win_enable = 0x3f;
  1098. win_protect = 0;
  1099. for (i = 0; i < dram->num_cs; i++) {
  1100. const struct mbus_dram_window *cs = dram->cs + i;
  1101. mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
  1102. (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
  1103. mvreg_write(pp, MVNETA_WIN_SIZE(i),
  1104. (cs->size - 1) & 0xffff0000);
  1105. win_enable &= ~(1 << i);
  1106. win_protect |= 3 << (2 * i);
  1107. }
  1108. mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
  1109. }
  1110. /* Power up the port */
  1111. static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
  1112. {
  1113. u32 ctrl;
  1114. /* MAC Cause register should be cleared */
  1115. mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
  1116. ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
  1117. /* Even though it might look weird, when we're configured in
  1118. * SGMII or QSGMII mode, the RGMII bit needs to be set.
  1119. */
  1120. switch (phy_mode) {
  1121. case PHY_INTERFACE_MODE_QSGMII:
  1122. mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
  1123. ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
  1124. break;
  1125. case PHY_INTERFACE_MODE_SGMII:
  1126. mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
  1127. ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
  1128. break;
  1129. case PHY_INTERFACE_MODE_RGMII:
  1130. case PHY_INTERFACE_MODE_RGMII_ID:
  1131. ctrl |= MVNETA_GMAC2_PORT_RGMII;
  1132. break;
  1133. default:
  1134. return -EINVAL;
  1135. }
  1136. /* Cancel Port Reset */
  1137. ctrl &= ~MVNETA_GMAC2_PORT_RESET;
  1138. mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
  1139. while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
  1140. MVNETA_GMAC2_PORT_RESET) != 0)
  1141. continue;
  1142. return 0;
  1143. }
  1144. /* Device initialization routine */
  1145. static int mvneta_init(struct udevice *dev)
  1146. {
  1147. struct eth_pdata *pdata = dev_get_platdata(dev);
  1148. struct mvneta_port *pp = dev_get_priv(dev);
  1149. int err;
  1150. pp->tx_ring_size = MVNETA_MAX_TXD;
  1151. pp->rx_ring_size = MVNETA_MAX_RXD;
  1152. err = mvneta_init2(pp);
  1153. if (err < 0) {
  1154. dev_err(&pdev->dev, "can't init eth hal\n");
  1155. return err;
  1156. }
  1157. mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def);
  1158. err = mvneta_port_power_up(pp, pp->phy_interface);
  1159. if (err < 0) {
  1160. dev_err(&pdev->dev, "can't power up port\n");
  1161. return err;
  1162. }
  1163. /* Call open() now as it needs to be done before runing send() */
  1164. mvneta_open(dev);
  1165. return 0;
  1166. }
  1167. /* U-Boot only functions follow here */
  1168. /* SMI / MDIO functions */
  1169. static int smi_wait_ready(struct mvneta_port *pp)
  1170. {
  1171. u32 timeout = MVNETA_SMI_TIMEOUT;
  1172. u32 smi_reg;
  1173. /* wait till the SMI is not busy */
  1174. do {
  1175. /* read smi register */
  1176. smi_reg = mvreg_read(pp, MVNETA_SMI);
  1177. if (timeout-- == 0) {
  1178. printf("Error: SMI busy timeout\n");
  1179. return -EFAULT;
  1180. }
  1181. } while (smi_reg & MVNETA_SMI_BUSY);
  1182. return 0;
  1183. }
  1184. /*
  1185. * mvneta_mdio_read - miiphy_read callback function.
  1186. *
  1187. * Returns 16bit phy register value, or 0xffff on error
  1188. */
  1189. static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  1190. {
  1191. struct mvneta_port *pp = bus->priv;
  1192. u32 smi_reg;
  1193. u32 timeout;
  1194. /* check parameters */
  1195. if (addr > MVNETA_PHY_ADDR_MASK) {
  1196. printf("Error: Invalid PHY address %d\n", addr);
  1197. return -EFAULT;
  1198. }
  1199. if (reg > MVNETA_PHY_REG_MASK) {
  1200. printf("Err: Invalid register offset %d\n", reg);
  1201. return -EFAULT;
  1202. }
  1203. /* wait till the SMI is not busy */
  1204. if (smi_wait_ready(pp) < 0)
  1205. return -EFAULT;
  1206. /* fill the phy address and regiser offset and read opcode */
  1207. smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS)
  1208. | (reg << MVNETA_SMI_REG_ADDR_OFFS)
  1209. | MVNETA_SMI_OPCODE_READ;
  1210. /* write the smi register */
  1211. mvreg_write(pp, MVNETA_SMI, smi_reg);
  1212. /* wait till read value is ready */
  1213. timeout = MVNETA_SMI_TIMEOUT;
  1214. do {
  1215. /* read smi register */
  1216. smi_reg = mvreg_read(pp, MVNETA_SMI);
  1217. if (timeout-- == 0) {
  1218. printf("Err: SMI read ready timeout\n");
  1219. return -EFAULT;
  1220. }
  1221. } while (!(smi_reg & MVNETA_SMI_READ_VALID));
  1222. /* Wait for the data to update in the SMI register */
  1223. for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++)
  1224. ;
  1225. return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK;
  1226. }
  1227. /*
  1228. * mvneta_mdio_write - miiphy_write callback function.
  1229. *
  1230. * Returns 0 if write succeed, -EINVAL on bad parameters
  1231. * -ETIME on timeout
  1232. */
  1233. static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  1234. u16 value)
  1235. {
  1236. struct mvneta_port *pp = bus->priv;
  1237. u32 smi_reg;
  1238. /* check parameters */
  1239. if (addr > MVNETA_PHY_ADDR_MASK) {
  1240. printf("Error: Invalid PHY address %d\n", addr);
  1241. return -EFAULT;
  1242. }
  1243. if (reg > MVNETA_PHY_REG_MASK) {
  1244. printf("Err: Invalid register offset %d\n", reg);
  1245. return -EFAULT;
  1246. }
  1247. /* wait till the SMI is not busy */
  1248. if (smi_wait_ready(pp) < 0)
  1249. return -EFAULT;
  1250. /* fill the phy addr and reg offset and write opcode and data */
  1251. smi_reg = value << MVNETA_SMI_DATA_OFFS;
  1252. smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS)
  1253. | (reg << MVNETA_SMI_REG_ADDR_OFFS);
  1254. smi_reg &= ~MVNETA_SMI_OPCODE_READ;
  1255. /* write the smi register */
  1256. mvreg_write(pp, MVNETA_SMI, smi_reg);
  1257. return 0;
  1258. }
  1259. static int mvneta_start(struct udevice *dev)
  1260. {
  1261. struct mvneta_port *pp = dev_get_priv(dev);
  1262. struct phy_device *phydev;
  1263. mvneta_port_power_up(pp, pp->phy_interface);
  1264. if (!pp->init || pp->link == 0) {
  1265. if (mvneta_port_is_fixed_link(pp)) {
  1266. u32 val;
  1267. pp->init = 1;
  1268. pp->link = 1;
  1269. mvneta_init(dev);
  1270. val = MVNETA_GMAC_FORCE_LINK_UP |
  1271. MVNETA_GMAC_IB_BYPASS_AN_EN |
  1272. MVNETA_GMAC_SET_FC_EN |
  1273. MVNETA_GMAC_ADVERT_FC_EN |
  1274. MVNETA_GMAC_SAMPLE_TX_CFG_EN;
  1275. if (pp->duplex)
  1276. val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
  1277. if (pp->speed == SPEED_1000)
  1278. val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
  1279. else if (pp->speed == SPEED_100)
  1280. val |= MVNETA_GMAC_CONFIG_MII_SPEED;
  1281. mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
  1282. } else {
  1283. /* Set phy address of the port */
  1284. mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr);
  1285. phydev = phy_connect(pp->bus, pp->phyaddr, dev,
  1286. pp->phy_interface);
  1287. if (!phydev) {
  1288. printf("phy_connect failed\n");
  1289. return -ENODEV;
  1290. }
  1291. pp->phydev = phydev;
  1292. phy_config(phydev);
  1293. phy_startup(phydev);
  1294. if (!phydev->link) {
  1295. printf("%s: No link.\n", phydev->dev->name);
  1296. return -1;
  1297. }
  1298. /* Full init on first call */
  1299. mvneta_init(dev);
  1300. pp->init = 1;
  1301. return 0;
  1302. }
  1303. }
  1304. /* Upon all following calls, this is enough */
  1305. mvneta_port_up(pp);
  1306. mvneta_port_enable(pp);
  1307. return 0;
  1308. }
  1309. static int mvneta_send(struct udevice *dev, void *packet, int length)
  1310. {
  1311. struct mvneta_port *pp = dev_get_priv(dev);
  1312. struct mvneta_tx_queue *txq = &pp->txqs[0];
  1313. struct mvneta_tx_desc *tx_desc;
  1314. int sent_desc;
  1315. u32 timeout = 0;
  1316. /* Get a descriptor for the first part of the packet */
  1317. tx_desc = mvneta_txq_next_desc_get(txq);
  1318. tx_desc->buf_phys_addr = (u32)(uintptr_t)packet;
  1319. tx_desc->data_size = length;
  1320. flush_dcache_range((ulong)packet,
  1321. (ulong)packet + ALIGN(length, PKTALIGN));
  1322. /* First and Last descriptor */
  1323. tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
  1324. mvneta_txq_pend_desc_add(pp, txq, 1);
  1325. /* Wait for packet to be sent (queue might help with speed here) */
  1326. sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
  1327. while (!sent_desc) {
  1328. if (timeout++ > 10000) {
  1329. printf("timeout: packet not sent\n");
  1330. return -1;
  1331. }
  1332. sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
  1333. }
  1334. /* txDone has increased - hw sent packet */
  1335. mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
  1336. return 0;
  1337. }
  1338. static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
  1339. {
  1340. struct mvneta_port *pp = dev_get_priv(dev);
  1341. int rx_done;
  1342. struct mvneta_rx_queue *rxq;
  1343. int rx_bytes = 0;
  1344. /* get rx queue */
  1345. rxq = mvneta_rxq_handle_get(pp, rxq_def);
  1346. rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
  1347. if (rx_done) {
  1348. struct mvneta_rx_desc *rx_desc;
  1349. unsigned char *data;
  1350. u32 rx_status;
  1351. /*
  1352. * No cache invalidation needed here, since the desc's are
  1353. * located in a uncached memory region
  1354. */
  1355. rx_desc = mvneta_rxq_next_desc_get(rxq);
  1356. rx_status = rx_desc->status;
  1357. if (!mvneta_rxq_desc_is_first_last(rx_status) ||
  1358. (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
  1359. mvneta_rx_error(pp, rx_desc);
  1360. /* leave the descriptor untouched */
  1361. return -EIO;
  1362. }
  1363. /* 2 bytes for marvell header. 4 bytes for crc */
  1364. rx_bytes = rx_desc->data_size - 6;
  1365. /* give packet to stack - skip on first 2 bytes */
  1366. data = (u8 *)(uintptr_t)rx_desc->buf_cookie + 2;
  1367. /*
  1368. * No cache invalidation needed here, since the rx_buffer's are
  1369. * located in a uncached memory region
  1370. */
  1371. *packetp = data;
  1372. /*
  1373. * Only mark one descriptor as free
  1374. * since only one was processed
  1375. */
  1376. mvneta_rxq_desc_num_update(pp, rxq, 1, 1);
  1377. }
  1378. return rx_bytes;
  1379. }
  1380. static int mvneta_probe(struct udevice *dev)
  1381. {
  1382. struct eth_pdata *pdata = dev_get_platdata(dev);
  1383. struct mvneta_port *pp = dev_get_priv(dev);
  1384. void *blob = (void *)gd->fdt_blob;
  1385. int node = dev_of_offset(dev);
  1386. struct mii_dev *bus;
  1387. unsigned long addr;
  1388. void *bd_space;
  1389. int ret;
  1390. int fl_node;
  1391. /*
  1392. * Allocate buffer area for descs and rx_buffers. This is only
  1393. * done once for all interfaces. As only one interface can
  1394. * be active. Make this area DMA safe by disabling the D-cache
  1395. */
  1396. if (!buffer_loc.tx_descs) {
  1397. u32 size;
  1398. /* Align buffer area for descs and rx_buffers to 1MiB */
  1399. bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
  1400. flush_dcache_range((ulong)bd_space, (ulong)bd_space + BD_SPACE);
  1401. mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE,
  1402. DCACHE_OFF);
  1403. buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
  1404. size = roundup(MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc),
  1405. ARCH_DMA_MINALIGN);
  1406. memset(buffer_loc.tx_descs, 0, size);
  1407. buffer_loc.rx_descs = (struct mvneta_rx_desc *)
  1408. ((phys_addr_t)bd_space + size);
  1409. size += roundup(MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc),
  1410. ARCH_DMA_MINALIGN);
  1411. buffer_loc.rx_buffers = (phys_addr_t)(bd_space + size);
  1412. }
  1413. pp->base = (void __iomem *)pdata->iobase;
  1414. /* Configure MBUS address windows */
  1415. if (device_is_compatible(dev, "marvell,armada-3700-neta"))
  1416. mvneta_bypass_mbus_windows(pp);
  1417. else
  1418. mvneta_conf_mbus_windows(pp);
  1419. /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */
  1420. pp->phy_interface = pdata->phy_interface;
  1421. /* fetch 'fixed-link' property from 'neta' node */
  1422. fl_node = fdt_subnode_offset(blob, node, "fixed-link");
  1423. if (fl_node != -FDT_ERR_NOTFOUND) {
  1424. /* set phy_addr to invalid value for fixed link */
  1425. pp->phyaddr = PHY_MAX_ADDR + 1;
  1426. pp->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex");
  1427. pp->speed = fdtdec_get_int(blob, fl_node, "speed", 0);
  1428. } else {
  1429. /* Now read phyaddr from DT */
  1430. addr = fdtdec_get_int(blob, node, "phy", 0);
  1431. addr = fdt_node_offset_by_phandle(blob, addr);
  1432. pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
  1433. }
  1434. bus = mdio_alloc();
  1435. if (!bus) {
  1436. printf("Failed to allocate MDIO bus\n");
  1437. return -ENOMEM;
  1438. }
  1439. bus->read = mvneta_mdio_read;
  1440. bus->write = mvneta_mdio_write;
  1441. snprintf(bus->name, sizeof(bus->name), dev->name);
  1442. bus->priv = (void *)pp;
  1443. pp->bus = bus;
  1444. ret = mdio_register(bus);
  1445. if (ret)
  1446. return ret;
  1447. #ifdef CONFIG_DM_GPIO
  1448. gpio_request_by_name(dev, "phy-reset-gpios", 0,
  1449. &pp->phy_reset_gpio, GPIOD_IS_OUT);
  1450. if (dm_gpio_is_valid(&pp->phy_reset_gpio)) {
  1451. dm_gpio_set_value(&pp->phy_reset_gpio, 1);
  1452. mdelay(10);
  1453. dm_gpio_set_value(&pp->phy_reset_gpio, 0);
  1454. }
  1455. #endif
  1456. return board_network_enable(bus);
  1457. }
  1458. static void mvneta_stop(struct udevice *dev)
  1459. {
  1460. struct mvneta_port *pp = dev_get_priv(dev);
  1461. mvneta_port_down(pp);
  1462. mvneta_port_disable(pp);
  1463. }
  1464. static const struct eth_ops mvneta_ops = {
  1465. .start = mvneta_start,
  1466. .send = mvneta_send,
  1467. .recv = mvneta_recv,
  1468. .stop = mvneta_stop,
  1469. .write_hwaddr = mvneta_write_hwaddr,
  1470. };
  1471. static int mvneta_ofdata_to_platdata(struct udevice *dev)
  1472. {
  1473. struct eth_pdata *pdata = dev_get_platdata(dev);
  1474. const char *phy_mode;
  1475. pdata->iobase = devfdt_get_addr(dev);
  1476. /* Get phy-mode / phy_interface from DT */
  1477. pdata->phy_interface = -1;
  1478. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  1479. NULL);
  1480. if (phy_mode)
  1481. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  1482. if (pdata->phy_interface == -1) {
  1483. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  1484. return -EINVAL;
  1485. }
  1486. return 0;
  1487. }
  1488. static const struct udevice_id mvneta_ids[] = {
  1489. { .compatible = "marvell,armada-370-neta" },
  1490. { .compatible = "marvell,armada-xp-neta" },
  1491. { .compatible = "marvell,armada-3700-neta" },
  1492. { }
  1493. };
  1494. U_BOOT_DRIVER(mvneta) = {
  1495. .name = "mvneta",
  1496. .id = UCLASS_ETH,
  1497. .of_match = mvneta_ids,
  1498. .ofdata_to_platdata = mvneta_ofdata_to_platdata,
  1499. .probe = mvneta_probe,
  1500. .ops = &mvneta_ops,
  1501. .priv_auto_alloc_size = sizeof(struct mvneta_port),
  1502. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  1503. };