lpc32xx_eth.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * LPC32xx Ethernet MAC interface driver
  4. *
  5. * (C) Copyright 2014 DENX Software Engineering GmbH
  6. * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
  7. */
  8. #include <common.h>
  9. #include <net.h>
  10. #include <malloc.h>
  11. #include <miiphy.h>
  12. #include <asm/io.h>
  13. #include <linux/errno.h>
  14. #include <asm/types.h>
  15. #include <asm/system.h>
  16. #include <asm/byteorder.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/config.h>
  19. /*
  20. * Notes:
  21. *
  22. * 1. Unless specified otherwise, all references to tables or paragraphs
  23. * are to UM10326, "LPC32x0 and LPC32x0/01 User manual".
  24. *
  25. * 2. Only bitfield masks/values which are actually used by the driver
  26. * are defined.
  27. */
  28. /* a single RX descriptor. The controller has an array of these */
  29. struct lpc32xx_eth_rxdesc {
  30. u32 packet; /* Receive packet pointer */
  31. u32 control; /* Descriptor command status */
  32. };
  33. #define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc))
  34. /* RX control bitfields/masks (see Table 330) */
  35. #define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x000007FF
  36. #define LPC32XX_ETH_RX_CTRL_UNUSED 0x7FFFF800
  37. #define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x80000000
  38. /* a single RX status. The controller has an array of these */
  39. struct lpc32xx_eth_rxstat {
  40. u32 statusinfo; /* Transmit Descriptor status */
  41. u32 statushashcrc; /* Transmit Descriptor CRCs */
  42. };
  43. #define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat))
  44. /* RX statusinfo bitfields/masks (see Table 333) */
  45. #define RX_STAT_RXSIZE 0x000007FF
  46. /* Helper: OR of all errors except RANGE */
  47. #define RX_STAT_ERRORS 0x1B800000
  48. /* a single TX descriptor. The controller has an array of these */
  49. struct lpc32xx_eth_txdesc {
  50. u32 packet; /* Transmit packet pointer */
  51. u32 control; /* Descriptor control */
  52. };
  53. #define LPC32XX_ETH_TX_DESC_SIZE (sizeof(struct lpc32xx_eth_txdesc))
  54. /* TX control bitfields/masks (see Table 335) */
  55. #define TX_CTRL_TXSIZE 0x000007FF
  56. #define TX_CTRL_LAST 0x40000000
  57. /* a single TX status. The controller has an array of these */
  58. struct lpc32xx_eth_txstat {
  59. u32 statusinfo; /* Transmit Descriptor status */
  60. };
  61. #define LPC32XX_ETH_TX_STAT_SIZE (sizeof(struct lpc32xx_eth_txstat))
  62. /* Ethernet MAC interface registers (see Table 283) */
  63. struct lpc32xx_eth_registers {
  64. /* MAC registers - 0x3106_0000 to 0x3106_01FC */
  65. u32 mac1; /* MAC configuration register 1 */
  66. u32 mac2; /* MAC configuration register 2 */
  67. u32 ipgt; /* Back-to-back Inter-Packet Gap reg. */
  68. u32 ipgr; /* Non-back-to-back IPG register */
  69. u32 clrt; /* Collision Window / Retry register */
  70. u32 maxf; /* Maximum Frame register */
  71. u32 supp; /* Phy Support register */
  72. u32 test;
  73. u32 mcfg; /* MII management configuration reg. */
  74. u32 mcmd; /* MII management command register */
  75. u32 madr; /* MII management address register */
  76. u32 mwtd; /* MII management wite data register */
  77. u32 mrdd; /* MII management read data register */
  78. u32 mind; /* MII management indicators register */
  79. u32 reserved1[2];
  80. u32 sa0; /* Station address register 0 */
  81. u32 sa1; /* Station address register 1 */
  82. u32 sa2; /* Station address register 2 */
  83. u32 reserved2[45];
  84. /* Control registers */
  85. u32 command;
  86. u32 status;
  87. u32 rxdescriptor;
  88. u32 rxstatus;
  89. u32 rxdescriptornumber; /* actually, number MINUS ONE */
  90. u32 rxproduceindex; /* head of rx desc fifo */
  91. u32 rxconsumeindex; /* tail of rx desc fifo */
  92. u32 txdescriptor;
  93. u32 txstatus;
  94. u32 txdescriptornumber; /* actually, number MINUS ONE */
  95. u32 txproduceindex; /* head of rx desc fifo */
  96. u32 txconsumeindex; /* tail of rx desc fifo */
  97. u32 reserved3[10];
  98. u32 tsv0; /* Transmit status vector register 0 */
  99. u32 tsv1; /* Transmit status vector register 1 */
  100. u32 rsv; /* Receive status vector register */
  101. u32 reserved4[3];
  102. u32 flowcontrolcounter;
  103. u32 flowcontrolstatus;
  104. u32 reserved5[34];
  105. /* RX filter registers - 0x3106_0200 to 0x3106_0FDC */
  106. u32 rxfilterctrl;
  107. u32 rxfilterwolstatus;
  108. u32 rxfilterwolclear;
  109. u32 reserved6;
  110. u32 hashfilterl;
  111. u32 hashfilterh;
  112. u32 reserved7[882];
  113. /* Module control registers - 0x3106_0FE0 to 0x3106_0FF8 */
  114. u32 intstatus; /* Interrupt status register */
  115. u32 intenable;
  116. u32 intclear;
  117. u32 intset;
  118. u32 reserved8;
  119. u32 powerdown;
  120. u32 reserved9;
  121. };
  122. /* MAC1 register bitfields/masks and offsets (see Table 283) */
  123. #define MAC1_RECV_ENABLE 0x00000001
  124. #define MAC1_PASS_ALL_RX_FRAMES 0x00000002
  125. #define MAC1_SOFT_RESET 0x00008000
  126. /* Helper: general reset */
  127. #define MAC1_RESETS 0x0000CF00
  128. /* MAC2 register bitfields/masks and offsets (see Table 284) */
  129. #define MAC2_FULL_DUPLEX 0x00000001
  130. #define MAC2_CRC_ENABLE 0x00000010
  131. #define MAC2_PAD_CRC_ENABLE 0x00000020
  132. /* SUPP register bitfields/masks and offsets (see Table 290) */
  133. #define SUPP_SPEED 0x00000100
  134. /* MCFG register bitfields/masks and offsets (see Table 292) */
  135. #define MCFG_RESET_MII_MGMT 0x00008000
  136. /* divide clock by 28 (see Table 293) */
  137. #define MCFG_CLOCK_SELECT_DIV28 0x0000001C
  138. /* MADR register bitfields/masks and offsets (see Table 295) */
  139. #define MADR_REG_MASK 0x0000001F
  140. #define MADR_PHY_MASK 0x00001F00
  141. #define MADR_REG_OFFSET 0
  142. #define MADR_PHY_OFFSET 8
  143. /* MIND register bitfields/masks (see Table 298) */
  144. #define MIND_BUSY 0x00000001
  145. /* COMMAND register bitfields/masks and offsets (see Table 283) */
  146. #define COMMAND_RXENABLE 0x00000001
  147. #define COMMAND_TXENABLE 0x00000002
  148. #define COMMAND_PASSRUNTFRAME 0x00000040
  149. #define COMMAND_RMII 0x00000200
  150. #define COMMAND_FULL_DUPLEX 0x00000400
  151. /* Helper: general reset */
  152. #define COMMAND_RESETS 0x00000038
  153. /* STATUS register bitfields/masks and offsets (see Table 283) */
  154. #define STATUS_RXSTATUS 0x00000001
  155. #define STATUS_TXSTATUS 0x00000002
  156. /* RXFILTERCTRL register bitfields/masks (see Table 319) */
  157. #define RXFILTERCTRL_ACCEPTBROADCAST 0x00000002
  158. #define RXFILTERCTRL_ACCEPTPERFECT 0x00000020
  159. /* Buffers and descriptors */
  160. #define ATTRS(n) __aligned(n)
  161. #define TX_BUF_COUNT 4
  162. #define RX_BUF_COUNT 4
  163. struct lpc32xx_eth_buffers {
  164. ATTRS(4) struct lpc32xx_eth_txdesc tx_desc[TX_BUF_COUNT];
  165. ATTRS(4) struct lpc32xx_eth_txstat tx_stat[TX_BUF_COUNT];
  166. ATTRS(PKTALIGN) u8 tx_buf[TX_BUF_COUNT*PKTSIZE_ALIGN];
  167. ATTRS(4) struct lpc32xx_eth_rxdesc rx_desc[RX_BUF_COUNT];
  168. ATTRS(8) struct lpc32xx_eth_rxstat rx_stat[RX_BUF_COUNT];
  169. ATTRS(PKTALIGN) u8 rx_buf[RX_BUF_COUNT*PKTSIZE_ALIGN];
  170. };
  171. /* port device data struct */
  172. struct lpc32xx_eth_device {
  173. struct eth_device dev;
  174. struct lpc32xx_eth_registers *regs;
  175. struct lpc32xx_eth_buffers *bufs;
  176. bool phy_rmii;
  177. };
  178. #define LPC32XX_ETH_DEVICE_SIZE (sizeof(struct lpc32xx_eth_device))
  179. /* generic macros */
  180. #define to_lpc32xx_eth(_d) container_of(_d, struct lpc32xx_eth_device, dev)
  181. /* timeout for MII polling */
  182. #define MII_TIMEOUT 10000000
  183. /* limits for PHY and register addresses */
  184. #define MII_MAX_REG (MADR_REG_MASK >> MADR_REG_OFFSET)
  185. #define MII_MAX_PHY (MADR_PHY_MASK >> MADR_PHY_OFFSET)
  186. #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  187. /*
  188. * mii_reg_read - miiphy_read callback function.
  189. *
  190. * Returns 16bit phy register value, or 0xffff on error
  191. */
  192. static int mii_reg_read(struct mii_dev *bus, int phy_adr, int devad,
  193. int reg_ofs)
  194. {
  195. u16 data = 0;
  196. struct eth_device *dev = eth_get_dev_by_name(bus->name);
  197. struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
  198. struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
  199. u32 mind_reg;
  200. u32 timeout;
  201. /* check parameters */
  202. if (phy_adr > MII_MAX_PHY) {
  203. printf("%s:%u: Invalid PHY address %d\n",
  204. __func__, __LINE__, phy_adr);
  205. return -EFAULT;
  206. }
  207. if (reg_ofs > MII_MAX_REG) {
  208. printf("%s:%u: Invalid register offset %d\n",
  209. __func__, __LINE__, reg_ofs);
  210. return -EFAULT;
  211. }
  212. /* write the phy and reg addressse into the MII address reg */
  213. writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
  214. &regs->madr);
  215. /* write 1 to the MII command register to cause a read */
  216. writel(1, &regs->mcmd);
  217. /* wait till the MII is not busy */
  218. timeout = MII_TIMEOUT;
  219. do {
  220. /* read MII indicators register */
  221. mind_reg = readl(&regs->mind);
  222. if (--timeout == 0)
  223. break;
  224. } while (mind_reg & MIND_BUSY);
  225. /* write 0 to the MII command register to finish the read */
  226. writel(0, &regs->mcmd);
  227. if (timeout == 0) {
  228. printf("%s:%u: MII busy timeout\n", __func__, __LINE__);
  229. return -EFAULT;
  230. }
  231. data = (u16) readl(&regs->mrdd);
  232. debug("%s:(adr %d, off %d) => %04x\n", __func__, phy_adr,
  233. reg_ofs, data);
  234. return data;
  235. }
  236. /*
  237. * mii_reg_write - imiiphy_write callback function.
  238. *
  239. * Returns 0 if write succeed, -EINVAL on bad parameters
  240. * -ETIME on timeout
  241. */
  242. static int mii_reg_write(struct mii_dev *bus, int phy_adr, int devad,
  243. int reg_ofs, u16 data)
  244. {
  245. struct eth_device *dev = eth_get_dev_by_name(bus->name);
  246. struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
  247. struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
  248. u32 mind_reg;
  249. u32 timeout;
  250. /* check parameters */
  251. if (phy_adr > MII_MAX_PHY) {
  252. printf("%s:%u: Invalid PHY address %d\n",
  253. __func__, __LINE__, phy_adr);
  254. return -EFAULT;
  255. }
  256. if (reg_ofs > MII_MAX_REG) {
  257. printf("%s:%u: Invalid register offset %d\n",
  258. __func__, __LINE__, reg_ofs);
  259. return -EFAULT;
  260. }
  261. /* write the phy and reg addressse into the MII address reg */
  262. writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
  263. &regs->madr);
  264. /* write data to the MII write register */
  265. writel(data, &regs->mwtd);
  266. /* wait till the MII is not busy */
  267. timeout = MII_TIMEOUT;
  268. do {
  269. /* read MII indicators register */
  270. mind_reg = readl(&regs->mind);
  271. if (--timeout == 0)
  272. break;
  273. } while (mind_reg & MIND_BUSY);
  274. if (timeout == 0) {
  275. printf("%s:%u: MII busy timeout\n", __func__,
  276. __LINE__);
  277. return -EFAULT;
  278. }
  279. /*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr,
  280. reg_ofs, data);*/
  281. return 0;
  282. }
  283. #endif
  284. /*
  285. * Provide default Ethernet buffers base address if target did not.
  286. * Locate buffers in SRAM at 0x00001000 to avoid cache issues and
  287. * maximize throughput.
  288. */
  289. #if !defined(CONFIG_LPC32XX_ETH_BUFS_BASE)
  290. #define CONFIG_LPC32XX_ETH_BUFS_BASE 0x00001000
  291. #endif
  292. static struct lpc32xx_eth_device lpc32xx_eth = {
  293. .regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE,
  294. .bufs = (struct lpc32xx_eth_buffers *)CONFIG_LPC32XX_ETH_BUFS_BASE,
  295. #if defined(CONFIG_RMII)
  296. .phy_rmii = true,
  297. #endif
  298. };
  299. #define TX_TIMEOUT 10000
  300. static int lpc32xx_eth_send(struct eth_device *dev, void *dataptr, int datasize)
  301. {
  302. struct lpc32xx_eth_device *lpc32xx_eth_device =
  303. container_of(dev, struct lpc32xx_eth_device, dev);
  304. struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  305. struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
  306. int timeout, tx_index;
  307. /* time out if transmit descriptor array remains full too long */
  308. timeout = TX_TIMEOUT;
  309. while ((readl(&regs->status) & STATUS_TXSTATUS) &&
  310. (readl(&regs->txconsumeindex)
  311. == readl(&regs->txproduceindex))) {
  312. if (timeout-- == 0)
  313. return -1;
  314. }
  315. /* determine next transmit packet index to use */
  316. tx_index = readl(&regs->txproduceindex);
  317. /* set up transmit packet */
  318. memcpy((void *)&bufs->tx_buf[tx_index * PKTSIZE_ALIGN],
  319. (void *)dataptr, datasize);
  320. writel(TX_CTRL_LAST | ((datasize - 1) & TX_CTRL_TXSIZE),
  321. &bufs->tx_desc[tx_index].control);
  322. writel(0, &bufs->tx_stat[tx_index].statusinfo);
  323. /* pass transmit packet to DMA engine */
  324. tx_index = (tx_index + 1) % TX_BUF_COUNT;
  325. writel(tx_index, &regs->txproduceindex);
  326. /* transmission succeeded */
  327. return 0;
  328. }
  329. #define RX_TIMEOUT 1000000
  330. static int lpc32xx_eth_recv(struct eth_device *dev)
  331. {
  332. struct lpc32xx_eth_device *lpc32xx_eth_device =
  333. container_of(dev, struct lpc32xx_eth_device, dev);
  334. struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  335. struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
  336. int timeout, rx_index;
  337. /* time out if receive descriptor array remains empty too long */
  338. timeout = RX_TIMEOUT;
  339. while (readl(&regs->rxproduceindex) == readl(&regs->rxconsumeindex)) {
  340. if (timeout-- == 0)
  341. return -1;
  342. }
  343. /* determine next receive packet index to use */
  344. rx_index = readl(&regs->rxconsumeindex);
  345. /* if data was valid, pass it on */
  346. if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS)) {
  347. net_process_received_packet(
  348. &(bufs->rx_buf[rx_index * PKTSIZE_ALIGN]),
  349. (bufs->rx_stat[rx_index].statusinfo
  350. & RX_STAT_RXSIZE) + 1);
  351. }
  352. /* pass receive slot back to DMA engine */
  353. rx_index = (rx_index + 1) % RX_BUF_COUNT;
  354. writel(rx_index, &regs->rxconsumeindex);
  355. /* reception successful */
  356. return 0;
  357. }
  358. static int lpc32xx_eth_write_hwaddr(struct eth_device *dev)
  359. {
  360. struct lpc32xx_eth_device *lpc32xx_eth_device =
  361. container_of(dev, struct lpc32xx_eth_device, dev);
  362. struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  363. /* Save station address */
  364. writel((unsigned long) (dev->enetaddr[0] |
  365. (dev->enetaddr[1] << 8)), &regs->sa2);
  366. writel((unsigned long) (dev->enetaddr[2] |
  367. (dev->enetaddr[3] << 8)), &regs->sa1);
  368. writel((unsigned long) (dev->enetaddr[4] |
  369. (dev->enetaddr[5] << 8)), &regs->sa0);
  370. return 0;
  371. }
  372. static int lpc32xx_eth_init(struct eth_device *dev)
  373. {
  374. struct lpc32xx_eth_device *lpc32xx_eth_device =
  375. container_of(dev, struct lpc32xx_eth_device, dev);
  376. struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  377. struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
  378. int index;
  379. /* Initial MAC initialization */
  380. writel(MAC1_PASS_ALL_RX_FRAMES, &regs->mac1);
  381. writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, &regs->mac2);
  382. writel(PKTSIZE_ALIGN, &regs->maxf);
  383. /* Retries: 15 (0xF). Collision window: 57 (0x37). */
  384. writel(0x370F, &regs->clrt);
  385. /* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */
  386. writel(0x0012, &regs->ipgr);
  387. /* pass runt (smaller than 64 bytes) frames */
  388. if (lpc32xx_eth_device->phy_rmii)
  389. writel(COMMAND_PASSRUNTFRAME | COMMAND_RMII, &regs->command);
  390. else
  391. writel(COMMAND_PASSRUNTFRAME, &regs->command);
  392. /* Configure Full/Half Duplex mode */
  393. if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) {
  394. setbits_le32(&regs->mac2, MAC2_FULL_DUPLEX);
  395. setbits_le32(&regs->command, COMMAND_FULL_DUPLEX);
  396. writel(0x15, &regs->ipgt);
  397. } else {
  398. writel(0x12, &regs->ipgt);
  399. }
  400. /* Configure 100MBit/10MBit mode */
  401. if (miiphy_speed(dev->name, CONFIG_PHY_ADDR) == _100BASET)
  402. writel(SUPP_SPEED, &regs->supp);
  403. else
  404. writel(0, &regs->supp);
  405. /* Save station address */
  406. writel((unsigned long) (dev->enetaddr[0] |
  407. (dev->enetaddr[1] << 8)), &regs->sa2);
  408. writel((unsigned long) (dev->enetaddr[2] |
  409. (dev->enetaddr[3] << 8)), &regs->sa1);
  410. writel((unsigned long) (dev->enetaddr[4] |
  411. (dev->enetaddr[5] << 8)), &regs->sa0);
  412. /* set up transmit buffers */
  413. for (index = 0; index < TX_BUF_COUNT; index++) {
  414. bufs->tx_desc[index].control = 0;
  415. bufs->tx_stat[index].statusinfo = 0;
  416. }
  417. writel((u32)(&bufs->tx_desc), (u32 *)&regs->txdescriptor);
  418. writel((u32)(&bufs->tx_stat), &regs->txstatus);
  419. writel(TX_BUF_COUNT-1, &regs->txdescriptornumber);
  420. /* set up receive buffers */
  421. for (index = 0; index < RX_BUF_COUNT; index++) {
  422. bufs->rx_desc[index].packet =
  423. (u32) (bufs->rx_buf+index*PKTSIZE_ALIGN);
  424. bufs->rx_desc[index].control = PKTSIZE_ALIGN - 1;
  425. bufs->rx_stat[index].statusinfo = 0;
  426. bufs->rx_stat[index].statushashcrc = 0;
  427. }
  428. writel((u32)(&bufs->rx_desc), &regs->rxdescriptor);
  429. writel((u32)(&bufs->rx_stat), &regs->rxstatus);
  430. writel(RX_BUF_COUNT-1, &regs->rxdescriptornumber);
  431. /* set up transmit buffers */
  432. for (index = 0; index < TX_BUF_COUNT; index++)
  433. bufs->tx_desc[index].packet =
  434. (u32)(bufs->tx_buf + index * PKTSIZE_ALIGN);
  435. /* Enable broadcast and matching address packets */
  436. writel(RXFILTERCTRL_ACCEPTBROADCAST |
  437. RXFILTERCTRL_ACCEPTPERFECT, &regs->rxfilterctrl);
  438. /* Clear and disable interrupts */
  439. writel(0xFFFF, &regs->intclear);
  440. writel(0, &regs->intenable);
  441. /* Enable receive and transmit mode of MAC ethernet core */
  442. setbits_le32(&regs->command, COMMAND_RXENABLE | COMMAND_TXENABLE);
  443. setbits_le32(&regs->mac1, MAC1_RECV_ENABLE);
  444. /*
  445. * Perform a 'dummy' first send to work around Ethernet.1
  446. * erratum (see ES_LPC3250 rev. 9 dated 1 June 2011).
  447. * Use zeroed "index" variable as the dummy.
  448. */
  449. index = 0;
  450. lpc32xx_eth_send(dev, &index, 4);
  451. return 0;
  452. }
  453. static int lpc32xx_eth_halt(struct eth_device *dev)
  454. {
  455. struct lpc32xx_eth_device *lpc32xx_eth_device =
  456. container_of(dev, struct lpc32xx_eth_device, dev);
  457. struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  458. /* Reset all MAC logic */
  459. writel(MAC1_RESETS, &regs->mac1);
  460. writel(COMMAND_RESETS, &regs->command);
  461. /* Let reset condition settle */
  462. udelay(2000);
  463. return 0;
  464. }
  465. #if defined(CONFIG_PHYLIB)
  466. int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid)
  467. {
  468. struct lpc32xx_eth_device *lpc32xx_eth_device =
  469. container_of(dev, struct lpc32xx_eth_device, dev);
  470. struct mii_dev *bus;
  471. struct phy_device *phydev;
  472. int ret;
  473. bus = mdio_alloc();
  474. if (!bus) {
  475. printf("mdio_alloc failed\n");
  476. return -ENOMEM;
  477. }
  478. bus->read = mii_reg_read;
  479. bus->write = mii_reg_write;
  480. strcpy(bus->name, dev->name);
  481. ret = mdio_register(bus);
  482. if (ret) {
  483. printf("mdio_register failed\n");
  484. free(bus);
  485. return -ENOMEM;
  486. }
  487. if (lpc32xx_eth_device->phy_rmii)
  488. phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RMII);
  489. else
  490. phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII);
  491. if (!phydev) {
  492. printf("phy_connect failed\n");
  493. return -ENODEV;
  494. }
  495. phy_config(phydev);
  496. phy_startup(phydev);
  497. return 0;
  498. }
  499. #endif
  500. int lpc32xx_eth_initialize(bd_t *bis)
  501. {
  502. struct eth_device *dev = &lpc32xx_eth.dev;
  503. struct lpc32xx_eth_registers *regs = lpc32xx_eth.regs;
  504. /*
  505. * Set RMII management clock rate. With HCLK at 104 MHz and
  506. * a divider of 28, this will be 3.72 MHz.
  507. */
  508. writel(MCFG_RESET_MII_MGMT, &regs->mcfg);
  509. writel(MCFG_CLOCK_SELECT_DIV28, &regs->mcfg);
  510. /* Reset all MAC logic */
  511. writel(MAC1_RESETS, &regs->mac1);
  512. writel(COMMAND_RESETS, &regs->command);
  513. /* wait 10 ms for the whole I/F to reset */
  514. udelay(10000);
  515. /* must be less than sizeof(dev->name) */
  516. strcpy(dev->name, "eth0");
  517. dev->init = (void *)lpc32xx_eth_init;
  518. dev->halt = (void *)lpc32xx_eth_halt;
  519. dev->send = (void *)lpc32xx_eth_send;
  520. dev->recv = (void *)lpc32xx_eth_recv;
  521. dev->write_hwaddr = (void *)lpc32xx_eth_write_hwaddr;
  522. /* Release SOFT reset to let MII talk to PHY */
  523. clrbits_le32(&regs->mac1, MAC1_SOFT_RESET);
  524. /* register driver before talking to phy */
  525. eth_register(dev);
  526. #if defined(CONFIG_PHYLIB)
  527. lpc32xx_eth_phylib_init(dev, CONFIG_PHY_ADDR);
  528. #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  529. int retval;
  530. struct mii_dev *mdiodev = mdio_alloc();
  531. if (!mdiodev)
  532. return -ENOMEM;
  533. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  534. mdiodev->read = mii_reg_read;
  535. mdiodev->write = mii_reg_write;
  536. retval = mdio_register(mdiodev);
  537. if (retval < 0)
  538. return retval;
  539. #endif
  540. return 0;
  541. }