fm.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  4. * Dave Liu <daveliu@freescale.com>
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <malloc.h>
  9. #include <asm/io.h>
  10. #include <linux/errno.h>
  11. #include <u-boot/crc.h>
  12. #include "fm.h"
  13. #include <fsl_qe.h> /* For struct qe_firmware */
  14. #include <nand.h>
  15. #include <spi_flash.h>
  16. #include <mmc.h>
  17. #ifdef CONFIG_ARM64
  18. #include <asm/armv8/mmu.h>
  19. #include <asm/arch/cpu.h>
  20. #endif
  21. struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
  22. void *fm_muram_base(int fm_idx)
  23. {
  24. return muram[fm_idx].base;
  25. }
  26. void *fm_muram_alloc(int fm_idx, size_t size, ulong align)
  27. {
  28. void *ret;
  29. ulong align_mask;
  30. size_t off;
  31. void *save;
  32. align_mask = align - 1;
  33. save = muram[fm_idx].alloc;
  34. off = (ulong)save & align_mask;
  35. if (off != 0)
  36. muram[fm_idx].alloc += (align - off);
  37. off = size & align_mask;
  38. if (off != 0)
  39. size += (align - off);
  40. if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) {
  41. muram[fm_idx].alloc = save;
  42. printf("%s: run out of ram.\n", __func__);
  43. return NULL;
  44. }
  45. ret = muram[fm_idx].alloc;
  46. muram[fm_idx].alloc += size;
  47. memset((void *)ret, 0, size);
  48. return ret;
  49. }
  50. static void fm_init_muram(int fm_idx, void *reg)
  51. {
  52. void *base = reg;
  53. muram[fm_idx].base = base;
  54. muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;
  55. muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE;
  56. muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE;
  57. }
  58. /*
  59. * fm_upload_ucode - Fman microcode upload worker function
  60. *
  61. * This function does the actual uploading of an Fman microcode
  62. * to an Fman.
  63. */
  64. static void fm_upload_ucode(int fm_idx, struct fm_imem *imem,
  65. u32 *ucode, unsigned int size)
  66. {
  67. unsigned int i;
  68. unsigned int timeout = 1000000;
  69. /* enable address auto increase */
  70. out_be32(&imem->iadd, IRAM_IADD_AIE);
  71. /* write microcode to IRAM */
  72. for (i = 0; i < size / 4; i++)
  73. out_be32(&imem->idata, (be32_to_cpu(ucode[i])));
  74. /* verify if the writing is over */
  75. out_be32(&imem->iadd, 0);
  76. while ((in_be32(&imem->idata) != be32_to_cpu(ucode[0])) && --timeout)
  77. ;
  78. if (!timeout)
  79. printf("Fman%u: microcode upload timeout\n", fm_idx + 1);
  80. /* enable microcode from IRAM */
  81. out_be32(&imem->iready, IRAM_READY);
  82. }
  83. /*
  84. * Upload an Fman firmware
  85. *
  86. * This function is similar to qe_upload_firmware(), exception that it uploads
  87. * a microcode to the Fman instead of the QE.
  88. *
  89. * Because the process for uploading a microcode to the Fman is similar for
  90. * that of the QE, the QE firmware binary format is used for Fman microcode.
  91. * It should be possible to unify these two functions, but for now we keep them
  92. * separate.
  93. */
  94. static int fman_upload_firmware(int fm_idx,
  95. struct fm_imem *fm_imem,
  96. const struct qe_firmware *firmware)
  97. {
  98. unsigned int i;
  99. u32 crc;
  100. size_t calc_size = sizeof(struct qe_firmware);
  101. size_t length;
  102. const struct qe_header *hdr;
  103. if (!firmware) {
  104. printf("Fman%u: Invalid address for firmware\n", fm_idx + 1);
  105. return -EINVAL;
  106. }
  107. hdr = &firmware->header;
  108. length = be32_to_cpu(hdr->length);
  109. /* Check the magic */
  110. if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
  111. (hdr->magic[2] != 'F')) {
  112. printf("Fman%u: Data at %p is not a firmware\n", fm_idx + 1,
  113. firmware);
  114. return -EPERM;
  115. }
  116. /* Check the version */
  117. if (hdr->version != 1) {
  118. printf("Fman%u: Unsupported firmware version %u\n", fm_idx + 1,
  119. hdr->version);
  120. return -EPERM;
  121. }
  122. /* Validate some of the fields */
  123. if ((firmware->count != 1)) {
  124. printf("Fman%u: Invalid data in firmware header\n", fm_idx + 1);
  125. return -EINVAL;
  126. }
  127. /* Validate the length and check if there's a CRC */
  128. calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
  129. for (i = 0; i < firmware->count; i++)
  130. /*
  131. * For situations where the second RISC uses the same microcode
  132. * as the first, the 'code_offset' and 'count' fields will be
  133. * zero, so it's okay to add those.
  134. */
  135. calc_size += sizeof(u32) *
  136. be32_to_cpu(firmware->microcode[i].count);
  137. /* Validate the length */
  138. if (length != calc_size + sizeof(u32)) {
  139. printf("Fman%u: Invalid length in firmware header\n",
  140. fm_idx + 1);
  141. return -EPERM;
  142. }
  143. /*
  144. * Validate the CRC. We would normally call crc32_no_comp(), but that
  145. * function isn't available unless you turn on JFFS support.
  146. */
  147. crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
  148. if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
  149. printf("Fman%u: Firmware CRC is invalid\n", fm_idx + 1);
  150. return -EIO;
  151. }
  152. /* Loop through each microcode. */
  153. for (i = 0; i < firmware->count; i++) {
  154. const struct qe_microcode *ucode = &firmware->microcode[i];
  155. /* Upload a microcode if it's present */
  156. if (be32_to_cpu(ucode->code_offset)) {
  157. u32 ucode_size;
  158. u32 *code;
  159. printf("Fman%u: Uploading microcode version %u.%u.%u\n",
  160. fm_idx + 1, ucode->major, ucode->minor,
  161. ucode->revision);
  162. code = (void *)firmware +
  163. be32_to_cpu(ucode->code_offset);
  164. ucode_size = sizeof(u32) * be32_to_cpu(ucode->count);
  165. fm_upload_ucode(fm_idx, fm_imem, code, ucode_size);
  166. }
  167. }
  168. return 0;
  169. }
  170. static u32 fm_assign_risc(int port_id)
  171. {
  172. u32 risc_sel, val;
  173. risc_sel = (port_id & 0x1) ? FMFPPRC_RISC2 : FMFPPRC_RISC1;
  174. val = (port_id << FMFPPRC_PORTID_SHIFT) & FMFPPRC_PORTID_MASK;
  175. val |= ((risc_sel << FMFPPRC_ORA_SHIFT) | risc_sel);
  176. return val;
  177. }
  178. static void fm_init_fpm(struct fm_fpm *fpm)
  179. {
  180. int i, port_id;
  181. u32 val;
  182. setbits_be32(&fpm->fmfpee, FMFPEE_EHM | FMFPEE_UEC |
  183. FMFPEE_CER | FMFPEE_DER);
  184. /* IM mode, each even port ID to RISC#1, each odd port ID to RISC#2 */
  185. /* offline/parser port */
  186. for (i = 0; i < MAX_NUM_OH_PORT; i++) {
  187. port_id = OH_PORT_ID_BASE + i;
  188. val = fm_assign_risc(port_id);
  189. out_be32(&fpm->fpmprc, val);
  190. }
  191. /* Rx 1G port */
  192. for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
  193. port_id = RX_PORT_1G_BASE + i;
  194. val = fm_assign_risc(port_id);
  195. out_be32(&fpm->fpmprc, val);
  196. }
  197. /* Tx 1G port */
  198. for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
  199. port_id = TX_PORT_1G_BASE + i;
  200. val = fm_assign_risc(port_id);
  201. out_be32(&fpm->fpmprc, val);
  202. }
  203. /* Rx 10G port */
  204. port_id = RX_PORT_10G_BASE;
  205. val = fm_assign_risc(port_id);
  206. out_be32(&fpm->fpmprc, val);
  207. /* Tx 10G port */
  208. port_id = TX_PORT_10G_BASE;
  209. val = fm_assign_risc(port_id);
  210. out_be32(&fpm->fpmprc, val);
  211. /* disable the dispatch limit in IM case */
  212. out_be32(&fpm->fpmflc, FMFP_FLC_DISP_LIM_NONE);
  213. /* clear events */
  214. out_be32(&fpm->fmfpee, FMFPEE_CLEAR_EVENT);
  215. /* clear risc events */
  216. for (i = 0; i < 4; i++)
  217. out_be32(&fpm->fpmcev[i], 0xffffffff);
  218. /* clear error */
  219. out_be32(&fpm->fpmrcr, FMFP_RCR_MDEC | FMFP_RCR_IDEC);
  220. }
  221. static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi)
  222. {
  223. int blk, i, port_id;
  224. u32 val;
  225. size_t offset;
  226. void *base;
  227. /* alloc free buffer pool in MURAM */
  228. base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN);
  229. if (!base) {
  230. printf("%s: no muram for free buffer pool\n", __func__);
  231. return -ENOMEM;
  232. }
  233. offset = base - fm_muram_base(fm_idx);
  234. /* Need 128KB total free buffer pool size */
  235. val = offset / 256;
  236. blk = FM_FREE_POOL_SIZE / 256;
  237. /* in IM, we must not begin from offset 0 in MURAM */
  238. val |= ((blk - 1) << FMBM_CFG1_FBPS_SHIFT);
  239. out_be32(&bmi->fmbm_cfg1, val);
  240. /* disable all BMI interrupt */
  241. out_be32(&bmi->fmbm_ier, FMBM_IER_DISABLE_ALL);
  242. /* clear all events */
  243. out_be32(&bmi->fmbm_ievr, FMBM_IEVR_CLEAR_ALL);
  244. /*
  245. * set port parameters - FMBM_PP_x
  246. * max tasks 10G Rx/Tx=12, 1G Rx/Tx 4, others is 1
  247. * max dma 10G Rx/Tx=3, others is 1
  248. * set port FIFO size - FMBM_PFS_x
  249. * 4KB for all Rx and Tx ports
  250. */
  251. /* offline/parser port */
  252. for (i = 0; i < MAX_NUM_OH_PORT; i++) {
  253. port_id = OH_PORT_ID_BASE + i - 1;
  254. /* max tasks=1, max dma=1, no extra */
  255. out_be32(&bmi->fmbm_pp[port_id], 0);
  256. /* port FIFO size - 256 bytes, no extra */
  257. out_be32(&bmi->fmbm_pfs[port_id], 0);
  258. }
  259. /* Rx 1G port */
  260. for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
  261. port_id = RX_PORT_1G_BASE + i - 1;
  262. /* max tasks=4, max dma=1, no extra */
  263. out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
  264. /* FIFO size - 4KB, no extra */
  265. out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
  266. }
  267. /* Tx 1G port FIFO size - 4KB, no extra */
  268. for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
  269. port_id = TX_PORT_1G_BASE + i - 1;
  270. /* max tasks=4, max dma=1, no extra */
  271. out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
  272. /* FIFO size - 4KB, no extra */
  273. out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
  274. }
  275. /* Rx 10G port */
  276. port_id = RX_PORT_10G_BASE - 1;
  277. /* max tasks=12, max dma=3, no extra */
  278. out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
  279. /* FIFO size - 4KB, no extra */
  280. out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
  281. /* Tx 10G port */
  282. port_id = TX_PORT_10G_BASE - 1;
  283. /* max tasks=12, max dma=3, no extra */
  284. out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
  285. /* FIFO size - 4KB, no extra */
  286. out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
  287. /* initialize internal buffers data base (linked list) */
  288. out_be32(&bmi->fmbm_init, FMBM_INIT_START);
  289. return 0;
  290. }
  291. static void fm_init_qmi(struct fm_qmi_common *qmi)
  292. {
  293. /* disable all error interrupts */
  294. out_be32(&qmi->fmqm_eien, FMQM_EIEN_DISABLE_ALL);
  295. /* clear all error events */
  296. out_be32(&qmi->fmqm_eie, FMQM_EIE_CLEAR_ALL);
  297. /* disable all interrupts */
  298. out_be32(&qmi->fmqm_ien, FMQM_IEN_DISABLE_ALL);
  299. /* clear all interrupts */
  300. out_be32(&qmi->fmqm_ie, FMQM_IE_CLEAR_ALL);
  301. }
  302. /* Init common part of FM, index is fm num# like fm as above */
  303. #ifdef CONFIG_TFABOOT
  304. int fm_init_common(int index, struct ccsr_fman *reg)
  305. {
  306. int rc;
  307. void *addr = NULL;
  308. enum boot_src src = get_boot_src();
  309. if (src == BOOT_SOURCE_IFC_NOR) {
  310. addr = (void *)(CONFIG_SYS_FMAN_FW_ADDR +
  311. CONFIG_SYS_FSL_IFC_BASE);
  312. } else if (src == BOOT_SOURCE_IFC_NAND) {
  313. size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
  314. addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
  315. rc = nand_read(get_nand_dev_by_index(0),
  316. (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
  317. &fw_length, (u_char *)addr);
  318. if (rc == -EUCLEAN) {
  319. printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
  320. CONFIG_SYS_FMAN_FW_ADDR, rc);
  321. }
  322. } else if (src == BOOT_SOURCE_QSPI_NOR) {
  323. struct spi_flash *ucode_flash;
  324. addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
  325. int ret = 0;
  326. #ifdef CONFIG_DM_SPI_FLASH
  327. struct udevice *new;
  328. /* speed and mode will be read from DT */
  329. ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS,
  330. CONFIG_ENV_SPI_CS, 0, 0, &new);
  331. ucode_flash = dev_get_uclass_priv(new);
  332. #else
  333. ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS,
  334. CONFIG_ENV_SPI_CS,
  335. CONFIG_ENV_SPI_MAX_HZ,
  336. CONFIG_ENV_SPI_MODE);
  337. #endif
  338. if (!ucode_flash) {
  339. printf("SF: probe for ucode failed\n");
  340. } else {
  341. ret = spi_flash_read(ucode_flash,
  342. CONFIG_SYS_FMAN_FW_ADDR +
  343. CONFIG_SYS_FSL_QSPI_BASE,
  344. CONFIG_SYS_QE_FMAN_FW_LENGTH,
  345. addr);
  346. if (ret)
  347. printf("SF: read for ucode failed\n");
  348. spi_flash_free(ucode_flash);
  349. }
  350. } else if (src == BOOT_SOURCE_SD_MMC) {
  351. int dev = CONFIG_SYS_MMC_ENV_DEV;
  352. addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
  353. u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
  354. u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
  355. struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
  356. if (!mmc) {
  357. printf("\nMMC cannot find device for ucode\n");
  358. } else {
  359. printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
  360. dev, blk, cnt);
  361. mmc_init(mmc);
  362. (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
  363. addr);
  364. }
  365. } else {
  366. addr = NULL;
  367. }
  368. /* Upload the Fman microcode if it's present */
  369. rc = fman_upload_firmware(index, &reg->fm_imem, addr);
  370. if (rc)
  371. return rc;
  372. env_set_addr("fman_ucode", addr);
  373. fm_init_muram(index, &reg->muram);
  374. fm_init_qmi(&reg->fm_qmi_common);
  375. fm_init_fpm(&reg->fm_fpm);
  376. /* clear DMA status */
  377. setbits_be32(&reg->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
  378. /* set DMA mode */
  379. setbits_be32(&reg->fm_dma.fmdmmr, FMDMMR_SBER);
  380. return fm_init_bmi(index, &reg->fm_bmi_common);
  381. }
  382. #else
  383. int fm_init_common(int index, struct ccsr_fman *reg)
  384. {
  385. int rc;
  386. #if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
  387. void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
  388. #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
  389. size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
  390. void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
  391. rc = nand_read(get_nand_dev_by_index(0),
  392. (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
  393. &fw_length, (u_char *)addr);
  394. if (rc == -EUCLEAN) {
  395. printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
  396. CONFIG_SYS_FMAN_FW_ADDR, rc);
  397. }
  398. #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH)
  399. struct spi_flash *ucode_flash;
  400. void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
  401. int ret = 0;
  402. #ifdef CONFIG_DM_SPI_FLASH
  403. struct udevice *new;
  404. /* speed and mode will be read from DT */
  405. ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
  406. 0, 0, &new);
  407. ucode_flash = dev_get_uclass_priv(new);
  408. #else
  409. ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
  410. CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
  411. #endif
  412. if (!ucode_flash)
  413. printf("SF: probe for ucode failed\n");
  414. else {
  415. ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR,
  416. CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
  417. if (ret)
  418. printf("SF: read for ucode failed\n");
  419. spi_flash_free(ucode_flash);
  420. }
  421. #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
  422. int dev = CONFIG_SYS_MMC_ENV_DEV;
  423. void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
  424. u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
  425. u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
  426. struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
  427. if (!mmc)
  428. printf("\nMMC cannot find device for ucode\n");
  429. else {
  430. printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
  431. dev, blk, cnt);
  432. mmc_init(mmc);
  433. (void)blk_dread(mmc_get_blk_desc(mmc), blk, cnt,
  434. addr);
  435. }
  436. #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
  437. void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
  438. #else
  439. void *addr = NULL;
  440. #endif
  441. /* Upload the Fman microcode if it's present */
  442. rc = fman_upload_firmware(index, &reg->fm_imem, addr);
  443. if (rc)
  444. return rc;
  445. env_set_addr("fman_ucode", addr);
  446. fm_init_muram(index, &reg->muram);
  447. fm_init_qmi(&reg->fm_qmi_common);
  448. fm_init_fpm(&reg->fm_fpm);
  449. /* clear DMA status */
  450. setbits_be32(&reg->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
  451. /* set DMA mode */
  452. setbits_be32(&reg->fm_dma.fmdmmr, FMDMMR_SBER);
  453. return fm_init_bmi(index, &reg->fm_bmi_common);
  454. }
  455. #endif