ethoc.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Opencore 10/100 ethernet mac driver
  4. *
  5. * Copyright (C) 2007-2008 Avionic Design Development GmbH
  6. * Copyright (C) 2008-2009 Avionic Design GmbH
  7. * Thierry Reding <thierry.reding@avionic-design.de>
  8. * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
  9. * Copyright (C) 2016 Cadence Design Systems Inc.
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <dm/platform_data/net_ethoc.h>
  14. #include <linux/io.h>
  15. #include <malloc.h>
  16. #include <net.h>
  17. #include <miiphy.h>
  18. #include <asm/cache.h>
  19. #include <wait_bit.h>
  20. /* register offsets */
  21. #define MODER 0x00
  22. #define INT_SOURCE 0x04
  23. #define INT_MASK 0x08
  24. #define IPGT 0x0c
  25. #define IPGR1 0x10
  26. #define IPGR2 0x14
  27. #define PACKETLEN 0x18
  28. #define COLLCONF 0x1c
  29. #define TX_BD_NUM 0x20
  30. #define CTRLMODER 0x24
  31. #define MIIMODER 0x28
  32. #define MIICOMMAND 0x2c
  33. #define MIIADDRESS 0x30
  34. #define MIITX_DATA 0x34
  35. #define MIIRX_DATA 0x38
  36. #define MIISTATUS 0x3c
  37. #define MAC_ADDR0 0x40
  38. #define MAC_ADDR1 0x44
  39. #define ETH_HASH0 0x48
  40. #define ETH_HASH1 0x4c
  41. #define ETH_TXCTRL 0x50
  42. /* mode register */
  43. #define MODER_RXEN (1 << 0) /* receive enable */
  44. #define MODER_TXEN (1 << 1) /* transmit enable */
  45. #define MODER_NOPRE (1 << 2) /* no preamble */
  46. #define MODER_BRO (1 << 3) /* broadcast address */
  47. #define MODER_IAM (1 << 4) /* individual address mode */
  48. #define MODER_PRO (1 << 5) /* promiscuous mode */
  49. #define MODER_IFG (1 << 6) /* interframe gap for incoming frames */
  50. #define MODER_LOOP (1 << 7) /* loopback */
  51. #define MODER_NBO (1 << 8) /* no back-off */
  52. #define MODER_EDE (1 << 9) /* excess defer enable */
  53. #define MODER_FULLD (1 << 10) /* full duplex */
  54. #define MODER_RESET (1 << 11) /* FIXME: reset (undocumented) */
  55. #define MODER_DCRC (1 << 12) /* delayed CRC enable */
  56. #define MODER_CRC (1 << 13) /* CRC enable */
  57. #define MODER_HUGE (1 << 14) /* huge packets enable */
  58. #define MODER_PAD (1 << 15) /* padding enabled */
  59. #define MODER_RSM (1 << 16) /* receive small packets */
  60. /* interrupt source and mask registers */
  61. #define INT_MASK_TXF (1 << 0) /* transmit frame */
  62. #define INT_MASK_TXE (1 << 1) /* transmit error */
  63. #define INT_MASK_RXF (1 << 2) /* receive frame */
  64. #define INT_MASK_RXE (1 << 3) /* receive error */
  65. #define INT_MASK_BUSY (1 << 4)
  66. #define INT_MASK_TXC (1 << 5) /* transmit control frame */
  67. #define INT_MASK_RXC (1 << 6) /* receive control frame */
  68. #define INT_MASK_TX (INT_MASK_TXF | INT_MASK_TXE)
  69. #define INT_MASK_RX (INT_MASK_RXF | INT_MASK_RXE)
  70. #define INT_MASK_ALL ( \
  71. INT_MASK_TXF | INT_MASK_TXE | \
  72. INT_MASK_RXF | INT_MASK_RXE | \
  73. INT_MASK_TXC | INT_MASK_RXC | \
  74. INT_MASK_BUSY \
  75. )
  76. /* packet length register */
  77. #define PACKETLEN_MIN(min) (((min) & 0xffff) << 16)
  78. #define PACKETLEN_MAX(max) (((max) & 0xffff) << 0)
  79. #define PACKETLEN_MIN_MAX(min, max) (PACKETLEN_MIN(min) | \
  80. PACKETLEN_MAX(max))
  81. /* transmit buffer number register */
  82. #define TX_BD_NUM_VAL(x) (((x) <= 0x80) ? (x) : 0x80)
  83. /* control module mode register */
  84. #define CTRLMODER_PASSALL (1 << 0) /* pass all receive frames */
  85. #define CTRLMODER_RXFLOW (1 << 1) /* receive control flow */
  86. #define CTRLMODER_TXFLOW (1 << 2) /* transmit control flow */
  87. /* MII mode register */
  88. #define MIIMODER_CLKDIV(x) ((x) & 0xfe) /* needs to be an even number */
  89. #define MIIMODER_NOPRE (1 << 8) /* no preamble */
  90. /* MII command register */
  91. #define MIICOMMAND_SCAN (1 << 0) /* scan status */
  92. #define MIICOMMAND_READ (1 << 1) /* read status */
  93. #define MIICOMMAND_WRITE (1 << 2) /* write control data */
  94. /* MII address register */
  95. #define MIIADDRESS_FIAD(x) (((x) & 0x1f) << 0)
  96. #define MIIADDRESS_RGAD(x) (((x) & 0x1f) << 8)
  97. #define MIIADDRESS_ADDR(phy, reg) (MIIADDRESS_FIAD(phy) | \
  98. MIIADDRESS_RGAD(reg))
  99. /* MII transmit data register */
  100. #define MIITX_DATA_VAL(x) ((x) & 0xffff)
  101. /* MII receive data register */
  102. #define MIIRX_DATA_VAL(x) ((x) & 0xffff)
  103. /* MII status register */
  104. #define MIISTATUS_LINKFAIL (1 << 0)
  105. #define MIISTATUS_BUSY (1 << 1)
  106. #define MIISTATUS_INVALID (1 << 2)
  107. /* TX buffer descriptor */
  108. #define TX_BD_CS (1 << 0) /* carrier sense lost */
  109. #define TX_BD_DF (1 << 1) /* defer indication */
  110. #define TX_BD_LC (1 << 2) /* late collision */
  111. #define TX_BD_RL (1 << 3) /* retransmission limit */
  112. #define TX_BD_RETRY_MASK (0x00f0)
  113. #define TX_BD_RETRY(x) (((x) & 0x00f0) >> 4)
  114. #define TX_BD_UR (1 << 8) /* transmitter underrun */
  115. #define TX_BD_CRC (1 << 11) /* TX CRC enable */
  116. #define TX_BD_PAD (1 << 12) /* pad enable */
  117. #define TX_BD_WRAP (1 << 13)
  118. #define TX_BD_IRQ (1 << 14) /* interrupt request enable */
  119. #define TX_BD_READY (1 << 15) /* TX buffer ready */
  120. #define TX_BD_LEN(x) (((x) & 0xffff) << 16)
  121. #define TX_BD_LEN_MASK (0xffff << 16)
  122. #define TX_BD_STATS (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
  123. TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
  124. /* RX buffer descriptor */
  125. #define RX_BD_LC (1 << 0) /* late collision */
  126. #define RX_BD_CRC (1 << 1) /* RX CRC error */
  127. #define RX_BD_SF (1 << 2) /* short frame */
  128. #define RX_BD_TL (1 << 3) /* too long */
  129. #define RX_BD_DN (1 << 4) /* dribble nibble */
  130. #define RX_BD_IS (1 << 5) /* invalid symbol */
  131. #define RX_BD_OR (1 << 6) /* receiver overrun */
  132. #define RX_BD_MISS (1 << 7)
  133. #define RX_BD_CF (1 << 8) /* control frame */
  134. #define RX_BD_WRAP (1 << 13)
  135. #define RX_BD_IRQ (1 << 14) /* interrupt request enable */
  136. #define RX_BD_EMPTY (1 << 15)
  137. #define RX_BD_LEN(x) (((x) & 0xffff) << 16)
  138. #define RX_BD_STATS (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
  139. RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
  140. #define ETHOC_BUFSIZ 1536
  141. #define ETHOC_ZLEN 64
  142. #define ETHOC_BD_BASE 0x400
  143. #define ETHOC_TIMEOUT (HZ / 2)
  144. #define ETHOC_MII_TIMEOUT (1 + (HZ / 5))
  145. #define ETHOC_IOSIZE 0x54
  146. /**
  147. * struct ethoc - driver-private device structure
  148. * @num_tx: number of send buffers
  149. * @cur_tx: last send buffer written
  150. * @dty_tx: last buffer actually sent
  151. * @num_rx: number of receive buffers
  152. * @cur_rx: current receive buffer
  153. */
  154. struct ethoc {
  155. u32 num_tx;
  156. u32 cur_tx;
  157. u32 dty_tx;
  158. u32 num_rx;
  159. u32 cur_rx;
  160. void __iomem *iobase;
  161. void __iomem *packet;
  162. phys_addr_t packet_phys;
  163. #ifdef CONFIG_PHYLIB
  164. struct mii_dev *bus;
  165. struct phy_device *phydev;
  166. #endif
  167. };
  168. /**
  169. * struct ethoc_bd - buffer descriptor
  170. * @stat: buffer statistics
  171. * @addr: physical memory address
  172. */
  173. struct ethoc_bd {
  174. u32 stat;
  175. u32 addr;
  176. };
  177. static inline u32 *ethoc_reg(struct ethoc *priv, size_t offset)
  178. {
  179. return priv->iobase + offset;
  180. }
  181. static inline u32 ethoc_read(struct ethoc *priv, size_t offset)
  182. {
  183. return readl(ethoc_reg(priv, offset));
  184. }
  185. static inline void ethoc_write(struct ethoc *priv, size_t offset, u32 data)
  186. {
  187. writel(data, ethoc_reg(priv, offset));
  188. }
  189. static inline void ethoc_read_bd(struct ethoc *priv, int index,
  190. struct ethoc_bd *bd)
  191. {
  192. size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
  193. bd->stat = ethoc_read(priv, offset + 0);
  194. bd->addr = ethoc_read(priv, offset + 4);
  195. }
  196. static inline void ethoc_write_bd(struct ethoc *priv, int index,
  197. const struct ethoc_bd *bd)
  198. {
  199. size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
  200. ethoc_write(priv, offset + 0, bd->stat);
  201. ethoc_write(priv, offset + 4, bd->addr);
  202. }
  203. static int ethoc_write_hwaddr_common(struct ethoc *priv, u8 *mac)
  204. {
  205. ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
  206. (mac[4] << 8) | (mac[5] << 0));
  207. ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0));
  208. return 0;
  209. }
  210. static inline void ethoc_ack_irq(struct ethoc *priv, u32 mask)
  211. {
  212. ethoc_write(priv, INT_SOURCE, mask);
  213. }
  214. static inline void ethoc_enable_rx_and_tx(struct ethoc *priv)
  215. {
  216. u32 mode = ethoc_read(priv, MODER);
  217. mode |= MODER_RXEN | MODER_TXEN;
  218. ethoc_write(priv, MODER, mode);
  219. }
  220. static inline void ethoc_disable_rx_and_tx(struct ethoc *priv)
  221. {
  222. u32 mode = ethoc_read(priv, MODER);
  223. mode &= ~(MODER_RXEN | MODER_TXEN);
  224. ethoc_write(priv, MODER, mode);
  225. }
  226. static int ethoc_init_ring(struct ethoc *priv)
  227. {
  228. struct ethoc_bd bd;
  229. phys_addr_t addr = priv->packet_phys;
  230. int i;
  231. priv->cur_tx = 0;
  232. priv->dty_tx = 0;
  233. priv->cur_rx = 0;
  234. /* setup transmission buffers */
  235. bd.stat = TX_BD_IRQ | TX_BD_CRC;
  236. bd.addr = 0;
  237. for (i = 0; i < priv->num_tx; i++) {
  238. if (addr) {
  239. bd.addr = addr;
  240. addr += PKTSIZE_ALIGN;
  241. }
  242. if (i == priv->num_tx - 1)
  243. bd.stat |= TX_BD_WRAP;
  244. ethoc_write_bd(priv, i, &bd);
  245. }
  246. bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
  247. for (i = 0; i < priv->num_rx; i++) {
  248. if (addr) {
  249. bd.addr = addr;
  250. addr += PKTSIZE_ALIGN;
  251. } else {
  252. bd.addr = virt_to_phys(net_rx_packets[i]);
  253. }
  254. if (i == priv->num_rx - 1)
  255. bd.stat |= RX_BD_WRAP;
  256. flush_dcache_range((ulong)net_rx_packets[i],
  257. (ulong)net_rx_packets[i] + PKTSIZE_ALIGN);
  258. ethoc_write_bd(priv, priv->num_tx + i, &bd);
  259. }
  260. return 0;
  261. }
  262. static int ethoc_reset(struct ethoc *priv)
  263. {
  264. u32 mode;
  265. /* TODO: reset controller? */
  266. ethoc_disable_rx_and_tx(priv);
  267. /* TODO: setup registers */
  268. /* enable FCS generation and automatic padding */
  269. mode = ethoc_read(priv, MODER);
  270. mode |= MODER_CRC | MODER_PAD;
  271. ethoc_write(priv, MODER, mode);
  272. /* set full-duplex mode */
  273. mode = ethoc_read(priv, MODER);
  274. mode |= MODER_FULLD;
  275. ethoc_write(priv, MODER, mode);
  276. ethoc_write(priv, IPGT, 0x15);
  277. ethoc_ack_irq(priv, INT_MASK_ALL);
  278. ethoc_enable_rx_and_tx(priv);
  279. return 0;
  280. }
  281. static int ethoc_init_common(struct ethoc *priv)
  282. {
  283. int ret = 0;
  284. priv->num_tx = 1;
  285. priv->num_rx = PKTBUFSRX;
  286. ethoc_write(priv, TX_BD_NUM, priv->num_tx);
  287. ethoc_init_ring(priv);
  288. ethoc_reset(priv);
  289. #ifdef CONFIG_PHYLIB
  290. ret = phy_startup(priv->phydev);
  291. if (ret) {
  292. printf("Could not initialize PHY %s\n",
  293. priv->phydev->dev->name);
  294. return ret;
  295. }
  296. #endif
  297. return ret;
  298. }
  299. static void ethoc_stop_common(struct ethoc *priv)
  300. {
  301. ethoc_disable_rx_and_tx(priv);
  302. #ifdef CONFIG_PHYLIB
  303. phy_shutdown(priv->phydev);
  304. #endif
  305. }
  306. static int ethoc_update_rx_stats(struct ethoc_bd *bd)
  307. {
  308. int ret = 0;
  309. if (bd->stat & RX_BD_TL) {
  310. debug("ETHOC: " "RX: frame too long\n");
  311. ret++;
  312. }
  313. if (bd->stat & RX_BD_SF) {
  314. debug("ETHOC: " "RX: frame too short\n");
  315. ret++;
  316. }
  317. if (bd->stat & RX_BD_DN)
  318. debug("ETHOC: " "RX: dribble nibble\n");
  319. if (bd->stat & RX_BD_CRC) {
  320. debug("ETHOC: " "RX: wrong CRC\n");
  321. ret++;
  322. }
  323. if (bd->stat & RX_BD_OR) {
  324. debug("ETHOC: " "RX: overrun\n");
  325. ret++;
  326. }
  327. if (bd->stat & RX_BD_LC) {
  328. debug("ETHOC: " "RX: late collision\n");
  329. ret++;
  330. }
  331. return ret;
  332. }
  333. static int ethoc_rx_common(struct ethoc *priv, uchar **packetp)
  334. {
  335. struct ethoc_bd bd;
  336. u32 i = priv->cur_rx % priv->num_rx;
  337. u32 entry = priv->num_tx + i;
  338. ethoc_read_bd(priv, entry, &bd);
  339. if (bd.stat & RX_BD_EMPTY)
  340. return -EAGAIN;
  341. debug("%s(): RX buffer %d, %x received\n",
  342. __func__, priv->cur_rx, bd.stat);
  343. if (ethoc_update_rx_stats(&bd) == 0) {
  344. int size = bd.stat >> 16;
  345. size -= 4; /* strip the CRC */
  346. if (priv->packet)
  347. *packetp = priv->packet + entry * PKTSIZE_ALIGN;
  348. else
  349. *packetp = net_rx_packets[i];
  350. return size;
  351. } else {
  352. return 0;
  353. }
  354. }
  355. static int ethoc_is_new_packet_received(struct ethoc *priv)
  356. {
  357. u32 pending;
  358. pending = ethoc_read(priv, INT_SOURCE);
  359. ethoc_ack_irq(priv, pending);
  360. if (pending & INT_MASK_BUSY)
  361. debug("%s(): packet dropped\n", __func__);
  362. if (pending & INT_MASK_RX) {
  363. debug("%s(): rx irq\n", __func__);
  364. return 1;
  365. }
  366. return 0;
  367. }
  368. static int ethoc_update_tx_stats(struct ethoc_bd *bd)
  369. {
  370. if (bd->stat & TX_BD_LC)
  371. debug("ETHOC: " "TX: late collision\n");
  372. if (bd->stat & TX_BD_RL)
  373. debug("ETHOC: " "TX: retransmit limit\n");
  374. if (bd->stat & TX_BD_UR)
  375. debug("ETHOC: " "TX: underrun\n");
  376. if (bd->stat & TX_BD_CS)
  377. debug("ETHOC: " "TX: carrier sense lost\n");
  378. return 0;
  379. }
  380. static void ethoc_tx(struct ethoc *priv)
  381. {
  382. u32 entry = priv->dty_tx % priv->num_tx;
  383. struct ethoc_bd bd;
  384. ethoc_read_bd(priv, entry, &bd);
  385. if ((bd.stat & TX_BD_READY) == 0)
  386. (void)ethoc_update_tx_stats(&bd);
  387. }
  388. static int ethoc_send_common(struct ethoc *priv, void *packet, int length)
  389. {
  390. struct ethoc_bd bd;
  391. u32 entry;
  392. u32 pending;
  393. int tmo;
  394. entry = priv->cur_tx % priv->num_tx;
  395. ethoc_read_bd(priv, entry, &bd);
  396. if (unlikely(length < ETHOC_ZLEN))
  397. bd.stat |= TX_BD_PAD;
  398. else
  399. bd.stat &= ~TX_BD_PAD;
  400. if (priv->packet) {
  401. void *p = priv->packet + entry * PKTSIZE_ALIGN;
  402. memcpy(p, packet, length);
  403. packet = p;
  404. } else {
  405. bd.addr = virt_to_phys(packet);
  406. }
  407. flush_dcache_range((ulong)packet, (ulong)packet + length);
  408. bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
  409. bd.stat |= TX_BD_LEN(length);
  410. ethoc_write_bd(priv, entry, &bd);
  411. /* start transmit */
  412. bd.stat |= TX_BD_READY;
  413. ethoc_write_bd(priv, entry, &bd);
  414. /* wait for transfer to succeed */
  415. tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
  416. while (1) {
  417. pending = ethoc_read(priv, INT_SOURCE);
  418. ethoc_ack_irq(priv, pending & ~INT_MASK_RX);
  419. if (pending & INT_MASK_BUSY)
  420. debug("%s(): packet dropped\n", __func__);
  421. if (pending & INT_MASK_TX) {
  422. ethoc_tx(priv);
  423. break;
  424. }
  425. if (get_timer(0) >= tmo) {
  426. debug("%s(): timed out\n", __func__);
  427. return -1;
  428. }
  429. }
  430. debug("%s(): packet sent\n", __func__);
  431. return 0;
  432. }
  433. static int ethoc_free_pkt_common(struct ethoc *priv)
  434. {
  435. struct ethoc_bd bd;
  436. u32 i = priv->cur_rx % priv->num_rx;
  437. u32 entry = priv->num_tx + i;
  438. void *src;
  439. ethoc_read_bd(priv, entry, &bd);
  440. if (priv->packet)
  441. src = priv->packet + entry * PKTSIZE_ALIGN;
  442. else
  443. src = net_rx_packets[i];
  444. /* clear the buffer descriptor so it can be reused */
  445. flush_dcache_range((ulong)src,
  446. (ulong)src + PKTSIZE_ALIGN);
  447. bd.stat &= ~RX_BD_STATS;
  448. bd.stat |= RX_BD_EMPTY;
  449. ethoc_write_bd(priv, entry, &bd);
  450. priv->cur_rx++;
  451. return 0;
  452. }
  453. #ifdef CONFIG_PHYLIB
  454. static int ethoc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  455. {
  456. struct ethoc *priv = bus->priv;
  457. int rc;
  458. ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(addr, reg));
  459. ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
  460. rc = wait_for_bit_le32(ethoc_reg(priv, MIISTATUS),
  461. MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
  462. if (rc == 0) {
  463. u32 data = ethoc_read(priv, MIIRX_DATA);
  464. /* reset MII command register */
  465. ethoc_write(priv, MIICOMMAND, 0);
  466. return data;
  467. }
  468. return rc;
  469. }
  470. static int ethoc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  471. u16 val)
  472. {
  473. struct ethoc *priv = bus->priv;
  474. int rc;
  475. ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(addr, reg));
  476. ethoc_write(priv, MIITX_DATA, val);
  477. ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
  478. rc = wait_for_bit_le32(ethoc_reg(priv, MIISTATUS),
  479. MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false);
  480. if (rc == 0) {
  481. /* reset MII command register */
  482. ethoc_write(priv, MIICOMMAND, 0);
  483. }
  484. return rc;
  485. }
  486. static int ethoc_mdio_init(const char *name, struct ethoc *priv)
  487. {
  488. struct mii_dev *bus = mdio_alloc();
  489. int ret;
  490. if (!bus) {
  491. printf("Failed to allocate MDIO bus\n");
  492. return -ENOMEM;
  493. }
  494. bus->read = ethoc_mdio_read;
  495. bus->write = ethoc_mdio_write;
  496. snprintf(bus->name, sizeof(bus->name), "%s", name);
  497. bus->priv = priv;
  498. ret = mdio_register(bus);
  499. if (ret < 0)
  500. return ret;
  501. priv->bus = miiphy_get_dev_by_name(name);
  502. return 0;
  503. }
  504. static int ethoc_phy_init(struct ethoc *priv, void *dev)
  505. {
  506. struct phy_device *phydev;
  507. int mask = 0xffffffff;
  508. #ifdef CONFIG_PHY_ADDR
  509. mask = 1 << CONFIG_PHY_ADDR;
  510. #endif
  511. phydev = phy_find_by_mask(priv->bus, mask, PHY_INTERFACE_MODE_MII);
  512. if (!phydev)
  513. return -ENODEV;
  514. phy_connect_dev(phydev, dev);
  515. phydev->supported &= PHY_BASIC_FEATURES;
  516. phydev->advertising = phydev->supported;
  517. priv->phydev = phydev;
  518. phy_config(phydev);
  519. return 0;
  520. }
  521. #else
  522. static inline int ethoc_mdio_init(const char *name, struct ethoc *priv)
  523. {
  524. return 0;
  525. }
  526. static inline int ethoc_phy_init(struct ethoc *priv, void *dev)
  527. {
  528. return 0;
  529. }
  530. #endif
  531. #ifdef CONFIG_DM_ETH
  532. static int ethoc_write_hwaddr(struct udevice *dev)
  533. {
  534. struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
  535. struct ethoc *priv = dev_get_priv(dev);
  536. u8 *mac = pdata->eth_pdata.enetaddr;
  537. return ethoc_write_hwaddr_common(priv, mac);
  538. }
  539. static int ethoc_send(struct udevice *dev, void *packet, int length)
  540. {
  541. return ethoc_send_common(dev_get_priv(dev), packet, length);
  542. }
  543. static int ethoc_free_pkt(struct udevice *dev, uchar *packet, int length)
  544. {
  545. return ethoc_free_pkt_common(dev_get_priv(dev));
  546. }
  547. static int ethoc_recv(struct udevice *dev, int flags, uchar **packetp)
  548. {
  549. struct ethoc *priv = dev_get_priv(dev);
  550. if (flags & ETH_RECV_CHECK_DEVICE)
  551. if (!ethoc_is_new_packet_received(priv))
  552. return -EAGAIN;
  553. return ethoc_rx_common(priv, packetp);
  554. }
  555. static int ethoc_start(struct udevice *dev)
  556. {
  557. return ethoc_init_common(dev_get_priv(dev));
  558. }
  559. static void ethoc_stop(struct udevice *dev)
  560. {
  561. ethoc_stop_common(dev_get_priv(dev));
  562. }
  563. static int ethoc_ofdata_to_platdata(struct udevice *dev)
  564. {
  565. struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
  566. fdt_addr_t addr;
  567. pdata->eth_pdata.iobase = devfdt_get_addr(dev);
  568. addr = devfdt_get_addr_index(dev, 1);
  569. if (addr != FDT_ADDR_T_NONE)
  570. pdata->packet_base = addr;
  571. return 0;
  572. }
  573. static int ethoc_probe(struct udevice *dev)
  574. {
  575. struct ethoc_eth_pdata *pdata = dev_get_platdata(dev);
  576. struct ethoc *priv = dev_get_priv(dev);
  577. priv->iobase = ioremap(pdata->eth_pdata.iobase, ETHOC_IOSIZE);
  578. if (pdata->packet_base) {
  579. priv->packet_phys = pdata->packet_base;
  580. priv->packet = ioremap(pdata->packet_base,
  581. (1 + PKTBUFSRX) * PKTSIZE_ALIGN);
  582. }
  583. ethoc_mdio_init(dev->name, priv);
  584. ethoc_phy_init(priv, dev);
  585. return 0;
  586. }
  587. static int ethoc_remove(struct udevice *dev)
  588. {
  589. struct ethoc *priv = dev_get_priv(dev);
  590. #ifdef CONFIG_PHYLIB
  591. free(priv->phydev);
  592. mdio_unregister(priv->bus);
  593. mdio_free(priv->bus);
  594. #endif
  595. iounmap(priv->iobase);
  596. return 0;
  597. }
  598. static const struct eth_ops ethoc_ops = {
  599. .start = ethoc_start,
  600. .stop = ethoc_stop,
  601. .send = ethoc_send,
  602. .recv = ethoc_recv,
  603. .free_pkt = ethoc_free_pkt,
  604. .write_hwaddr = ethoc_write_hwaddr,
  605. };
  606. static const struct udevice_id ethoc_ids[] = {
  607. { .compatible = "opencores,ethoc" },
  608. { }
  609. };
  610. U_BOOT_DRIVER(ethoc) = {
  611. .name = "ethoc",
  612. .id = UCLASS_ETH,
  613. .of_match = ethoc_ids,
  614. .ofdata_to_platdata = ethoc_ofdata_to_platdata,
  615. .probe = ethoc_probe,
  616. .remove = ethoc_remove,
  617. .ops = &ethoc_ops,
  618. .priv_auto_alloc_size = sizeof(struct ethoc),
  619. .platdata_auto_alloc_size = sizeof(struct ethoc_eth_pdata),
  620. };
  621. #else
  622. static int ethoc_init(struct eth_device *dev, bd_t *bd)
  623. {
  624. struct ethoc *priv = (struct ethoc *)dev->priv;
  625. return ethoc_init_common(priv);
  626. }
  627. static int ethoc_write_hwaddr(struct eth_device *dev)
  628. {
  629. struct ethoc *priv = (struct ethoc *)dev->priv;
  630. u8 *mac = dev->enetaddr;
  631. return ethoc_write_hwaddr_common(priv, mac);
  632. }
  633. static int ethoc_send(struct eth_device *dev, void *packet, int length)
  634. {
  635. return ethoc_send_common(dev->priv, packet, length);
  636. }
  637. static void ethoc_halt(struct eth_device *dev)
  638. {
  639. ethoc_disable_rx_and_tx(dev->priv);
  640. }
  641. static int ethoc_recv(struct eth_device *dev)
  642. {
  643. struct ethoc *priv = (struct ethoc *)dev->priv;
  644. int count;
  645. if (!ethoc_is_new_packet_received(priv))
  646. return 0;
  647. for (count = 0; count < PKTBUFSRX; ++count) {
  648. uchar *packetp;
  649. int size = ethoc_rx_common(priv, &packetp);
  650. if (size < 0)
  651. break;
  652. if (size > 0)
  653. net_process_received_packet(packetp, size);
  654. ethoc_free_pkt_common(priv);
  655. }
  656. return 0;
  657. }
  658. int ethoc_initialize(u8 dev_num, int base_addr)
  659. {
  660. struct ethoc *priv;
  661. struct eth_device *dev;
  662. priv = malloc(sizeof(*priv));
  663. if (!priv)
  664. return 0;
  665. dev = malloc(sizeof(*dev));
  666. if (!dev) {
  667. free(priv);
  668. return 0;
  669. }
  670. memset(dev, 0, sizeof(*dev));
  671. dev->priv = priv;
  672. dev->iobase = base_addr;
  673. dev->init = ethoc_init;
  674. dev->halt = ethoc_halt;
  675. dev->send = ethoc_send;
  676. dev->recv = ethoc_recv;
  677. dev->write_hwaddr = ethoc_write_hwaddr;
  678. sprintf(dev->name, "%s-%hu", "ETHOC", dev_num);
  679. priv->iobase = ioremap(dev->iobase, ETHOC_IOSIZE);
  680. eth_register(dev);
  681. ethoc_mdio_init(dev->name, priv);
  682. ethoc_phy_init(priv, dev);
  683. return 1;
  684. }
  685. #endif