designware.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. */
  6. /*
  7. * Designware ethernet IP driver for U-Boot
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <miiphy.h>
  14. #include <malloc.h>
  15. #include <pci.h>
  16. #include <reset.h>
  17. #include <linux/compiler.h>
  18. #include <linux/err.h>
  19. #include <linux/kernel.h>
  20. #include <asm/io.h>
  21. #include <power/regulator.h>
  22. #include "designware.h"
  23. static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  24. {
  25. #ifdef CONFIG_DM_ETH
  26. struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
  27. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  28. #else
  29. struct eth_mac_regs *mac_p = bus->priv;
  30. #endif
  31. ulong start;
  32. u16 miiaddr;
  33. int timeout = CONFIG_MDIO_TIMEOUT;
  34. miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
  35. ((reg << MIIREGSHIFT) & MII_REGMSK);
  36. writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
  37. start = get_timer(0);
  38. while (get_timer(start) < timeout) {
  39. if (!(readl(&mac_p->miiaddr) & MII_BUSY))
  40. return readl(&mac_p->miidata);
  41. udelay(10);
  42. };
  43. return -ETIMEDOUT;
  44. }
  45. static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  46. u16 val)
  47. {
  48. #ifdef CONFIG_DM_ETH
  49. struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
  50. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  51. #else
  52. struct eth_mac_regs *mac_p = bus->priv;
  53. #endif
  54. ulong start;
  55. u16 miiaddr;
  56. int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
  57. writel(val, &mac_p->miidata);
  58. miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
  59. ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
  60. writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
  61. start = get_timer(0);
  62. while (get_timer(start) < timeout) {
  63. if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
  64. ret = 0;
  65. break;
  66. }
  67. udelay(10);
  68. };
  69. return ret;
  70. }
  71. #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
  72. static int dw_mdio_reset(struct mii_dev *bus)
  73. {
  74. struct udevice *dev = bus->priv;
  75. struct dw_eth_dev *priv = dev_get_priv(dev);
  76. struct dw_eth_pdata *pdata = dev_get_platdata(dev);
  77. int ret;
  78. if (!dm_gpio_is_valid(&priv->reset_gpio))
  79. return 0;
  80. /* reset the phy */
  81. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  82. if (ret)
  83. return ret;
  84. udelay(pdata->reset_delays[0]);
  85. ret = dm_gpio_set_value(&priv->reset_gpio, 1);
  86. if (ret)
  87. return ret;
  88. udelay(pdata->reset_delays[1]);
  89. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  90. if (ret)
  91. return ret;
  92. udelay(pdata->reset_delays[2]);
  93. return 0;
  94. }
  95. #endif
  96. static int dw_mdio_init(const char *name, void *priv)
  97. {
  98. struct mii_dev *bus = mdio_alloc();
  99. if (!bus) {
  100. printf("Failed to allocate MDIO bus\n");
  101. return -ENOMEM;
  102. }
  103. bus->read = dw_mdio_read;
  104. bus->write = dw_mdio_write;
  105. snprintf(bus->name, sizeof(bus->name), "%s", name);
  106. #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO)
  107. bus->reset = dw_mdio_reset;
  108. #endif
  109. bus->priv = priv;
  110. return mdio_register(bus);
  111. }
  112. static void tx_descs_init(struct dw_eth_dev *priv)
  113. {
  114. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  115. struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
  116. char *txbuffs = &priv->txbuffs[0];
  117. struct dmamacdescr *desc_p;
  118. u32 idx;
  119. for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
  120. desc_p = &desc_table_p[idx];
  121. desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
  122. desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
  123. #if defined(CONFIG_DW_ALTDESCRIPTOR)
  124. desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
  125. DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
  126. DESC_TXSTS_TXCHECKINSCTRL |
  127. DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
  128. desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
  129. desc_p->dmamac_cntl = 0;
  130. desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
  131. #else
  132. desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
  133. desc_p->txrx_status = 0;
  134. #endif
  135. }
  136. /* Correcting the last pointer of the chain */
  137. desc_p->dmamac_next = (ulong)&desc_table_p[0];
  138. /* Flush all Tx buffer descriptors at once */
  139. flush_dcache_range((ulong)priv->tx_mac_descrtable,
  140. (ulong)priv->tx_mac_descrtable +
  141. sizeof(priv->tx_mac_descrtable));
  142. writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
  143. priv->tx_currdescnum = 0;
  144. }
  145. static void rx_descs_init(struct dw_eth_dev *priv)
  146. {
  147. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  148. struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
  149. char *rxbuffs = &priv->rxbuffs[0];
  150. struct dmamacdescr *desc_p;
  151. u32 idx;
  152. /* Before passing buffers to GMAC we need to make sure zeros
  153. * written there right after "priv" structure allocation were
  154. * flushed into RAM.
  155. * Otherwise there's a chance to get some of them flushed in RAM when
  156. * GMAC is already pushing data to RAM via DMA. This way incoming from
  157. * GMAC data will be corrupted. */
  158. flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
  159. for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
  160. desc_p = &desc_table_p[idx];
  161. desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
  162. desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
  163. desc_p->dmamac_cntl =
  164. (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
  165. DESC_RXCTRL_RXCHAIN;
  166. desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
  167. }
  168. /* Correcting the last pointer of the chain */
  169. desc_p->dmamac_next = (ulong)&desc_table_p[0];
  170. /* Flush all Rx buffer descriptors at once */
  171. flush_dcache_range((ulong)priv->rx_mac_descrtable,
  172. (ulong)priv->rx_mac_descrtable +
  173. sizeof(priv->rx_mac_descrtable));
  174. writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
  175. priv->rx_currdescnum = 0;
  176. }
  177. static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
  178. {
  179. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  180. u32 macid_lo, macid_hi;
  181. macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
  182. (mac_id[3] << 24);
  183. macid_hi = mac_id[4] + (mac_id[5] << 8);
  184. writel(macid_hi, &mac_p->macaddr0hi);
  185. writel(macid_lo, &mac_p->macaddr0lo);
  186. return 0;
  187. }
  188. static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
  189. struct phy_device *phydev)
  190. {
  191. u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
  192. if (!phydev->link) {
  193. printf("%s: No link.\n", phydev->dev->name);
  194. return 0;
  195. }
  196. if (phydev->speed != 1000)
  197. conf |= MII_PORTSELECT;
  198. else
  199. conf &= ~MII_PORTSELECT;
  200. if (phydev->speed == 100)
  201. conf |= FES_100;
  202. if (phydev->duplex)
  203. conf |= FULLDPLXMODE;
  204. writel(conf, &mac_p->conf);
  205. printf("Speed: %d, %s duplex%s\n", phydev->speed,
  206. (phydev->duplex) ? "full" : "half",
  207. (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
  208. return 0;
  209. }
  210. static void _dw_eth_halt(struct dw_eth_dev *priv)
  211. {
  212. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  213. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  214. writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
  215. writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
  216. phy_shutdown(priv->phydev);
  217. }
  218. int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
  219. {
  220. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  221. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  222. unsigned int start;
  223. int ret;
  224. writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
  225. /*
  226. * When a MII PHY is used, we must set the PS bit for the DMA
  227. * reset to succeed.
  228. */
  229. if (priv->phydev->interface == PHY_INTERFACE_MODE_MII)
  230. writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf);
  231. else
  232. writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf);
  233. start = get_timer(0);
  234. while (readl(&dma_p->busmode) & DMAMAC_SRST) {
  235. if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
  236. printf("DMA reset timeout\n");
  237. return -ETIMEDOUT;
  238. }
  239. mdelay(100);
  240. };
  241. /*
  242. * Soft reset above clears HW address registers.
  243. * So we have to set it here once again.
  244. */
  245. _dw_write_hwaddr(priv, enetaddr);
  246. rx_descs_init(priv);
  247. tx_descs_init(priv);
  248. writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
  249. #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
  250. writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
  251. &dma_p->opmode);
  252. #else
  253. writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
  254. &dma_p->opmode);
  255. #endif
  256. writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
  257. #ifdef CONFIG_DW_AXI_BURST_LEN
  258. writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
  259. #endif
  260. /* Start up the PHY */
  261. ret = phy_startup(priv->phydev);
  262. if (ret) {
  263. printf("Could not initialize PHY %s\n",
  264. priv->phydev->dev->name);
  265. return ret;
  266. }
  267. ret = dw_adjust_link(priv, mac_p, priv->phydev);
  268. if (ret)
  269. return ret;
  270. return 0;
  271. }
  272. int designware_eth_enable(struct dw_eth_dev *priv)
  273. {
  274. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  275. if (!priv->phydev->link)
  276. return -EIO;
  277. writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
  278. return 0;
  279. }
  280. #define ETH_ZLEN 60
  281. static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
  282. {
  283. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  284. u32 desc_num = priv->tx_currdescnum;
  285. struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
  286. ulong desc_start = (ulong)desc_p;
  287. ulong desc_end = desc_start +
  288. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  289. ulong data_start = desc_p->dmamac_addr;
  290. ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
  291. /*
  292. * Strictly we only need to invalidate the "txrx_status" field
  293. * for the following check, but on some platforms we cannot
  294. * invalidate only 4 bytes, so we flush the entire descriptor,
  295. * which is 16 bytes in total. This is safe because the
  296. * individual descriptors in the array are each aligned to
  297. * ARCH_DMA_MINALIGN and padded appropriately.
  298. */
  299. invalidate_dcache_range(desc_start, desc_end);
  300. /* Check if the descriptor is owned by CPU */
  301. if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
  302. printf("CPU not owner of tx frame\n");
  303. return -EPERM;
  304. }
  305. memcpy((void *)data_start, packet, length);
  306. if (length < ETH_ZLEN) {
  307. memset(&((char *)data_start)[length], 0, ETH_ZLEN - length);
  308. length = ETH_ZLEN;
  309. }
  310. /* Flush data to be sent */
  311. flush_dcache_range(data_start, data_end);
  312. #if defined(CONFIG_DW_ALTDESCRIPTOR)
  313. desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
  314. desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
  315. ((length << DESC_TXCTRL_SIZE1SHFT) &
  316. DESC_TXCTRL_SIZE1MASK);
  317. desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
  318. desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
  319. #else
  320. desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
  321. ((length << DESC_TXCTRL_SIZE1SHFT) &
  322. DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
  323. DESC_TXCTRL_TXFIRST;
  324. desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
  325. #endif
  326. /* Flush modified buffer descriptor */
  327. flush_dcache_range(desc_start, desc_end);
  328. /* Test the wrap-around condition. */
  329. if (++desc_num >= CONFIG_TX_DESCR_NUM)
  330. desc_num = 0;
  331. priv->tx_currdescnum = desc_num;
  332. /* Start the transmission */
  333. writel(POLL_DATA, &dma_p->txpolldemand);
  334. return 0;
  335. }
  336. static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
  337. {
  338. u32 status, desc_num = priv->rx_currdescnum;
  339. struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
  340. int length = -EAGAIN;
  341. ulong desc_start = (ulong)desc_p;
  342. ulong desc_end = desc_start +
  343. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  344. ulong data_start = desc_p->dmamac_addr;
  345. ulong data_end;
  346. /* Invalidate entire buffer descriptor */
  347. invalidate_dcache_range(desc_start, desc_end);
  348. status = desc_p->txrx_status;
  349. /* Check if the owner is the CPU */
  350. if (!(status & DESC_RXSTS_OWNBYDMA)) {
  351. length = (status & DESC_RXSTS_FRMLENMSK) >>
  352. DESC_RXSTS_FRMLENSHFT;
  353. /* Invalidate received data */
  354. data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
  355. invalidate_dcache_range(data_start, data_end);
  356. *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
  357. }
  358. return length;
  359. }
  360. static int _dw_free_pkt(struct dw_eth_dev *priv)
  361. {
  362. u32 desc_num = priv->rx_currdescnum;
  363. struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
  364. ulong desc_start = (ulong)desc_p;
  365. ulong desc_end = desc_start +
  366. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  367. /*
  368. * Make the current descriptor valid again and go to
  369. * the next one
  370. */
  371. desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
  372. /* Flush only status field - others weren't changed */
  373. flush_dcache_range(desc_start, desc_end);
  374. /* Test the wrap-around condition. */
  375. if (++desc_num >= CONFIG_RX_DESCR_NUM)
  376. desc_num = 0;
  377. priv->rx_currdescnum = desc_num;
  378. return 0;
  379. }
  380. static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
  381. {
  382. struct phy_device *phydev;
  383. int phy_addr = -1, ret;
  384. #ifdef CONFIG_PHY_ADDR
  385. phy_addr = CONFIG_PHY_ADDR;
  386. #endif
  387. phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface);
  388. if (!phydev)
  389. return -ENODEV;
  390. phydev->supported &= PHY_GBIT_FEATURES;
  391. if (priv->max_speed) {
  392. ret = phy_set_supported(phydev, priv->max_speed);
  393. if (ret)
  394. return ret;
  395. }
  396. phydev->advertising = phydev->supported;
  397. priv->phydev = phydev;
  398. phy_config(phydev);
  399. return 0;
  400. }
  401. #ifndef CONFIG_DM_ETH
  402. static int dw_eth_init(struct eth_device *dev, bd_t *bis)
  403. {
  404. int ret;
  405. ret = designware_eth_init(dev->priv, dev->enetaddr);
  406. if (!ret)
  407. ret = designware_eth_enable(dev->priv);
  408. return ret;
  409. }
  410. static int dw_eth_send(struct eth_device *dev, void *packet, int length)
  411. {
  412. return _dw_eth_send(dev->priv, packet, length);
  413. }
  414. static int dw_eth_recv(struct eth_device *dev)
  415. {
  416. uchar *packet;
  417. int length;
  418. length = _dw_eth_recv(dev->priv, &packet);
  419. if (length == -EAGAIN)
  420. return 0;
  421. net_process_received_packet(packet, length);
  422. _dw_free_pkt(dev->priv);
  423. return 0;
  424. }
  425. static void dw_eth_halt(struct eth_device *dev)
  426. {
  427. return _dw_eth_halt(dev->priv);
  428. }
  429. static int dw_write_hwaddr(struct eth_device *dev)
  430. {
  431. return _dw_write_hwaddr(dev->priv, dev->enetaddr);
  432. }
  433. int designware_initialize(ulong base_addr, u32 interface)
  434. {
  435. struct eth_device *dev;
  436. struct dw_eth_dev *priv;
  437. dev = (struct eth_device *) malloc(sizeof(struct eth_device));
  438. if (!dev)
  439. return -ENOMEM;
  440. /*
  441. * Since the priv structure contains the descriptors which need a strict
  442. * buswidth alignment, memalign is used to allocate memory
  443. */
  444. priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
  445. sizeof(struct dw_eth_dev));
  446. if (!priv) {
  447. free(dev);
  448. return -ENOMEM;
  449. }
  450. if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
  451. printf("designware: buffers are outside DMA memory\n");
  452. return -EINVAL;
  453. }
  454. memset(dev, 0, sizeof(struct eth_device));
  455. memset(priv, 0, sizeof(struct dw_eth_dev));
  456. sprintf(dev->name, "dwmac.%lx", base_addr);
  457. dev->iobase = (int)base_addr;
  458. dev->priv = priv;
  459. priv->dev = dev;
  460. priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
  461. priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
  462. DW_DMA_BASE_OFFSET);
  463. dev->init = dw_eth_init;
  464. dev->send = dw_eth_send;
  465. dev->recv = dw_eth_recv;
  466. dev->halt = dw_eth_halt;
  467. dev->write_hwaddr = dw_write_hwaddr;
  468. eth_register(dev);
  469. priv->interface = interface;
  470. dw_mdio_init(dev->name, priv->mac_regs_p);
  471. priv->bus = miiphy_get_dev_by_name(dev->name);
  472. return dw_phy_init(priv, dev);
  473. }
  474. #endif
  475. #ifdef CONFIG_DM_ETH
  476. static int designware_eth_start(struct udevice *dev)
  477. {
  478. struct eth_pdata *pdata = dev_get_platdata(dev);
  479. struct dw_eth_dev *priv = dev_get_priv(dev);
  480. int ret;
  481. ret = designware_eth_init(priv, pdata->enetaddr);
  482. if (ret)
  483. return ret;
  484. ret = designware_eth_enable(priv);
  485. if (ret)
  486. return ret;
  487. return 0;
  488. }
  489. int designware_eth_send(struct udevice *dev, void *packet, int length)
  490. {
  491. struct dw_eth_dev *priv = dev_get_priv(dev);
  492. return _dw_eth_send(priv, packet, length);
  493. }
  494. int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  495. {
  496. struct dw_eth_dev *priv = dev_get_priv(dev);
  497. return _dw_eth_recv(priv, packetp);
  498. }
  499. int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
  500. {
  501. struct dw_eth_dev *priv = dev_get_priv(dev);
  502. return _dw_free_pkt(priv);
  503. }
  504. void designware_eth_stop(struct udevice *dev)
  505. {
  506. struct dw_eth_dev *priv = dev_get_priv(dev);
  507. return _dw_eth_halt(priv);
  508. }
  509. int designware_eth_write_hwaddr(struct udevice *dev)
  510. {
  511. struct eth_pdata *pdata = dev_get_platdata(dev);
  512. struct dw_eth_dev *priv = dev_get_priv(dev);
  513. return _dw_write_hwaddr(priv, pdata->enetaddr);
  514. }
  515. static int designware_eth_bind(struct udevice *dev)
  516. {
  517. #ifdef CONFIG_DM_PCI
  518. static int num_cards;
  519. char name[20];
  520. /* Create a unique device name for PCI type devices */
  521. if (device_is_on_pci_bus(dev)) {
  522. sprintf(name, "eth_designware#%u", num_cards++);
  523. device_set_name(dev, name);
  524. }
  525. #endif
  526. return 0;
  527. }
  528. int designware_eth_probe(struct udevice *dev)
  529. {
  530. struct eth_pdata *pdata = dev_get_platdata(dev);
  531. struct dw_eth_dev *priv = dev_get_priv(dev);
  532. u32 iobase = pdata->iobase;
  533. ulong ioaddr;
  534. int ret, err;
  535. struct reset_ctl_bulk reset_bulk;
  536. #ifdef CONFIG_CLK
  537. int i, clock_nb;
  538. priv->clock_count = 0;
  539. clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
  540. if (clock_nb > 0) {
  541. priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
  542. GFP_KERNEL);
  543. if (!priv->clocks)
  544. return -ENOMEM;
  545. for (i = 0; i < clock_nb; i++) {
  546. err = clk_get_by_index(dev, i, &priv->clocks[i]);
  547. if (err < 0)
  548. break;
  549. err = clk_enable(&priv->clocks[i]);
  550. if (err && err != -ENOSYS && err != -ENOTSUPP) {
  551. pr_err("failed to enable clock %d\n", i);
  552. clk_free(&priv->clocks[i]);
  553. goto clk_err;
  554. }
  555. priv->clock_count++;
  556. }
  557. } else if (clock_nb != -ENOENT) {
  558. pr_err("failed to get clock phandle(%d)\n", clock_nb);
  559. return clock_nb;
  560. }
  561. #endif
  562. #if defined(CONFIG_DM_REGULATOR)
  563. struct udevice *phy_supply;
  564. ret = device_get_supply_regulator(dev, "phy-supply",
  565. &phy_supply);
  566. if (ret) {
  567. debug("%s: No phy supply\n", dev->name);
  568. } else {
  569. ret = regulator_set_enable(phy_supply, true);
  570. if (ret) {
  571. puts("Error enabling phy supply\n");
  572. return ret;
  573. }
  574. }
  575. #endif
  576. ret = reset_get_bulk(dev, &reset_bulk);
  577. if (ret)
  578. dev_warn(dev, "Can't get reset: %d\n", ret);
  579. else
  580. reset_deassert_bulk(&reset_bulk);
  581. #ifdef CONFIG_DM_PCI
  582. /*
  583. * If we are on PCI bus, either directly attached to a PCI root port,
  584. * or via a PCI bridge, fill in platdata before we probe the hardware.
  585. */
  586. if (device_is_on_pci_bus(dev)) {
  587. dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
  588. iobase &= PCI_BASE_ADDRESS_MEM_MASK;
  589. iobase = dm_pci_mem_to_phys(dev, iobase);
  590. pdata->iobase = iobase;
  591. pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
  592. }
  593. #endif
  594. debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
  595. ioaddr = iobase;
  596. priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
  597. priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
  598. priv->interface = pdata->phy_interface;
  599. priv->max_speed = pdata->max_speed;
  600. ret = dw_mdio_init(dev->name, dev);
  601. if (ret) {
  602. err = ret;
  603. goto mdio_err;
  604. }
  605. priv->bus = miiphy_get_dev_by_name(dev->name);
  606. ret = dw_phy_init(priv, dev);
  607. debug("%s, ret=%d\n", __func__, ret);
  608. if (!ret)
  609. return 0;
  610. /* continue here for cleanup if no PHY found */
  611. err = ret;
  612. mdio_unregister(priv->bus);
  613. mdio_free(priv->bus);
  614. mdio_err:
  615. #ifdef CONFIG_CLK
  616. clk_err:
  617. ret = clk_release_all(priv->clocks, priv->clock_count);
  618. if (ret)
  619. pr_err("failed to disable all clocks\n");
  620. #endif
  621. return err;
  622. }
  623. static int designware_eth_remove(struct udevice *dev)
  624. {
  625. struct dw_eth_dev *priv = dev_get_priv(dev);
  626. free(priv->phydev);
  627. mdio_unregister(priv->bus);
  628. mdio_free(priv->bus);
  629. #ifdef CONFIG_CLK
  630. return clk_release_all(priv->clocks, priv->clock_count);
  631. #else
  632. return 0;
  633. #endif
  634. }
  635. const struct eth_ops designware_eth_ops = {
  636. .start = designware_eth_start,
  637. .send = designware_eth_send,
  638. .recv = designware_eth_recv,
  639. .free_pkt = designware_eth_free_pkt,
  640. .stop = designware_eth_stop,
  641. .write_hwaddr = designware_eth_write_hwaddr,
  642. };
  643. int designware_eth_ofdata_to_platdata(struct udevice *dev)
  644. {
  645. struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
  646. #ifdef CONFIG_DM_GPIO
  647. struct dw_eth_dev *priv = dev_get_priv(dev);
  648. #endif
  649. struct eth_pdata *pdata = &dw_pdata->eth_pdata;
  650. const char *phy_mode;
  651. #ifdef CONFIG_DM_GPIO
  652. int reset_flags = GPIOD_IS_OUT;
  653. #endif
  654. int ret = 0;
  655. pdata->iobase = dev_read_addr(dev);
  656. pdata->phy_interface = -1;
  657. phy_mode = dev_read_string(dev, "phy-mode");
  658. if (phy_mode)
  659. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  660. if (pdata->phy_interface == -1) {
  661. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  662. return -EINVAL;
  663. }
  664. pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
  665. #ifdef CONFIG_DM_GPIO
  666. if (dev_read_bool(dev, "snps,reset-active-low"))
  667. reset_flags |= GPIOD_ACTIVE_LOW;
  668. ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
  669. &priv->reset_gpio, reset_flags);
  670. if (ret == 0) {
  671. ret = dev_read_u32_array(dev, "snps,reset-delays-us",
  672. dw_pdata->reset_delays, 3);
  673. } else if (ret == -ENOENT) {
  674. ret = 0;
  675. }
  676. #endif
  677. return ret;
  678. }
  679. static const struct udevice_id designware_eth_ids[] = {
  680. { .compatible = "allwinner,sun7i-a20-gmac" },
  681. { .compatible = "amlogic,meson6-dwmac" },
  682. { .compatible = "amlogic,meson-gx-dwmac" },
  683. { .compatible = "amlogic,meson-gxbb-dwmac" },
  684. { .compatible = "amlogic,meson-axg-dwmac" },
  685. { .compatible = "st,stm32-dwmac" },
  686. { .compatible = "snps,arc-dwmac-3.70a" },
  687. { }
  688. };
  689. U_BOOT_DRIVER(eth_designware) = {
  690. .name = "eth_designware",
  691. .id = UCLASS_ETH,
  692. .of_match = designware_eth_ids,
  693. .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
  694. .bind = designware_eth_bind,
  695. .probe = designware_eth_probe,
  696. .remove = designware_eth_remove,
  697. .ops = &designware_eth_ops,
  698. .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
  699. .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
  700. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  701. };
  702. static struct pci_device_id supported[] = {
  703. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
  704. { }
  705. };
  706. U_BOOT_PCI_DEVICE(eth_designware, supported);
  707. #endif