dc2114x.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. #include <common.h>
  3. #include <env.h>
  4. #include <malloc.h>
  5. #include <net.h>
  6. #include <netdev.h>
  7. #include <pci.h>
  8. #undef DEBUG_SROM
  9. #undef DEBUG_SROM2
  10. #undef UPDATE_SROM
  11. /* PCI Registers.
  12. */
  13. #define PCI_CFDA_PSM 0x43
  14. #define CFRV_RN 0x000000f0 /* Revision Number */
  15. #define WAKEUP 0x00 /* Power Saving Wakeup */
  16. #define SLEEP 0x80 /* Power Saving Sleep Mode */
  17. #define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
  18. /* Ethernet chip registers.
  19. */
  20. #define DE4X5_BMR 0x000 /* Bus Mode Register */
  21. #define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
  22. #define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
  23. #define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
  24. #define DE4X5_STS 0x028 /* Status Register */
  25. #define DE4X5_OMR 0x030 /* Operation Mode Register */
  26. #define DE4X5_SICR 0x068 /* SIA Connectivity Register */
  27. #define DE4X5_APROM 0x048 /* Ethernet Address PROM */
  28. /* Register bits.
  29. */
  30. #define BMR_SWR 0x00000001 /* Software Reset */
  31. #define STS_TS 0x00700000 /* Transmit Process State */
  32. #define STS_RS 0x000e0000 /* Receive Process State */
  33. #define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
  34. #define OMR_SR 0x00000002 /* Start/Stop Receive */
  35. #define OMR_PS 0x00040000 /* Port Select */
  36. #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
  37. #define OMR_PM 0x00000080 /* Pass All Multicast */
  38. /* Descriptor bits.
  39. */
  40. #define R_OWN 0x80000000 /* Own Bit */
  41. #define RD_RER 0x02000000 /* Receive End Of Ring */
  42. #define RD_LS 0x00000100 /* Last Descriptor */
  43. #define RD_ES 0x00008000 /* Error Summary */
  44. #define TD_TER 0x02000000 /* Transmit End Of Ring */
  45. #define T_OWN 0x80000000 /* Own Bit */
  46. #define TD_LS 0x40000000 /* Last Segment */
  47. #define TD_FS 0x20000000 /* First Segment */
  48. #define TD_ES 0x00008000 /* Error Summary */
  49. #define TD_SET 0x08000000 /* Setup Packet */
  50. /* The EEPROM commands include the alway-set leading bit. */
  51. #define SROM_WRITE_CMD 5
  52. #define SROM_READ_CMD 6
  53. #define SROM_ERASE_CMD 7
  54. #define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
  55. #define SROM_RD 0x00004000 /* Read from Boot ROM */
  56. #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
  57. #define EE_WRITE_0 0x4801
  58. #define EE_WRITE_1 0x4805
  59. #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
  60. #define SROM_SR 0x00000800 /* Select Serial ROM when set */
  61. #define DT_IN 0x00000004 /* Serial Data In */
  62. #define DT_CLK 0x00000002 /* Serial ROM Clock */
  63. #define DT_CS 0x00000001 /* Serial ROM Chip Select */
  64. #define POLL_DEMAND 1
  65. #ifdef CONFIG_TULIP_FIX_DAVICOM
  66. #define RESET_DM9102(dev) {\
  67. unsigned long i;\
  68. i=INL(dev, 0x0);\
  69. udelay(1000);\
  70. OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
  71. udelay(1000);\
  72. }
  73. #else
  74. #define RESET_DE4X5(dev) {\
  75. int i;\
  76. i=INL(dev, DE4X5_BMR);\
  77. udelay(1000);\
  78. OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
  79. udelay(1000);\
  80. OUTL(dev, i, DE4X5_BMR);\
  81. udelay(1000);\
  82. for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\
  83. udelay(1000);\
  84. }
  85. #endif
  86. #define START_DE4X5(dev) {\
  87. s32 omr; \
  88. omr = INL(dev, DE4X5_OMR);\
  89. omr |= OMR_ST | OMR_SR;\
  90. OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */\
  91. }
  92. #define STOP_DE4X5(dev) {\
  93. s32 omr; \
  94. omr = INL(dev, DE4X5_OMR);\
  95. omr &= ~(OMR_ST|OMR_SR);\
  96. OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
  97. }
  98. #define NUM_RX_DESC PKTBUFSRX
  99. #ifndef CONFIG_TULIP_FIX_DAVICOM
  100. #define NUM_TX_DESC 1 /* Number of TX descriptors */
  101. #else
  102. #define NUM_TX_DESC 4
  103. #endif
  104. #define RX_BUFF_SZ PKTSIZE_ALIGN
  105. #define TOUT_LOOP 1000000
  106. #define SETUP_FRAME_LEN 192
  107. struct de4x5_desc {
  108. volatile s32 status;
  109. u32 des1;
  110. u32 buf;
  111. u32 next;
  112. };
  113. static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring */
  114. static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring */
  115. static int rx_new; /* RX descriptor ring pointer */
  116. static int tx_new; /* TX descriptor ring pointer */
  117. static char rxRingSize;
  118. static char txRingSize;
  119. #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
  120. static void sendto_srom(struct eth_device* dev, u_int command, u_long addr);
  121. static int getfrom_srom(struct eth_device* dev, u_long addr);
  122. static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len);
  123. static int do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len);
  124. #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
  125. #ifdef UPDATE_SROM
  126. static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value);
  127. static void update_srom(struct eth_device *dev, bd_t *bis);
  128. #endif
  129. #ifndef CONFIG_TULIP_FIX_DAVICOM
  130. static int read_srom(struct eth_device *dev, u_long ioaddr, int index);
  131. static void read_hw_addr(struct eth_device* dev, bd_t * bis);
  132. #endif /* CONFIG_TULIP_FIX_DAVICOM */
  133. static void send_setup_frame(struct eth_device* dev, bd_t * bis);
  134. static int dc21x4x_init(struct eth_device* dev, bd_t* bis);
  135. static int dc21x4x_send(struct eth_device *dev, void *packet, int length);
  136. static int dc21x4x_recv(struct eth_device* dev);
  137. static void dc21x4x_halt(struct eth_device* dev);
  138. #ifdef CONFIG_TULIP_SELECT_MEDIA
  139. extern void dc21x4x_select_media(struct eth_device* dev);
  140. #endif
  141. #if defined(CONFIG_E500)
  142. #define phys_to_bus(a) (a)
  143. #else
  144. #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
  145. #endif
  146. static int INL(struct eth_device* dev, u_long addr)
  147. {
  148. return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
  149. }
  150. static void OUTL(struct eth_device* dev, int command, u_long addr)
  151. {
  152. *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
  153. }
  154. static struct pci_device_id supported[] = {
  155. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
  156. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
  157. #ifdef CONFIG_TULIP_FIX_DAVICOM
  158. { PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A },
  159. #endif
  160. { }
  161. };
  162. int dc21x4x_initialize(bd_t *bis)
  163. {
  164. int idx=0;
  165. int card_number = 0;
  166. unsigned int cfrv;
  167. unsigned char timer;
  168. pci_dev_t devbusfn;
  169. unsigned int iobase;
  170. unsigned short status;
  171. struct eth_device* dev;
  172. while(1) {
  173. devbusfn = pci_find_devices(supported, idx++);
  174. if (devbusfn == -1) {
  175. break;
  176. }
  177. /* Get the chip configuration revision register. */
  178. pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
  179. #ifndef CONFIG_TULIP_FIX_DAVICOM
  180. if ((cfrv & CFRV_RN) < DC2114x_BRK ) {
  181. printf("Error: The chip is not DC21143.\n");
  182. continue;
  183. }
  184. #endif
  185. pci_read_config_word(devbusfn, PCI_COMMAND, &status);
  186. status |=
  187. #ifdef CONFIG_TULIP_USE_IO
  188. PCI_COMMAND_IO |
  189. #else
  190. PCI_COMMAND_MEMORY |
  191. #endif
  192. PCI_COMMAND_MASTER;
  193. pci_write_config_word(devbusfn, PCI_COMMAND, status);
  194. pci_read_config_word(devbusfn, PCI_COMMAND, &status);
  195. #ifdef CONFIG_TULIP_USE_IO
  196. if (!(status & PCI_COMMAND_IO)) {
  197. printf("Error: Can not enable I/O access.\n");
  198. continue;
  199. }
  200. #else
  201. if (!(status & PCI_COMMAND_MEMORY)) {
  202. printf("Error: Can not enable MEMORY access.\n");
  203. continue;
  204. }
  205. #endif
  206. if (!(status & PCI_COMMAND_MASTER)) {
  207. printf("Error: Can not enable Bus Mastering.\n");
  208. continue;
  209. }
  210. /* Check the latency timer for values >= 0x60. */
  211. pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
  212. if (timer < 0x60) {
  213. pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60);
  214. }
  215. #ifdef CONFIG_TULIP_USE_IO
  216. /* read BAR for memory space access */
  217. pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
  218. iobase &= PCI_BASE_ADDRESS_IO_MASK;
  219. #else
  220. /* read BAR for memory space access */
  221. pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
  222. iobase &= PCI_BASE_ADDRESS_MEM_MASK;
  223. #endif
  224. debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
  225. dev = (struct eth_device*) malloc(sizeof *dev);
  226. if (!dev) {
  227. printf("Can not allocalte memory of dc21x4x\n");
  228. break;
  229. }
  230. memset(dev, 0, sizeof(*dev));
  231. #ifdef CONFIG_TULIP_FIX_DAVICOM
  232. sprintf(dev->name, "Davicom#%d", card_number);
  233. #else
  234. sprintf(dev->name, "dc21x4x#%d", card_number);
  235. #endif
  236. #ifdef CONFIG_TULIP_USE_IO
  237. dev->iobase = pci_io_to_phys(devbusfn, iobase);
  238. #else
  239. dev->iobase = pci_mem_to_phys(devbusfn, iobase);
  240. #endif
  241. dev->priv = (void*) devbusfn;
  242. dev->init = dc21x4x_init;
  243. dev->halt = dc21x4x_halt;
  244. dev->send = dc21x4x_send;
  245. dev->recv = dc21x4x_recv;
  246. /* Ensure we're not sleeping. */
  247. pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
  248. udelay(10 * 1000);
  249. #ifndef CONFIG_TULIP_FIX_DAVICOM
  250. read_hw_addr(dev, bis);
  251. #endif
  252. eth_register(dev);
  253. card_number++;
  254. }
  255. return card_number;
  256. }
  257. static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
  258. {
  259. int i;
  260. int devbusfn = (int) dev->priv;
  261. /* Ensure we're not sleeping. */
  262. pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
  263. #ifdef CONFIG_TULIP_FIX_DAVICOM
  264. RESET_DM9102(dev);
  265. #else
  266. RESET_DE4X5(dev);
  267. #endif
  268. if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
  269. printf("Error: Cannot reset ethernet controller.\n");
  270. return -1;
  271. }
  272. #ifdef CONFIG_TULIP_SELECT_MEDIA
  273. dc21x4x_select_media(dev);
  274. #else
  275. OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
  276. #endif
  277. for (i = 0; i < NUM_RX_DESC; i++) {
  278. rx_ring[i].status = cpu_to_le32(R_OWN);
  279. rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
  280. rx_ring[i].buf = cpu_to_le32(
  281. phys_to_bus((u32)net_rx_packets[i]));
  282. #ifdef CONFIG_TULIP_FIX_DAVICOM
  283. rx_ring[i].next = cpu_to_le32(
  284. phys_to_bus((u32)&rx_ring[(i + 1) % NUM_RX_DESC]));
  285. #else
  286. rx_ring[i].next = 0;
  287. #endif
  288. }
  289. for (i=0; i < NUM_TX_DESC; i++) {
  290. tx_ring[i].status = 0;
  291. tx_ring[i].des1 = 0;
  292. tx_ring[i].buf = 0;
  293. #ifdef CONFIG_TULIP_FIX_DAVICOM
  294. tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC]));
  295. #else
  296. tx_ring[i].next = 0;
  297. #endif
  298. }
  299. rxRingSize = NUM_RX_DESC;
  300. txRingSize = NUM_TX_DESC;
  301. /* Write the end of list marker to the descriptor lists. */
  302. rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
  303. tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
  304. /* Tell the adapter where the TX/RX rings are located. */
  305. OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA);
  306. OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA);
  307. START_DE4X5(dev);
  308. tx_new = 0;
  309. rx_new = 0;
  310. send_setup_frame(dev, bis);
  311. return 0;
  312. }
  313. static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
  314. {
  315. int status = -1;
  316. int i;
  317. if (length <= 0) {
  318. printf("%s: bad packet size: %d\n", dev->name, length);
  319. goto Done;
  320. }
  321. for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
  322. if (i >= TOUT_LOOP) {
  323. printf("%s: tx error buffer not ready\n", dev->name);
  324. goto Done;
  325. }
  326. }
  327. tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet));
  328. tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
  329. tx_ring[tx_new].status = cpu_to_le32(T_OWN);
  330. OUTL(dev, POLL_DEMAND, DE4X5_TPD);
  331. for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
  332. if (i >= TOUT_LOOP) {
  333. printf(".%s: tx buffer not ready\n", dev->name);
  334. goto Done;
  335. }
  336. }
  337. if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
  338. #if 0 /* test-only */
  339. printf("TX error status = 0x%08X\n",
  340. le32_to_cpu(tx_ring[tx_new].status));
  341. #endif
  342. tx_ring[tx_new].status = 0x0;
  343. goto Done;
  344. }
  345. status = length;
  346. Done:
  347. tx_new = (tx_new+1) % NUM_TX_DESC;
  348. return status;
  349. }
  350. static int dc21x4x_recv(struct eth_device* dev)
  351. {
  352. s32 status;
  353. int length = 0;
  354. for ( ; ; ) {
  355. status = (s32)le32_to_cpu(rx_ring[rx_new].status);
  356. if (status & R_OWN) {
  357. break;
  358. }
  359. if (status & RD_LS) {
  360. /* Valid frame status.
  361. */
  362. if (status & RD_ES) {
  363. /* There was an error.
  364. */
  365. printf("RX error status = 0x%08X\n", status);
  366. } else {
  367. /* A valid frame received.
  368. */
  369. length = (le32_to_cpu(rx_ring[rx_new].status) >> 16);
  370. /* Pass the packet up to the protocol
  371. * layers.
  372. */
  373. net_process_received_packet(
  374. net_rx_packets[rx_new], length - 4);
  375. }
  376. /* Change buffer ownership for this frame, back
  377. * to the adapter.
  378. */
  379. rx_ring[rx_new].status = cpu_to_le32(R_OWN);
  380. }
  381. /* Update entry information.
  382. */
  383. rx_new = (rx_new + 1) % rxRingSize;
  384. }
  385. return length;
  386. }
  387. static void dc21x4x_halt(struct eth_device* dev)
  388. {
  389. int devbusfn = (int) dev->priv;
  390. STOP_DE4X5(dev);
  391. OUTL(dev, 0, DE4X5_SICR);
  392. pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
  393. }
  394. static void send_setup_frame(struct eth_device* dev, bd_t *bis)
  395. {
  396. int i;
  397. char setup_frame[SETUP_FRAME_LEN];
  398. char *pa = &setup_frame[0];
  399. memset(pa, 0xff, SETUP_FRAME_LEN);
  400. for (i = 0; i < ETH_ALEN; i++) {
  401. *(pa + (i & 1)) = dev->enetaddr[i];
  402. if (i & 0x01) {
  403. pa += 4;
  404. }
  405. }
  406. for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
  407. if (i >= TOUT_LOOP) {
  408. printf("%s: tx error buffer not ready\n", dev->name);
  409. goto Done;
  410. }
  411. }
  412. tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0]));
  413. tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN);
  414. tx_ring[tx_new].status = cpu_to_le32(T_OWN);
  415. OUTL(dev, POLL_DEMAND, DE4X5_TPD);
  416. for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
  417. if (i >= TOUT_LOOP) {
  418. printf("%s: tx buffer not ready\n", dev->name);
  419. goto Done;
  420. }
  421. }
  422. if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
  423. printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status));
  424. }
  425. tx_new = (tx_new+1) % NUM_TX_DESC;
  426. Done:
  427. return;
  428. }
  429. #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
  430. /* SROM Read and write routines.
  431. */
  432. static void
  433. sendto_srom(struct eth_device* dev, u_int command, u_long addr)
  434. {
  435. OUTL(dev, command, addr);
  436. udelay(1);
  437. }
  438. static int
  439. getfrom_srom(struct eth_device* dev, u_long addr)
  440. {
  441. s32 tmp;
  442. tmp = INL(dev, addr);
  443. udelay(1);
  444. return tmp;
  445. }
  446. /* Note: this routine returns extra data bits for size detection. */
  447. static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len)
  448. {
  449. int i;
  450. unsigned retval = 0;
  451. int read_cmd = location | (SROM_READ_CMD << addr_len);
  452. sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
  453. sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
  454. #ifdef DEBUG_SROM
  455. printf(" EEPROM read at %d ", location);
  456. #endif
  457. /* Shift the read command bits out. */
  458. for (i = 4 + addr_len; i >= 0; i--) {
  459. short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
  460. sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr);
  461. udelay(10);
  462. sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr);
  463. udelay(10);
  464. #ifdef DEBUG_SROM2
  465. printf("%X", getfrom_srom(dev, ioaddr) & 15);
  466. #endif
  467. retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
  468. }
  469. sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
  470. #ifdef DEBUG_SROM2
  471. printf(" :%X:", getfrom_srom(dev, ioaddr) & 15);
  472. #endif
  473. for (i = 16; i > 0; i--) {
  474. sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
  475. udelay(10);
  476. #ifdef DEBUG_SROM2
  477. printf("%X", getfrom_srom(dev, ioaddr) & 15);
  478. #endif
  479. retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
  480. sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
  481. udelay(10);
  482. }
  483. /* Terminate the EEPROM access. */
  484. sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
  485. #ifdef DEBUG_SROM2
  486. printf(" EEPROM value at %d is %5.5x.\n", location, retval);
  487. #endif
  488. return retval;
  489. }
  490. #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
  491. /* This executes a generic EEPROM command, typically a write or write
  492. * enable. It returns the data output from the EEPROM, and thus may
  493. * also be used for reads.
  494. */
  495. #if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
  496. static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len)
  497. {
  498. unsigned retval = 0;
  499. #ifdef DEBUG_SROM
  500. printf(" EEPROM op 0x%x: ", cmd);
  501. #endif
  502. sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
  503. /* Shift the command bits out. */
  504. do {
  505. short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
  506. sendto_srom(dev,dataval, ioaddr);
  507. udelay(10);
  508. #ifdef DEBUG_SROM2
  509. printf("%X", getfrom_srom(dev,ioaddr) & 15);
  510. #endif
  511. sendto_srom(dev,dataval | DT_CLK, ioaddr);
  512. udelay(10);
  513. retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0);
  514. } while (--cmd_len >= 0);
  515. sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr);
  516. /* Terminate the EEPROM access. */
  517. sendto_srom(dev,SROM_RD | SROM_SR, ioaddr);
  518. #ifdef DEBUG_SROM
  519. printf(" EEPROM result is 0x%5.5x.\n", retval);
  520. #endif
  521. return retval;
  522. }
  523. #endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
  524. #ifndef CONFIG_TULIP_FIX_DAVICOM
  525. static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
  526. {
  527. int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
  528. return do_eeprom_cmd(dev, ioaddr,
  529. (((SROM_READ_CMD << ee_addr_size) | index) << 16)
  530. | 0xffff, 3 + ee_addr_size + 16);
  531. }
  532. #endif /* CONFIG_TULIP_FIX_DAVICOM */
  533. #ifdef UPDATE_SROM
  534. static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value)
  535. {
  536. int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
  537. int i;
  538. unsigned short newval;
  539. udelay(10*1000); /* test-only */
  540. #ifdef DEBUG_SROM
  541. printf("ee_addr_size=%d.\n", ee_addr_size);
  542. printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index);
  543. #endif
  544. /* Enable programming modes. */
  545. do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size);
  546. /* Do the actual write. */
  547. do_eeprom_cmd(dev, ioaddr,
  548. (((SROM_WRITE_CMD<<ee_addr_size)|index) << 16) | new_value,
  549. 3 + ee_addr_size + 16);
  550. /* Poll for write finished. */
  551. sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
  552. for (i = 0; i < 10000; i++) /* Typical 2000 ticks */
  553. if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
  554. break;
  555. #ifdef DEBUG_SROM
  556. printf(" Write finished after %d ticks.\n", i);
  557. #endif
  558. /* Disable programming. */
  559. do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size);
  560. /* And read the result. */
  561. newval = do_eeprom_cmd(dev, ioaddr,
  562. (((SROM_READ_CMD<<ee_addr_size)|index) << 16)
  563. | 0xffff, 3 + ee_addr_size + 16);
  564. #ifdef DEBUG_SROM
  565. printf(" New value at offset %d is %4.4x.\n", index, newval);
  566. #endif
  567. return 1;
  568. }
  569. #endif
  570. #ifndef CONFIG_TULIP_FIX_DAVICOM
  571. static void read_hw_addr(struct eth_device *dev, bd_t *bis)
  572. {
  573. u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
  574. int i, j = 0;
  575. for (i = 0; i < (ETH_ALEN >> 1); i++) {
  576. tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i));
  577. *p = le16_to_cpu(tmp);
  578. j += *p++;
  579. }
  580. if ((j == 0) || (j == 0x2fffd)) {
  581. memset (dev->enetaddr, 0, ETH_ALEN);
  582. debug ("Warning: can't read HW address from SROM.\n");
  583. goto Done;
  584. }
  585. return;
  586. Done:
  587. #ifdef UPDATE_SROM
  588. update_srom(dev, bis);
  589. #endif
  590. return;
  591. }
  592. #endif /* CONFIG_TULIP_FIX_DAVICOM */
  593. #ifdef UPDATE_SROM
  594. static void update_srom(struct eth_device *dev, bd_t *bis)
  595. {
  596. int i;
  597. static unsigned short eeprom[0x40] = {
  598. 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */
  599. 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */
  600. 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */
  601. 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */
  602. 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */
  603. 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */
  604. 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */
  605. 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */
  606. 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */
  607. 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
  608. 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
  609. 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */
  610. 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
  611. 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */
  612. 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */
  613. 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */
  614. };
  615. uchar enetaddr[6];
  616. /* Ethernet Addr... */
  617. if (!eth_env_get_enetaddr("ethaddr", enetaddr))
  618. return;
  619. eeprom[0x0a] = (enetaddr[1] << 8) | enetaddr[0];
  620. eeprom[0x0b] = (enetaddr[3] << 8) | enetaddr[2];
  621. eeprom[0x0c] = (enetaddr[5] << 8) | enetaddr[4];
  622. for (i=0; i<0x40; i++) {
  623. write_srom(dev, DE4X5_APROM, i, eeprom[i]);
  624. }
  625. }
  626. #endif /* UPDATE_SROM */