calxedaxgmac.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2011 Calxeda, Inc.
  4. */
  5. #include <common.h>
  6. #include <malloc.h>
  7. #include <linux/compiler.h>
  8. #include <linux/err.h>
  9. #include <asm/io.h>
  10. #define TX_NUM_DESC 1
  11. #define RX_NUM_DESC 32
  12. #define MAC_TIMEOUT (5*CONFIG_SYS_HZ)
  13. #define ETH_BUF_SZ 2048
  14. #define TX_BUF_SZ (ETH_BUF_SZ * TX_NUM_DESC)
  15. #define RX_BUF_SZ (ETH_BUF_SZ * RX_NUM_DESC)
  16. #define RXSTART 0x00000002
  17. #define TXSTART 0x00002000
  18. #define RXENABLE 0x00000004
  19. #define TXENABLE 0x00000008
  20. #define XGMAC_CONTROL_SPD 0x40000000
  21. #define XGMAC_CONTROL_SPD_MASK 0x60000000
  22. #define XGMAC_CONTROL_SARC 0x10000000
  23. #define XGMAC_CONTROL_SARK_MASK 0x18000000
  24. #define XGMAC_CONTROL_CAR 0x04000000
  25. #define XGMAC_CONTROL_CAR_MASK 0x06000000
  26. #define XGMAC_CONTROL_CAR_SHIFT 25
  27. #define XGMAC_CONTROL_DP 0x01000000
  28. #define XGMAC_CONTROL_WD 0x00800000
  29. #define XGMAC_CONTROL_JD 0x00400000
  30. #define XGMAC_CONTROL_JE 0x00100000
  31. #define XGMAC_CONTROL_LM 0x00001000
  32. #define XGMAC_CONTROL_IPC 0x00000400
  33. #define XGMAC_CONTROL_ACS 0x00000080
  34. #define XGMAC_CONTROL_DDIC 0x00000010
  35. #define XGMAC_CONTROL_TE 0x00000008
  36. #define XGMAC_CONTROL_RE 0x00000004
  37. #define XGMAC_DMA_BUSMODE_RESET 0x00000001
  38. #define XGMAC_DMA_BUSMODE_DSL 0x00000004
  39. #define XGMAC_DMA_BUSMODE_DSL_MASK 0x0000007c
  40. #define XGMAC_DMA_BUSMODE_DSL_SHIFT 2
  41. #define XGMAC_DMA_BUSMODE_ATDS 0x00000080
  42. #define XGMAC_DMA_BUSMODE_PBL_MASK 0x00003f00
  43. #define XGMAC_DMA_BUSMODE_PBL_SHIFT 8
  44. #define XGMAC_DMA_BUSMODE_FB 0x00010000
  45. #define XGMAC_DMA_BUSMODE_USP 0x00800000
  46. #define XGMAC_DMA_BUSMODE_8PBL 0x01000000
  47. #define XGMAC_DMA_BUSMODE_AAL 0x02000000
  48. #define XGMAC_DMA_AXIMODE_ENLPI 0x80000000
  49. #define XGMAC_DMA_AXIMODE_MGK 0x40000000
  50. #define XGMAC_DMA_AXIMODE_WROSR 0x00100000
  51. #define XGMAC_DMA_AXIMODE_WROSR_MASK 0x00F00000
  52. #define XGMAC_DMA_AXIMODE_WROSR_SHIFT 20
  53. #define XGMAC_DMA_AXIMODE_RDOSR 0x00010000
  54. #define XGMAC_DMA_AXIMODE_RDOSR_MASK 0x000F0000
  55. #define XGMAC_DMA_AXIMODE_RDOSR_SHIFT 16
  56. #define XGMAC_DMA_AXIMODE_AAL 0x00001000
  57. #define XGMAC_DMA_AXIMODE_BLEN256 0x00000080
  58. #define XGMAC_DMA_AXIMODE_BLEN128 0x00000040
  59. #define XGMAC_DMA_AXIMODE_BLEN64 0x00000020
  60. #define XGMAC_DMA_AXIMODE_BLEN32 0x00000010
  61. #define XGMAC_DMA_AXIMODE_BLEN16 0x00000008
  62. #define XGMAC_DMA_AXIMODE_BLEN8 0x00000004
  63. #define XGMAC_DMA_AXIMODE_BLEN4 0x00000002
  64. #define XGMAC_DMA_AXIMODE_UNDEF 0x00000001
  65. #define XGMAC_CORE_OMR_RTC_SHIFT 3
  66. #define XGMAC_CORE_OMR_RTC_MASK 0x00000018
  67. #define XGMAC_CORE_OMR_RTC 0x00000010
  68. #define XGMAC_CORE_OMR_RSF 0x00000020
  69. #define XGMAC_CORE_OMR_DT 0x00000040
  70. #define XGMAC_CORE_OMR_FEF 0x00000080
  71. #define XGMAC_CORE_OMR_EFC 0x00000100
  72. #define XGMAC_CORE_OMR_RFA_SHIFT 9
  73. #define XGMAC_CORE_OMR_RFA_MASK 0x00000E00
  74. #define XGMAC_CORE_OMR_RFD_SHIFT 12
  75. #define XGMAC_CORE_OMR_RFD_MASK 0x00007000
  76. #define XGMAC_CORE_OMR_TTC_SHIFT 16
  77. #define XGMAC_CORE_OMR_TTC_MASK 0x00030000
  78. #define XGMAC_CORE_OMR_TTC 0x00020000
  79. #define XGMAC_CORE_OMR_FTF 0x00100000
  80. #define XGMAC_CORE_OMR_TSF 0x00200000
  81. #define FIFO_MINUS_1K 0x0
  82. #define FIFO_MINUS_2K 0x1
  83. #define FIFO_MINUS_3K 0x2
  84. #define FIFO_MINUS_4K 0x3
  85. #define FIFO_MINUS_6K 0x4
  86. #define FIFO_MINUS_8K 0x5
  87. #define FIFO_MINUS_12K 0x6
  88. #define FIFO_MINUS_16K 0x7
  89. #define XGMAC_CORE_FLOW_PT_SHIFT 16
  90. #define XGMAC_CORE_FLOW_PT_MASK 0xFFFF0000
  91. #define XGMAC_CORE_FLOW_PT 0x00010000
  92. #define XGMAC_CORE_FLOW_DZQP 0x00000080
  93. #define XGMAC_CORE_FLOW_PLT_SHIFT 4
  94. #define XGMAC_CORE_FLOW_PLT_MASK 0x00000030
  95. #define XGMAC_CORE_FLOW_PLT 0x00000010
  96. #define XGMAC_CORE_FLOW_UP 0x00000008
  97. #define XGMAC_CORE_FLOW_RFE 0x00000004
  98. #define XGMAC_CORE_FLOW_TFE 0x00000002
  99. #define XGMAC_CORE_FLOW_FCB 0x00000001
  100. /* XGMAC Descriptor Defines */
  101. #define MAX_DESC_BUF_SZ (0x2000 - 8)
  102. #define RXDESC_EXT_STATUS 0x00000001
  103. #define RXDESC_CRC_ERR 0x00000002
  104. #define RXDESC_RX_ERR 0x00000008
  105. #define RXDESC_RX_WDOG 0x00000010
  106. #define RXDESC_FRAME_TYPE 0x00000020
  107. #define RXDESC_GIANT_FRAME 0x00000080
  108. #define RXDESC_LAST_SEG 0x00000100
  109. #define RXDESC_FIRST_SEG 0x00000200
  110. #define RXDESC_VLAN_FRAME 0x00000400
  111. #define RXDESC_OVERFLOW_ERR 0x00000800
  112. #define RXDESC_LENGTH_ERR 0x00001000
  113. #define RXDESC_SA_FILTER_FAIL 0x00002000
  114. #define RXDESC_DESCRIPTOR_ERR 0x00004000
  115. #define RXDESC_ERROR_SUMMARY 0x00008000
  116. #define RXDESC_FRAME_LEN_OFFSET 16
  117. #define RXDESC_FRAME_LEN_MASK 0x3fff0000
  118. #define RXDESC_DA_FILTER_FAIL 0x40000000
  119. #define RXDESC1_END_RING 0x00008000
  120. #define RXDESC_IP_PAYLOAD_MASK 0x00000003
  121. #define RXDESC_IP_PAYLOAD_UDP 0x00000001
  122. #define RXDESC_IP_PAYLOAD_TCP 0x00000002
  123. #define RXDESC_IP_PAYLOAD_ICMP 0x00000003
  124. #define RXDESC_IP_HEADER_ERR 0x00000008
  125. #define RXDESC_IP_PAYLOAD_ERR 0x00000010
  126. #define RXDESC_IPV4_PACKET 0x00000040
  127. #define RXDESC_IPV6_PACKET 0x00000080
  128. #define TXDESC_UNDERFLOW_ERR 0x00000001
  129. #define TXDESC_JABBER_TIMEOUT 0x00000002
  130. #define TXDESC_LOCAL_FAULT 0x00000004
  131. #define TXDESC_REMOTE_FAULT 0x00000008
  132. #define TXDESC_VLAN_FRAME 0x00000010
  133. #define TXDESC_FRAME_FLUSHED 0x00000020
  134. #define TXDESC_IP_HEADER_ERR 0x00000040
  135. #define TXDESC_PAYLOAD_CSUM_ERR 0x00000080
  136. #define TXDESC_ERROR_SUMMARY 0x00008000
  137. #define TXDESC_SA_CTRL_INSERT 0x00040000
  138. #define TXDESC_SA_CTRL_REPLACE 0x00080000
  139. #define TXDESC_2ND_ADDR_CHAINED 0x00100000
  140. #define TXDESC_END_RING 0x00200000
  141. #define TXDESC_CSUM_IP 0x00400000
  142. #define TXDESC_CSUM_IP_PAYLD 0x00800000
  143. #define TXDESC_CSUM_ALL 0x00C00000
  144. #define TXDESC_CRC_EN_REPLACE 0x01000000
  145. #define TXDESC_CRC_EN_APPEND 0x02000000
  146. #define TXDESC_DISABLE_PAD 0x04000000
  147. #define TXDESC_FIRST_SEG 0x10000000
  148. #define TXDESC_LAST_SEG 0x20000000
  149. #define TXDESC_INTERRUPT 0x40000000
  150. #define DESC_OWN 0x80000000
  151. #define DESC_BUFFER1_SZ_MASK 0x00001fff
  152. #define DESC_BUFFER2_SZ_MASK 0x1fff0000
  153. #define DESC_BUFFER2_SZ_OFFSET 16
  154. struct xgmac_regs {
  155. u32 config;
  156. u32 framefilter;
  157. u32 resv_1[4];
  158. u32 flow_control;
  159. u32 vlantag;
  160. u32 version;
  161. u32 vlaninclude;
  162. u32 resv_2[2];
  163. u32 pacestretch;
  164. u32 vlanhash;
  165. u32 resv_3;
  166. u32 intreg;
  167. struct {
  168. u32 hi; /* 0x40 */
  169. u32 lo; /* 0x44 */
  170. } macaddr[16];
  171. u32 resv_4[0xd0];
  172. u32 core_opmode; /* 0x400 */
  173. u32 resv_5[0x2bf];
  174. u32 busmode; /* 0xf00 */
  175. u32 txpoll;
  176. u32 rxpoll;
  177. u32 rxdesclist;
  178. u32 txdesclist;
  179. u32 dma_status;
  180. u32 dma_opmode;
  181. u32 intenable;
  182. u32 resv_6[2];
  183. u32 axi_mode; /* 0xf28 */
  184. };
  185. struct xgmac_dma_desc {
  186. __le32 flags;
  187. __le32 buf_size;
  188. __le32 buf1_addr; /* Buffer 1 Address Pointer */
  189. __le32 buf2_addr; /* Buffer 2 Address Pointer */
  190. __le32 ext_status;
  191. __le32 res[3];
  192. };
  193. /* XGMAC Descriptor Access Helpers */
  194. static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz)
  195. {
  196. if (buf_sz > MAX_DESC_BUF_SZ)
  197. p->buf_size = cpu_to_le32(MAX_DESC_BUF_SZ |
  198. (buf_sz - MAX_DESC_BUF_SZ) << DESC_BUFFER2_SZ_OFFSET);
  199. else
  200. p->buf_size = cpu_to_le32(buf_sz);
  201. }
  202. static inline int desc_get_buf_len(struct xgmac_dma_desc *p)
  203. {
  204. u32 len = le32_to_cpu(p->buf_size);
  205. return (len & DESC_BUFFER1_SZ_MASK) +
  206. ((len & DESC_BUFFER2_SZ_MASK) >> DESC_BUFFER2_SZ_OFFSET);
  207. }
  208. static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size,
  209. int buf_sz)
  210. {
  211. struct xgmac_dma_desc *end = p + ring_size - 1;
  212. memset(p, 0, sizeof(*p) * ring_size);
  213. for (; p <= end; p++)
  214. desc_set_buf_len(p, buf_sz);
  215. end->buf_size |= cpu_to_le32(RXDESC1_END_RING);
  216. }
  217. static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size)
  218. {
  219. memset(p, 0, sizeof(*p) * ring_size);
  220. p[ring_size - 1].flags = cpu_to_le32(TXDESC_END_RING);
  221. }
  222. static inline int desc_get_owner(struct xgmac_dma_desc *p)
  223. {
  224. return le32_to_cpu(p->flags) & DESC_OWN;
  225. }
  226. static inline void desc_set_rx_owner(struct xgmac_dma_desc *p)
  227. {
  228. /* Clear all fields and set the owner */
  229. p->flags = cpu_to_le32(DESC_OWN);
  230. }
  231. static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags)
  232. {
  233. u32 tmpflags = le32_to_cpu(p->flags);
  234. tmpflags &= TXDESC_END_RING;
  235. tmpflags |= flags | DESC_OWN;
  236. p->flags = cpu_to_le32(tmpflags);
  237. }
  238. static inline void *desc_get_buf_addr(struct xgmac_dma_desc *p)
  239. {
  240. return (void *)le32_to_cpu(p->buf1_addr);
  241. }
  242. static inline void desc_set_buf_addr(struct xgmac_dma_desc *p,
  243. void *paddr, int len)
  244. {
  245. p->buf1_addr = cpu_to_le32(paddr);
  246. if (len > MAX_DESC_BUF_SZ)
  247. p->buf2_addr = cpu_to_le32(paddr + MAX_DESC_BUF_SZ);
  248. }
  249. static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p,
  250. void *paddr, int len)
  251. {
  252. desc_set_buf_len(p, len);
  253. desc_set_buf_addr(p, paddr, len);
  254. }
  255. static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p)
  256. {
  257. u32 data = le32_to_cpu(p->flags);
  258. u32 len = (data & RXDESC_FRAME_LEN_MASK) >> RXDESC_FRAME_LEN_OFFSET;
  259. if (data & RXDESC_FRAME_TYPE)
  260. len -= 4;
  261. return len;
  262. }
  263. struct calxeda_eth_dev {
  264. struct xgmac_dma_desc rx_chain[RX_NUM_DESC];
  265. struct xgmac_dma_desc tx_chain[TX_NUM_DESC];
  266. char rxbuffer[RX_BUF_SZ];
  267. u32 tx_currdesc;
  268. u32 rx_currdesc;
  269. struct eth_device *dev;
  270. } __aligned(32);
  271. /*
  272. * Initialize a descriptor ring. Calxeda XGMAC is configured to use
  273. * advanced descriptors.
  274. */
  275. static void init_rx_desc(struct calxeda_eth_dev *priv)
  276. {
  277. struct xgmac_dma_desc *rxdesc = priv->rx_chain;
  278. struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase;
  279. void *rxbuffer = priv->rxbuffer;
  280. int i;
  281. desc_init_rx_desc(rxdesc, RX_NUM_DESC, ETH_BUF_SZ);
  282. writel((ulong)rxdesc, &regs->rxdesclist);
  283. for (i = 0; i < RX_NUM_DESC; i++) {
  284. desc_set_buf_addr(rxdesc + i, rxbuffer + (i * ETH_BUF_SZ),
  285. ETH_BUF_SZ);
  286. desc_set_rx_owner(rxdesc + i);
  287. }
  288. }
  289. static void init_tx_desc(struct calxeda_eth_dev *priv)
  290. {
  291. struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase;
  292. desc_init_tx_desc(priv->tx_chain, TX_NUM_DESC);
  293. writel((ulong)priv->tx_chain, &regs->txdesclist);
  294. }
  295. static int xgmac_reset(struct eth_device *dev)
  296. {
  297. struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
  298. int timeout = MAC_TIMEOUT;
  299. u32 value;
  300. value = readl(&regs->config) & XGMAC_CONTROL_SPD_MASK;
  301. writel(XGMAC_DMA_BUSMODE_RESET, &regs->busmode);
  302. while ((timeout-- >= 0) &&
  303. (readl(&regs->busmode) & XGMAC_DMA_BUSMODE_RESET))
  304. udelay(1);
  305. writel(value, &regs->config);
  306. return timeout;
  307. }
  308. static void xgmac_hwmacaddr(struct eth_device *dev)
  309. {
  310. struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
  311. u32 macaddr[2];
  312. memcpy(macaddr, dev->enetaddr, 6);
  313. writel(macaddr[1], &regs->macaddr[0].hi);
  314. writel(macaddr[0], &regs->macaddr[0].lo);
  315. }
  316. static int xgmac_init(struct eth_device *dev, bd_t * bis)
  317. {
  318. struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
  319. struct calxeda_eth_dev *priv = dev->priv;
  320. int value;
  321. if (xgmac_reset(dev) < 0)
  322. return -1;
  323. /* set the hardware MAC address */
  324. xgmac_hwmacaddr(dev);
  325. /* set the AXI bus modes */
  326. value = XGMAC_DMA_BUSMODE_ATDS |
  327. (16 << XGMAC_DMA_BUSMODE_PBL_SHIFT) |
  328. XGMAC_DMA_BUSMODE_FB | XGMAC_DMA_BUSMODE_AAL;
  329. writel(value, &regs->busmode);
  330. value = XGMAC_DMA_AXIMODE_AAL | XGMAC_DMA_AXIMODE_BLEN16 |
  331. XGMAC_DMA_AXIMODE_BLEN8 | XGMAC_DMA_AXIMODE_BLEN4;
  332. writel(value, &regs->axi_mode);
  333. /* set flow control parameters and store and forward mode */
  334. value = (FIFO_MINUS_12K << XGMAC_CORE_OMR_RFD_SHIFT) |
  335. (FIFO_MINUS_4K << XGMAC_CORE_OMR_RFA_SHIFT) |
  336. XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF;
  337. writel(value, &regs->core_opmode);
  338. /* enable pause frames */
  339. value = (1024 << XGMAC_CORE_FLOW_PT_SHIFT) |
  340. (1 << XGMAC_CORE_FLOW_PLT_SHIFT) |
  341. XGMAC_CORE_FLOW_UP | XGMAC_CORE_FLOW_RFE | XGMAC_CORE_FLOW_TFE;
  342. writel(value, &regs->flow_control);
  343. /* Initialize the descriptor chains */
  344. init_rx_desc(priv);
  345. init_tx_desc(priv);
  346. /* must set to 0, or when started up will cause issues */
  347. priv->tx_currdesc = 0;
  348. priv->rx_currdesc = 0;
  349. /* set default core values */
  350. value = readl(&regs->config);
  351. value &= XGMAC_CONTROL_SPD_MASK;
  352. value |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_ACS |
  353. XGMAC_CONTROL_IPC | XGMAC_CONTROL_CAR;
  354. /* Everything is ready enable both mac and DMA */
  355. value |= RXENABLE | TXENABLE;
  356. writel(value, &regs->config);
  357. value = readl(&regs->dma_opmode);
  358. value |= RXSTART | TXSTART;
  359. writel(value, &regs->dma_opmode);
  360. return 0;
  361. }
  362. static int xgmac_tx(struct eth_device *dev, void *packet, int length)
  363. {
  364. struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
  365. struct calxeda_eth_dev *priv = dev->priv;
  366. u32 currdesc = priv->tx_currdesc;
  367. struct xgmac_dma_desc *txdesc = &priv->tx_chain[currdesc];
  368. int timeout;
  369. desc_set_buf_addr_and_size(txdesc, packet, length);
  370. desc_set_tx_owner(txdesc, TXDESC_FIRST_SEG |
  371. TXDESC_LAST_SEG | TXDESC_CRC_EN_APPEND);
  372. /* write poll demand */
  373. writel(1, &regs->txpoll);
  374. timeout = 1000000;
  375. while (desc_get_owner(txdesc)) {
  376. if (timeout-- < 0) {
  377. printf("xgmac: TX timeout\n");
  378. return -ETIMEDOUT;
  379. }
  380. udelay(1);
  381. }
  382. priv->tx_currdesc = (currdesc + 1) & (TX_NUM_DESC - 1);
  383. return 0;
  384. }
  385. static int xgmac_rx(struct eth_device *dev)
  386. {
  387. struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
  388. struct calxeda_eth_dev *priv = dev->priv;
  389. u32 currdesc = priv->rx_currdesc;
  390. struct xgmac_dma_desc *rxdesc = &priv->rx_chain[currdesc];
  391. int length = 0;
  392. /* check if the host has the desc */
  393. if (desc_get_owner(rxdesc))
  394. return -1; /* something bad happened */
  395. length = desc_get_rx_frame_len(rxdesc);
  396. net_process_received_packet(desc_get_buf_addr(rxdesc), length);
  397. /* set descriptor back to owned by XGMAC */
  398. desc_set_rx_owner(rxdesc);
  399. writel(1, &regs->rxpoll);
  400. priv->rx_currdesc = (currdesc + 1) & (RX_NUM_DESC - 1);
  401. return length;
  402. }
  403. static void xgmac_halt(struct eth_device *dev)
  404. {
  405. struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
  406. struct calxeda_eth_dev *priv = dev->priv;
  407. int value;
  408. /* Disable TX/RX */
  409. value = readl(&regs->config);
  410. value &= ~(RXENABLE | TXENABLE);
  411. writel(value, &regs->config);
  412. /* Disable DMA */
  413. value = readl(&regs->dma_opmode);
  414. value &= ~(RXSTART | TXSTART);
  415. writel(value, &regs->dma_opmode);
  416. /* must set to 0, or when started up will cause issues */
  417. priv->tx_currdesc = 0;
  418. priv->rx_currdesc = 0;
  419. }
  420. int calxedaxgmac_initialize(u32 id, ulong base_addr)
  421. {
  422. struct eth_device *dev;
  423. struct calxeda_eth_dev *priv;
  424. struct xgmac_regs *regs;
  425. u32 macaddr[2];
  426. regs = (struct xgmac_regs *)base_addr;
  427. /* check hardware version */
  428. if (readl(&regs->version) != 0x1012)
  429. return -1;
  430. dev = malloc(sizeof(*dev));
  431. if (!dev)
  432. return 0;
  433. memset(dev, 0, sizeof(*dev));
  434. /* Structure must be aligned, because it contains the descriptors */
  435. priv = memalign(32, sizeof(*priv));
  436. if (!priv) {
  437. free(dev);
  438. return 0;
  439. }
  440. dev->iobase = (int)base_addr;
  441. dev->priv = priv;
  442. priv->dev = dev;
  443. sprintf(dev->name, "xgmac%d", id);
  444. /* The MAC address is already configured, so read it from registers. */
  445. macaddr[1] = readl(&regs->macaddr[0].hi);
  446. macaddr[0] = readl(&regs->macaddr[0].lo);
  447. memcpy(dev->enetaddr, macaddr, 6);
  448. dev->init = xgmac_init;
  449. dev->send = xgmac_tx;
  450. dev->recv = xgmac_rx;
  451. dev->halt = xgmac_halt;
  452. eth_register(dev);
  453. return 1;
  454. }