armada100_fec.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2011
  4. * eInfochips Ltd. <www.einfochips.com>
  5. * Written-by: Ajay Bhargav <contact@8051projects.net>
  6. *
  7. * (C) Copyright 2010
  8. * Marvell Semiconductor <www.marvell.com>
  9. * Contributor: Mahavir Jain <mjain@marvell.com>
  10. */
  11. #include <common.h>
  12. #include <net.h>
  13. #include <malloc.h>
  14. #include <miiphy.h>
  15. #include <netdev.h>
  16. #include <asm/types.h>
  17. #include <asm/byteorder.h>
  18. #include <linux/err.h>
  19. #include <linux/mii.h>
  20. #include <asm/io.h>
  21. #include <asm/arch/armada100.h>
  22. #include "armada100_fec.h"
  23. #define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */
  24. #ifdef DEBUG
  25. static int eth_dump_regs(struct eth_device *dev)
  26. {
  27. struct armdfec_device *darmdfec = to_darmdfec(dev);
  28. struct armdfec_reg *regs = darmdfec->regs;
  29. unsigned int i = 0;
  30. printf("\noffset: phy_adr, value: 0x%x\n", readl(&regs->phyadr));
  31. printf("offset: smi, value: 0x%x\n", readl(&regs->smi));
  32. for (i = 0x400; i <= 0x4e4; i += 4)
  33. printf("offset: 0x%x, value: 0x%x\n",
  34. i, readl(ARMD1_FEC_BASE + i));
  35. return 0;
  36. }
  37. #endif
  38. static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond)
  39. {
  40. u32 timeout = PHY_WAIT_ITERATIONS;
  41. u32 reg_val;
  42. while (--timeout) {
  43. reg_val = readl(reg);
  44. if (cond && (reg_val & flag))
  45. break;
  46. else if (!cond && !(reg_val & flag))
  47. break;
  48. udelay(PHY_WAIT_MICRO_SECONDS);
  49. }
  50. return !timeout;
  51. }
  52. static int smi_reg_read(struct mii_dev *bus, int phy_addr, int devad,
  53. int phy_reg)
  54. {
  55. u16 value = 0;
  56. struct eth_device *dev = eth_get_dev_by_name(bus->name);
  57. struct armdfec_device *darmdfec = to_darmdfec(dev);
  58. struct armdfec_reg *regs = darmdfec->regs;
  59. u32 val;
  60. if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
  61. val = readl(&regs->phyadr);
  62. value = val & 0x1f;
  63. return value;
  64. }
  65. /* check parameters */
  66. if (phy_addr > PHY_MASK) {
  67. printf("ARMD100 FEC: (%s) Invalid phy address: 0x%X\n",
  68. __func__, phy_addr);
  69. return -EINVAL;
  70. }
  71. if (phy_reg > PHY_MASK) {
  72. printf("ARMD100 FEC: (%s) Invalid register offset: 0x%X\n",
  73. __func__, phy_reg);
  74. return -EINVAL;
  75. }
  76. /* wait for the SMI register to become available */
  77. if (armdfec_phy_timeout(&regs->smi, SMI_BUSY, false)) {
  78. printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
  79. return -1;
  80. }
  81. writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, &regs->smi);
  82. /* now wait for the data to be valid */
  83. if (armdfec_phy_timeout(&regs->smi, SMI_R_VALID, true)) {
  84. val = readl(&regs->smi);
  85. printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n",
  86. __func__, val);
  87. return -1;
  88. }
  89. val = readl(&regs->smi);
  90. value = val & 0xffff;
  91. return value;
  92. }
  93. static int smi_reg_write(struct mii_dev *bus, int phy_addr, int devad,
  94. int phy_reg, u16 value)
  95. {
  96. struct eth_device *dev = eth_get_dev_by_name(bus->name);
  97. struct armdfec_device *darmdfec = to_darmdfec(dev);
  98. struct armdfec_reg *regs = darmdfec->regs;
  99. if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
  100. clrsetbits_le32(&regs->phyadr, 0x1f, value & 0x1f);
  101. return 0;
  102. }
  103. /* check parameters */
  104. if (phy_addr > PHY_MASK) {
  105. printf("ARMD100 FEC: (%s) Invalid phy address\n", __func__);
  106. return -EINVAL;
  107. }
  108. if (phy_reg > PHY_MASK) {
  109. printf("ARMD100 FEC: (%s) Invalid register offset\n", __func__);
  110. return -EINVAL;
  111. }
  112. /* wait for the SMI register to become available */
  113. if (armdfec_phy_timeout(&regs->smi, SMI_BUSY, false)) {
  114. printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__);
  115. return -1;
  116. }
  117. writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_W | (value & 0xffff),
  118. &regs->smi);
  119. return 0;
  120. }
  121. /*
  122. * Abort any transmit and receive operations and put DMA
  123. * in idle state. AT and AR bits are cleared upon entering
  124. * in IDLE state. So poll those bits to verify operation.
  125. */
  126. static void abortdma(struct eth_device *dev)
  127. {
  128. struct armdfec_device *darmdfec = to_darmdfec(dev);
  129. struct armdfec_reg *regs = darmdfec->regs;
  130. int delay;
  131. int maxretries = 40;
  132. u32 tmp;
  133. while (--maxretries) {
  134. writel(SDMA_CMD_AR | SDMA_CMD_AT, &regs->sdma_cmd);
  135. udelay(100);
  136. delay = 10;
  137. while (--delay) {
  138. tmp = readl(&regs->sdma_cmd);
  139. if (!(tmp & (SDMA_CMD_AR | SDMA_CMD_AT)))
  140. break;
  141. udelay(10);
  142. }
  143. if (delay)
  144. break;
  145. }
  146. if (!maxretries)
  147. printf("ARMD100 FEC: (%s) DMA Stuck\n", __func__);
  148. }
  149. static inline u32 nibble_swapping_32_bit(u32 x)
  150. {
  151. return ((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4);
  152. }
  153. static inline u32 nibble_swapping_16_bit(u32 x)
  154. {
  155. return ((x & 0x0000f0f0) >> 4) | ((x & 0x00000f0f) << 4);
  156. }
  157. static inline u32 flip_4_bits(u32 x)
  158. {
  159. return ((x & 0x01) << 3) | ((x & 0x002) << 1)
  160. | ((x & 0x04) >> 1) | ((x & 0x008) >> 3);
  161. }
  162. /*
  163. * This function will calculate the hash function of the address.
  164. * depends on the hash mode and hash size.
  165. * Inputs
  166. * mach - the 2 most significant bytes of the MAC address.
  167. * macl - the 4 least significant bytes of the MAC address.
  168. * Outputs
  169. * return the calculated entry.
  170. */
  171. static u32 hash_function(u32 mach, u32 macl)
  172. {
  173. u32 hashresult;
  174. u32 addrh;
  175. u32 addrl;
  176. u32 addr0;
  177. u32 addr1;
  178. u32 addr2;
  179. u32 addr3;
  180. u32 addrhswapped;
  181. u32 addrlswapped;
  182. addrh = nibble_swapping_16_bit(mach);
  183. addrl = nibble_swapping_32_bit(macl);
  184. addrhswapped = flip_4_bits(addrh & 0xf)
  185. + ((flip_4_bits((addrh >> 4) & 0xf)) << 4)
  186. + ((flip_4_bits((addrh >> 8) & 0xf)) << 8)
  187. + ((flip_4_bits((addrh >> 12) & 0xf)) << 12);
  188. addrlswapped = flip_4_bits(addrl & 0xf)
  189. + ((flip_4_bits((addrl >> 4) & 0xf)) << 4)
  190. + ((flip_4_bits((addrl >> 8) & 0xf)) << 8)
  191. + ((flip_4_bits((addrl >> 12) & 0xf)) << 12)
  192. + ((flip_4_bits((addrl >> 16) & 0xf)) << 16)
  193. + ((flip_4_bits((addrl >> 20) & 0xf)) << 20)
  194. + ((flip_4_bits((addrl >> 24) & 0xf)) << 24)
  195. + ((flip_4_bits((addrl >> 28) & 0xf)) << 28);
  196. addrh = addrhswapped;
  197. addrl = addrlswapped;
  198. addr0 = (addrl >> 2) & 0x03f;
  199. addr1 = (addrl & 0x003) | (((addrl >> 8) & 0x7f) << 2);
  200. addr2 = (addrl >> 15) & 0x1ff;
  201. addr3 = ((addrl >> 24) & 0x0ff) | ((addrh & 1) << 8);
  202. hashresult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
  203. hashresult = hashresult & 0x07ff;
  204. return hashresult;
  205. }
  206. /*
  207. * This function will add an entry to the address table.
  208. * depends on the hash mode and hash size that was initialized.
  209. * Inputs
  210. * mach - the 2 most significant bytes of the MAC address.
  211. * macl - the 4 least significant bytes of the MAC address.
  212. * skip - if 1, skip this address.
  213. * rd - the RD field in the address table.
  214. * Outputs
  215. * address table entry is added.
  216. * 0 if success.
  217. * -ENOSPC if table full
  218. */
  219. static int add_del_hash_entry(struct armdfec_device *darmdfec, u32 mach,
  220. u32 macl, u32 rd, u32 skip, int del)
  221. {
  222. struct addr_table_entry_t *entry, *start;
  223. u32 newhi;
  224. u32 newlo;
  225. u32 i;
  226. newlo = (((mach >> 4) & 0xf) << 15)
  227. | (((mach >> 0) & 0xf) << 11)
  228. | (((mach >> 12) & 0xf) << 7)
  229. | (((mach >> 8) & 0xf) << 3)
  230. | (((macl >> 20) & 0x1) << 31)
  231. | (((macl >> 16) & 0xf) << 27)
  232. | (((macl >> 28) & 0xf) << 23)
  233. | (((macl >> 24) & 0xf) << 19)
  234. | (skip << HTESKIP) | (rd << HTERDBIT)
  235. | HTEVALID;
  236. newhi = (((macl >> 4) & 0xf) << 15)
  237. | (((macl >> 0) & 0xf) << 11)
  238. | (((macl >> 12) & 0xf) << 7)
  239. | (((macl >> 8) & 0xf) << 3)
  240. | (((macl >> 21) & 0x7) << 0);
  241. /*
  242. * Pick the appropriate table, start scanning for free/reusable
  243. * entries at the index obtained by hashing the specified MAC address
  244. */
  245. start = (struct addr_table_entry_t *)(darmdfec->htpr);
  246. entry = start + hash_function(mach, macl);
  247. for (i = 0; i < HOP_NUMBER; i++) {
  248. if (!(entry->lo & HTEVALID)) {
  249. break;
  250. } else {
  251. /* if same address put in same position */
  252. if (((entry->lo & 0xfffffff8) == (newlo & 0xfffffff8))
  253. && (entry->hi == newhi))
  254. break;
  255. }
  256. if (entry == start + 0x7ff)
  257. entry = start;
  258. else
  259. entry++;
  260. }
  261. if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) &&
  262. (entry->hi != newhi) && del)
  263. return 0;
  264. if (i == HOP_NUMBER) {
  265. if (!del) {
  266. printf("ARMD100 FEC: (%s) table section is full\n",
  267. __func__);
  268. return -ENOSPC;
  269. } else {
  270. return 0;
  271. }
  272. }
  273. /*
  274. * Update the selected entry
  275. */
  276. if (del) {
  277. entry->hi = 0;
  278. entry->lo = 0;
  279. } else {
  280. entry->hi = newhi;
  281. entry->lo = newlo;
  282. }
  283. return 0;
  284. }
  285. /*
  286. * Create an addressTable entry from MAC address info
  287. * found in the specifed net_device struct
  288. *
  289. * Input : pointer to ethernet interface network device structure
  290. * Output : N/A
  291. */
  292. static void update_hash_table_mac_address(struct armdfec_device *darmdfec,
  293. u8 *oaddr, u8 *addr)
  294. {
  295. u32 mach;
  296. u32 macl;
  297. /* Delete old entry */
  298. if (oaddr) {
  299. mach = (oaddr[0] << 8) | oaddr[1];
  300. macl = (oaddr[2] << 24) | (oaddr[3] << 16) |
  301. (oaddr[4] << 8) | oaddr[5];
  302. add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE);
  303. }
  304. /* Add new entry */
  305. mach = (addr[0] << 8) | addr[1];
  306. macl = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
  307. add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD);
  308. }
  309. /* Address Table Initialization */
  310. static void init_hashtable(struct eth_device *dev)
  311. {
  312. struct armdfec_device *darmdfec = to_darmdfec(dev);
  313. struct armdfec_reg *regs = darmdfec->regs;
  314. memset(darmdfec->htpr, 0, HASH_ADDR_TABLE_SIZE);
  315. writel((u32)darmdfec->htpr, &regs->htpr);
  316. }
  317. /*
  318. * This detects PHY chip from address 0-31 by reading PHY status
  319. * registers. PHY chip can be connected at any of this address.
  320. */
  321. static int ethernet_phy_detect(struct eth_device *dev)
  322. {
  323. u32 val;
  324. u16 tmp, mii_status;
  325. u8 addr;
  326. for (addr = 0; addr < 32; addr++) {
  327. if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status) != 0)
  328. /* try next phy */
  329. continue;
  330. /* invalid MII status. More validation required here... */
  331. if (mii_status == 0 || mii_status == 0xffff)
  332. /* try next phy */
  333. continue;
  334. if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0)
  335. /* try next phy */
  336. continue;
  337. val = tmp << 16;
  338. if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0)
  339. /* try next phy */
  340. continue;
  341. val |= tmp;
  342. if ((val & 0xfffffff0) != 0)
  343. return addr;
  344. }
  345. return -1;
  346. }
  347. static void armdfec_init_rx_desc_ring(struct armdfec_device *darmdfec)
  348. {
  349. struct rx_desc *p_rx_desc;
  350. int i;
  351. /* initialize the Rx descriptors ring */
  352. p_rx_desc = darmdfec->p_rxdesc;
  353. for (i = 0; i < RINGSZ; i++) {
  354. p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
  355. p_rx_desc->buf_size = PKTSIZE_ALIGN;
  356. p_rx_desc->byte_cnt = 0;
  357. p_rx_desc->buf_ptr = darmdfec->p_rxbuf + i * PKTSIZE_ALIGN;
  358. if (i == (RINGSZ - 1)) {
  359. p_rx_desc->nxtdesc_p = darmdfec->p_rxdesc;
  360. } else {
  361. p_rx_desc->nxtdesc_p = (struct rx_desc *)
  362. ((u32)p_rx_desc + ARMDFEC_RXQ_DESC_ALIGNED_SIZE);
  363. p_rx_desc = p_rx_desc->nxtdesc_p;
  364. }
  365. }
  366. darmdfec->p_rxdesc_curr = darmdfec->p_rxdesc;
  367. }
  368. static int armdfec_init(struct eth_device *dev, bd_t *bd)
  369. {
  370. struct armdfec_device *darmdfec = to_darmdfec(dev);
  371. struct armdfec_reg *regs = darmdfec->regs;
  372. int phy_adr;
  373. u32 temp;
  374. armdfec_init_rx_desc_ring(darmdfec);
  375. /* Disable interrupts */
  376. writel(0, &regs->im);
  377. writel(0, &regs->ic);
  378. /* Write to ICR to clear interrupts. */
  379. writel(0, &regs->iwc);
  380. /*
  381. * Abort any transmit and receive operations and put DMA
  382. * in idle state.
  383. */
  384. abortdma(dev);
  385. /* Initialize address hash table */
  386. init_hashtable(dev);
  387. /* SDMA configuration */
  388. writel(SDCR_BSZ8 | /* Burst size = 32 bytes */
  389. SDCR_RIFB | /* Rx interrupt on frame */
  390. SDCR_BLMT | /* Little endian transmit */
  391. SDCR_BLMR | /* Little endian receive */
  392. SDCR_RC_MAX_RETRANS, /* Max retransmit count */
  393. &regs->sdma_conf);
  394. /* Port Configuration */
  395. writel(PCR_HS, &regs->pconf); /* Hash size is 1/2kb */
  396. /* Set extended port configuration */
  397. writel(PCXR_2BSM | /* Two byte suffix aligns IP hdr */
  398. PCXR_DSCP_EN | /* Enable DSCP in IP */
  399. PCXR_MFL_1536 | /* Set MTU = 1536 */
  400. PCXR_FLP | /* do not force link pass */
  401. PCXR_TX_HIGH_PRI, /* Transmit - high priority queue */
  402. &regs->pconf_ext);
  403. update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr);
  404. /* Update TX and RX queue descriptor register */
  405. temp = (u32)&regs->txcdp[TXQ];
  406. writel((u32)darmdfec->p_txdesc, temp);
  407. temp = (u32)&regs->rxfdp[RXQ];
  408. writel((u32)darmdfec->p_rxdesc, temp);
  409. temp = (u32)&regs->rxcdp[RXQ];
  410. writel((u32)darmdfec->p_rxdesc_curr, temp);
  411. /* Enable Interrupts */
  412. writel(ALL_INTS, &regs->im);
  413. /* Enable Ethernet Port */
  414. setbits_le32(&regs->pconf, PCR_EN);
  415. /* Enable RX DMA engine */
  416. setbits_le32(&regs->sdma_cmd, SDMA_CMD_ERD);
  417. #ifdef DEBUG
  418. eth_dump_regs(dev);
  419. #endif
  420. #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
  421. #if defined(CONFIG_PHY_BASE_ADR)
  422. miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, CONFIG_PHY_BASE_ADR);
  423. #else
  424. /* Search phy address from range 0-31 */
  425. phy_adr = ethernet_phy_detect(dev);
  426. if (phy_adr < 0) {
  427. printf("ARMD100 FEC: PHY not detected at address range 0-31\n");
  428. return -1;
  429. } else {
  430. debug("ARMD100 FEC: PHY detected at addr %d\n", phy_adr);
  431. miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, phy_adr);
  432. }
  433. #endif
  434. #if defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
  435. /* Wait up to 5s for the link status */
  436. for (i = 0; i < 5; i++) {
  437. u16 phy_adr;
  438. miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr);
  439. /* Return if we get link up */
  440. if (miiphy_link(dev->name, phy_adr))
  441. return 0;
  442. udelay(1000000);
  443. }
  444. printf("ARMD100 FEC: No link on %s\n", dev->name);
  445. return -1;
  446. #endif
  447. #endif
  448. return 0;
  449. }
  450. static void armdfec_halt(struct eth_device *dev)
  451. {
  452. struct armdfec_device *darmdfec = to_darmdfec(dev);
  453. struct armdfec_reg *regs = darmdfec->regs;
  454. /* Stop RX DMA */
  455. clrbits_le32(&regs->sdma_cmd, SDMA_CMD_ERD);
  456. /*
  457. * Abort any transmit and receive operations and put DMA
  458. * in idle state.
  459. */
  460. abortdma(dev);
  461. /* Disable interrupts */
  462. writel(0, &regs->im);
  463. writel(0, &regs->ic);
  464. writel(0, &regs->iwc);
  465. /* Disable Port */
  466. clrbits_le32(&regs->pconf, PCR_EN);
  467. }
  468. static int armdfec_send(struct eth_device *dev, void *dataptr, int datasize)
  469. {
  470. struct armdfec_device *darmdfec = to_darmdfec(dev);
  471. struct armdfec_reg *regs = darmdfec->regs;
  472. struct tx_desc *p_txdesc = darmdfec->p_txdesc;
  473. void *p = (void *)dataptr;
  474. int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS;
  475. u32 cmd_sts, temp;
  476. /* Copy buffer if it's misaligned */
  477. if ((u32)dataptr & 0x07) {
  478. if (datasize > PKTSIZE_ALIGN) {
  479. printf("ARMD100 FEC: Non-aligned data too large (%d)\n",
  480. datasize);
  481. return -1;
  482. }
  483. memcpy(darmdfec->p_aligned_txbuf, p, datasize);
  484. p = darmdfec->p_aligned_txbuf;
  485. }
  486. p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC;
  487. p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC;
  488. p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA;
  489. p_txdesc->cmd_sts |= TX_EN_INT;
  490. p_txdesc->buf_ptr = p;
  491. p_txdesc->byte_cnt = datasize;
  492. /* Apply send command using high priority TX queue */
  493. temp = (u32)&regs->txcdp[TXQ];
  494. writel((u32)p_txdesc, temp);
  495. writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, &regs->sdma_cmd);
  496. /*
  497. * wait for packet xmit completion
  498. */
  499. cmd_sts = readl(&p_txdesc->cmd_sts);
  500. while (cmd_sts & BUF_OWNED_BY_DMA) {
  501. /* return fail if error is detected */
  502. if ((cmd_sts & (TX_ERROR | TX_LAST_DESC)) ==
  503. (TX_ERROR | TX_LAST_DESC)) {
  504. printf("ARMD100 FEC: (%s) in xmit packet\n", __func__);
  505. return -1;
  506. }
  507. cmd_sts = readl(&p_txdesc->cmd_sts);
  508. if (!(retry--)) {
  509. printf("ARMD100 FEC: (%s) xmit packet timeout!\n",
  510. __func__);
  511. return -1;
  512. }
  513. }
  514. return 0;
  515. }
  516. static int armdfec_recv(struct eth_device *dev)
  517. {
  518. struct armdfec_device *darmdfec = to_darmdfec(dev);
  519. struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr;
  520. u32 cmd_sts;
  521. u32 timeout = 0;
  522. u32 temp;
  523. /* wait untill rx packet available or timeout */
  524. do {
  525. if (timeout < PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS) {
  526. timeout++;
  527. } else {
  528. debug("ARMD100 FEC: %s time out...\n", __func__);
  529. return -1;
  530. }
  531. } while (readl(&p_rxdesc_curr->cmd_sts) & BUF_OWNED_BY_DMA);
  532. if (p_rxdesc_curr->byte_cnt != 0) {
  533. debug("ARMD100 FEC: %s: Received %d byte Packet @ 0x%x"
  534. "(cmd_sts= %08x)\n", __func__,
  535. (u32)p_rxdesc_curr->byte_cnt,
  536. (u32)p_rxdesc_curr->buf_ptr,
  537. (u32)p_rxdesc_curr->cmd_sts);
  538. }
  539. /*
  540. * In case received a packet without first/last bits on
  541. * OR the error summary bit is on,
  542. * the packets needs to be dropeed.
  543. */
  544. cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
  545. if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
  546. (RX_FIRST_DESC | RX_LAST_DESC)) {
  547. printf("ARMD100 FEC: (%s) Dropping packet spread on"
  548. " multiple descriptors\n", __func__);
  549. } else if (cmd_sts & RX_ERROR) {
  550. printf("ARMD100 FEC: (%s) Dropping packet with errors\n",
  551. __func__);
  552. } else {
  553. /* !!! call higher layer processing */
  554. debug("ARMD100 FEC: (%s) Sending Received packet to"
  555. " upper layer (net_process_received_packet)\n", __func__);
  556. /*
  557. * let the upper layer handle the packet, subtract offset
  558. * as two dummy bytes are added in received buffer see
  559. * PORT_CONFIG_EXT register bit TWO_Byte_Stuff_Mode bit.
  560. */
  561. net_process_received_packet(
  562. p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET,
  563. (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
  564. }
  565. /*
  566. * free these descriptors and point next in the ring
  567. */
  568. p_rxdesc_curr->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
  569. p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
  570. p_rxdesc_curr->byte_cnt = 0;
  571. temp = (u32)&darmdfec->p_rxdesc_curr;
  572. writel((u32)p_rxdesc_curr->nxtdesc_p, temp);
  573. return 0;
  574. }
  575. int armada100_fec_register(unsigned long base_addr)
  576. {
  577. struct armdfec_device *darmdfec;
  578. struct eth_device *dev;
  579. darmdfec = malloc(sizeof(struct armdfec_device));
  580. if (!darmdfec)
  581. goto error;
  582. memset(darmdfec, 0, sizeof(struct armdfec_device));
  583. darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE);
  584. if (!darmdfec->htpr)
  585. goto error1;
  586. darmdfec->p_rxdesc = memalign(PKTALIGN,
  587. ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1);
  588. if (!darmdfec->p_rxdesc)
  589. goto error1;
  590. darmdfec->p_rxbuf = memalign(PKTALIGN, RINGSZ * PKTSIZE_ALIGN + 1);
  591. if (!darmdfec->p_rxbuf)
  592. goto error1;
  593. darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
  594. if (!darmdfec->p_aligned_txbuf)
  595. goto error1;
  596. darmdfec->p_txdesc = memalign(PKTALIGN, sizeof(struct tx_desc) + 1);
  597. if (!darmdfec->p_txdesc)
  598. goto error1;
  599. dev = &darmdfec->dev;
  600. /* Assign ARMADA100 Fast Ethernet Controller Base Address */
  601. darmdfec->regs = (void *)base_addr;
  602. /* must be less than sizeof(dev->name) */
  603. strcpy(dev->name, "armd-fec0");
  604. dev->init = armdfec_init;
  605. dev->halt = armdfec_halt;
  606. dev->send = armdfec_send;
  607. dev->recv = armdfec_recv;
  608. eth_register(dev);
  609. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  610. int retval;
  611. struct mii_dev *mdiodev = mdio_alloc();
  612. if (!mdiodev)
  613. return -ENOMEM;
  614. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  615. mdiodev->read = smi_reg_read;
  616. mdiodev->write = smi_reg_write;
  617. retval = mdio_register(mdiodev);
  618. if (retval < 0)
  619. return retval;
  620. #endif
  621. return 0;
  622. error1:
  623. free(darmdfec->p_aligned_txbuf);
  624. free(darmdfec->p_rxbuf);
  625. free(darmdfec->p_rxdesc);
  626. free(darmdfec->htpr);
  627. error:
  628. free(darmdfec);
  629. printf("AMD100 FEC: (%s) Failed to allocate memory\n", __func__);
  630. return -1;
  631. }