board.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
  4. * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  5. *
  6. * (C) Copyright 2007-2011
  7. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  8. * Tom Cubie <tangliang@allwinnertech.com>
  9. *
  10. * Some board init for the Allwinner A10-evb board.
  11. */
  12. #include <common.h>
  13. #include <dm.h>
  14. #include <env.h>
  15. #include <mmc.h>
  16. #include <axp_pmic.h>
  17. #include <generic-phy.h>
  18. #include <phy-sun4i-usb.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/cpu.h>
  21. #include <asm/arch/display.h>
  22. #include <asm/arch/dram.h>
  23. #include <asm/arch/gpio.h>
  24. #include <asm/arch/mmc.h>
  25. #include <asm/arch/spl.h>
  26. #include <u-boot/crc.h>
  27. #ifndef CONFIG_ARM64
  28. #include <asm/armv7.h>
  29. #endif
  30. #include <asm/gpio.h>
  31. #include <asm/io.h>
  32. #include <u-boot/crc.h>
  33. #include <env_internal.h>
  34. #include <linux/libfdt.h>
  35. #include <nand.h>
  36. #include <net.h>
  37. #include <spl.h>
  38. #include <sy8106a.h>
  39. #include <asm/setup.h>
  40. #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
  41. /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
  42. int soft_i2c_gpio_sda;
  43. int soft_i2c_gpio_scl;
  44. static int soft_i2c_board_init(void)
  45. {
  46. int ret;
  47. soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
  48. if (soft_i2c_gpio_sda < 0) {
  49. printf("Error invalid soft i2c sda pin: '%s', err %d\n",
  50. CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
  51. return soft_i2c_gpio_sda;
  52. }
  53. ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
  54. if (ret) {
  55. printf("Error requesting soft i2c sda pin: '%s', err %d\n",
  56. CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
  57. return ret;
  58. }
  59. soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
  60. if (soft_i2c_gpio_scl < 0) {
  61. printf("Error invalid soft i2c scl pin: '%s', err %d\n",
  62. CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
  63. return soft_i2c_gpio_scl;
  64. }
  65. ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
  66. if (ret) {
  67. printf("Error requesting soft i2c scl pin: '%s', err %d\n",
  68. CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
  69. return ret;
  70. }
  71. return 0;
  72. }
  73. #else
  74. static int soft_i2c_board_init(void) { return 0; }
  75. #endif
  76. DECLARE_GLOBAL_DATA_PTR;
  77. void i2c_init_board(void)
  78. {
  79. #ifdef CONFIG_I2C0_ENABLE
  80. #if defined(CONFIG_MACH_SUN4I) || \
  81. defined(CONFIG_MACH_SUN5I) || \
  82. defined(CONFIG_MACH_SUN7I) || \
  83. defined(CONFIG_MACH_SUN8I_R40)
  84. sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
  85. sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
  86. clock_twi_onoff(0, 1);
  87. #elif defined(CONFIG_MACH_SUN6I)
  88. sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
  89. sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
  90. clock_twi_onoff(0, 1);
  91. #elif defined(CONFIG_MACH_SUN8I)
  92. sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
  93. sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
  94. clock_twi_onoff(0, 1);
  95. #elif defined(CONFIG_MACH_SUN50I)
  96. sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
  97. sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
  98. clock_twi_onoff(0, 1);
  99. #endif
  100. #endif
  101. #ifdef CONFIG_I2C1_ENABLE
  102. #if defined(CONFIG_MACH_SUN4I) || \
  103. defined(CONFIG_MACH_SUN7I) || \
  104. defined(CONFIG_MACH_SUN8I_R40)
  105. sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
  106. sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
  107. clock_twi_onoff(1, 1);
  108. #elif defined(CONFIG_MACH_SUN5I)
  109. sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
  110. sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
  111. clock_twi_onoff(1, 1);
  112. #elif defined(CONFIG_MACH_SUN6I)
  113. sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
  114. sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
  115. clock_twi_onoff(1, 1);
  116. #elif defined(CONFIG_MACH_SUN8I)
  117. sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
  118. sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
  119. clock_twi_onoff(1, 1);
  120. #elif defined(CONFIG_MACH_SUN50I)
  121. sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
  122. sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
  123. clock_twi_onoff(1, 1);
  124. #endif
  125. #endif
  126. #ifdef CONFIG_I2C2_ENABLE
  127. #if defined(CONFIG_MACH_SUN4I) || \
  128. defined(CONFIG_MACH_SUN7I) || \
  129. defined(CONFIG_MACH_SUN8I_R40)
  130. sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
  131. sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
  132. clock_twi_onoff(2, 1);
  133. #elif defined(CONFIG_MACH_SUN5I)
  134. sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
  135. sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
  136. clock_twi_onoff(2, 1);
  137. #elif defined(CONFIG_MACH_SUN6I)
  138. sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
  139. sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
  140. clock_twi_onoff(2, 1);
  141. #elif defined(CONFIG_MACH_SUN8I)
  142. sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
  143. sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
  144. clock_twi_onoff(2, 1);
  145. #elif defined(CONFIG_MACH_SUN50I)
  146. sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
  147. sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
  148. clock_twi_onoff(2, 1);
  149. #endif
  150. #endif
  151. #ifdef CONFIG_I2C3_ENABLE
  152. #if defined(CONFIG_MACH_SUN6I)
  153. sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
  154. sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
  155. clock_twi_onoff(3, 1);
  156. #elif defined(CONFIG_MACH_SUN7I) || \
  157. defined(CONFIG_MACH_SUN8I_R40)
  158. sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
  159. sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
  160. clock_twi_onoff(3, 1);
  161. #endif
  162. #endif
  163. #ifdef CONFIG_I2C4_ENABLE
  164. #if defined(CONFIG_MACH_SUN7I) || \
  165. defined(CONFIG_MACH_SUN8I_R40)
  166. sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
  167. sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
  168. clock_twi_onoff(4, 1);
  169. #endif
  170. #endif
  171. #ifdef CONFIG_R_I2C_ENABLE
  172. #ifdef CONFIG_MACH_SUN50I
  173. clock_twi_onoff(5, 1);
  174. sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
  175. sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
  176. #else
  177. clock_twi_onoff(5, 1);
  178. sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
  179. sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
  180. #endif
  181. #endif
  182. }
  183. #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
  184. enum env_location env_get_location(enum env_operation op, int prio)
  185. {
  186. switch (prio) {
  187. case 0:
  188. return ENVL_FAT;
  189. case 1:
  190. return ENVL_MMC;
  191. default:
  192. return ENVL_UNKNOWN;
  193. }
  194. }
  195. #endif
  196. #ifdef CONFIG_DM_MMC
  197. static void mmc_pinmux_setup(int sdc);
  198. #endif
  199. /* add board specific code here */
  200. int board_init(void)
  201. {
  202. __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
  203. gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
  204. #ifndef CONFIG_ARM64
  205. asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
  206. debug("id_pfr1: 0x%08x\n", id_pfr1);
  207. /* Generic Timer Extension available? */
  208. if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
  209. uint32_t freq;
  210. debug("Setting CNTFRQ\n");
  211. /*
  212. * CNTFRQ is a secure register, so we will crash if we try to
  213. * write this from the non-secure world (read is OK, though).
  214. * In case some bootcode has already set the correct value,
  215. * we avoid the risk of writing to it.
  216. */
  217. asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
  218. if (freq != COUNTER_FREQUENCY) {
  219. debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
  220. freq, COUNTER_FREQUENCY);
  221. #ifdef CONFIG_NON_SECURE
  222. printf("arch timer frequency is wrong, but cannot adjust it\n");
  223. #else
  224. asm volatile("mcr p15, 0, %0, c14, c0, 0"
  225. : : "r"(COUNTER_FREQUENCY));
  226. #endif
  227. }
  228. }
  229. #endif /* !CONFIG_ARM64 */
  230. ret = axp_gpio_init();
  231. if (ret)
  232. return ret;
  233. #ifdef CONFIG_SATAPWR
  234. satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
  235. gpio_request(satapwr_pin, "satapwr");
  236. gpio_direction_output(satapwr_pin, 1);
  237. /* Give attached sata device time to power-up to avoid link timeouts */
  238. mdelay(500);
  239. #endif
  240. #ifdef CONFIG_MACPWR
  241. macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
  242. gpio_request(macpwr_pin, "macpwr");
  243. gpio_direction_output(macpwr_pin, 1);
  244. #endif
  245. #ifdef CONFIG_DM_I2C
  246. /*
  247. * Temporary workaround for enabling I2C clocks until proper sunxi DM
  248. * clk, reset and pinctrl drivers land.
  249. */
  250. i2c_init_board();
  251. #endif
  252. #ifdef CONFIG_DM_MMC
  253. /*
  254. * Temporary workaround for enabling MMC clocks until a sunxi DM
  255. * pinctrl driver lands.
  256. */
  257. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
  258. #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
  259. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
  260. #endif
  261. #endif /* CONFIG_DM_MMC */
  262. /* Uses dm gpio code so do this here and not in i2c_init_board() */
  263. return soft_i2c_board_init();
  264. }
  265. /*
  266. * On older SoCs the SPL is actually at address zero, so using NULL as
  267. * an error value does not work.
  268. */
  269. #define INVALID_SPL_HEADER ((void *)~0UL)
  270. static struct boot_file_head * get_spl_header(uint8_t req_version)
  271. {
  272. struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
  273. uint8_t spl_header_version = spl->spl_signature[3];
  274. /* Is there really the SPL header (still) there? */
  275. if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
  276. return INVALID_SPL_HEADER;
  277. if (spl_header_version < req_version) {
  278. printf("sunxi SPL version mismatch: expected %u, got %u\n",
  279. req_version, spl_header_version);
  280. return INVALID_SPL_HEADER;
  281. }
  282. return spl;
  283. }
  284. int dram_init(void)
  285. {
  286. struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
  287. if (spl == INVALID_SPL_HEADER)
  288. gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
  289. PHYS_SDRAM_0_SIZE);
  290. else
  291. gd->ram_size = (phys_addr_t)spl->dram_size << 20;
  292. if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
  293. gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
  294. return 0;
  295. }
  296. #if defined(CONFIG_NAND_SUNXI)
  297. static void nand_pinmux_setup(void)
  298. {
  299. unsigned int pin;
  300. for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
  301. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
  302. #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
  303. for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
  304. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
  305. #endif
  306. /* sun4i / sun7i do have a PC23, but it is not used for nand,
  307. * only sun7i has a PC24 */
  308. #ifdef CONFIG_MACH_SUN7I
  309. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
  310. #endif
  311. }
  312. static void nand_clock_setup(void)
  313. {
  314. struct sunxi_ccm_reg *const ccm =
  315. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  316. setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
  317. #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
  318. defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
  319. setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
  320. #endif
  321. setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
  322. }
  323. void board_nand_init(void)
  324. {
  325. nand_pinmux_setup();
  326. nand_clock_setup();
  327. #ifndef CONFIG_SPL_BUILD
  328. sunxi_nand_init();
  329. #endif
  330. }
  331. #endif
  332. #ifdef CONFIG_MMC
  333. static void mmc_pinmux_setup(int sdc)
  334. {
  335. unsigned int pin;
  336. __maybe_unused int pins;
  337. switch (sdc) {
  338. case 0:
  339. /* SDC0: PF0-PF5 */
  340. for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
  341. sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
  342. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  343. sunxi_gpio_set_drv(pin, 2);
  344. }
  345. break;
  346. case 1:
  347. pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
  348. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
  349. defined(CONFIG_MACH_SUN8I_R40)
  350. if (pins == SUNXI_GPIO_H) {
  351. /* SDC1: PH22-PH-27 */
  352. for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
  353. sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
  354. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  355. sunxi_gpio_set_drv(pin, 2);
  356. }
  357. } else {
  358. /* SDC1: PG0-PG5 */
  359. for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  360. sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
  361. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  362. sunxi_gpio_set_drv(pin, 2);
  363. }
  364. }
  365. #elif defined(CONFIG_MACH_SUN5I)
  366. /* SDC1: PG3-PG8 */
  367. for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
  368. sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
  369. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  370. sunxi_gpio_set_drv(pin, 2);
  371. }
  372. #elif defined(CONFIG_MACH_SUN6I)
  373. /* SDC1: PG0-PG5 */
  374. for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  375. sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
  376. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  377. sunxi_gpio_set_drv(pin, 2);
  378. }
  379. #elif defined(CONFIG_MACH_SUN8I)
  380. if (pins == SUNXI_GPIO_D) {
  381. /* SDC1: PD2-PD7 */
  382. for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
  383. sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
  384. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  385. sunxi_gpio_set_drv(pin, 2);
  386. }
  387. } else {
  388. /* SDC1: PG0-PG5 */
  389. for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  390. sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
  391. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  392. sunxi_gpio_set_drv(pin, 2);
  393. }
  394. }
  395. #endif
  396. break;
  397. case 2:
  398. pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
  399. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
  400. /* SDC2: PC6-PC11 */
  401. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
  402. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  403. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  404. sunxi_gpio_set_drv(pin, 2);
  405. }
  406. #elif defined(CONFIG_MACH_SUN5I)
  407. if (pins == SUNXI_GPIO_E) {
  408. /* SDC2: PE4-PE9 */
  409. for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
  410. sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
  411. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  412. sunxi_gpio_set_drv(pin, 2);
  413. }
  414. } else {
  415. /* SDC2: PC6-PC15 */
  416. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  417. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  418. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  419. sunxi_gpio_set_drv(pin, 2);
  420. }
  421. }
  422. #elif defined(CONFIG_MACH_SUN6I)
  423. if (pins == SUNXI_GPIO_A) {
  424. /* SDC2: PA9-PA14 */
  425. for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
  426. sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
  427. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  428. sunxi_gpio_set_drv(pin, 2);
  429. }
  430. } else {
  431. /* SDC2: PC6-PC15, PC24 */
  432. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  433. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  434. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  435. sunxi_gpio_set_drv(pin, 2);
  436. }
  437. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
  438. sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  439. sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  440. }
  441. #elif defined(CONFIG_MACH_SUN8I_R40)
  442. /* SDC2: PC6-PC15, PC24 */
  443. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  444. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  445. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  446. sunxi_gpio_set_drv(pin, 2);
  447. }
  448. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
  449. sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  450. sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  451. #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
  452. /* SDC2: PC5-PC6, PC8-PC16 */
  453. for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
  454. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  455. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  456. sunxi_gpio_set_drv(pin, 2);
  457. }
  458. for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
  459. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  460. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  461. sunxi_gpio_set_drv(pin, 2);
  462. }
  463. #elif defined(CONFIG_MACH_SUN50I_H6)
  464. /* SDC2: PC4-PC14 */
  465. for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
  466. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  467. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  468. sunxi_gpio_set_drv(pin, 2);
  469. }
  470. #elif defined(CONFIG_MACH_SUN9I)
  471. /* SDC2: PC6-PC16 */
  472. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
  473. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  474. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  475. sunxi_gpio_set_drv(pin, 2);
  476. }
  477. #endif
  478. break;
  479. case 3:
  480. pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
  481. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
  482. defined(CONFIG_MACH_SUN8I_R40)
  483. /* SDC3: PI4-PI9 */
  484. for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
  485. sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
  486. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  487. sunxi_gpio_set_drv(pin, 2);
  488. }
  489. #elif defined(CONFIG_MACH_SUN6I)
  490. if (pins == SUNXI_GPIO_A) {
  491. /* SDC3: PA9-PA14 */
  492. for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
  493. sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
  494. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  495. sunxi_gpio_set_drv(pin, 2);
  496. }
  497. } else {
  498. /* SDC3: PC6-PC15, PC24 */
  499. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  500. sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
  501. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  502. sunxi_gpio_set_drv(pin, 2);
  503. }
  504. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
  505. sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  506. sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  507. }
  508. #endif
  509. break;
  510. default:
  511. printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
  512. break;
  513. }
  514. }
  515. int board_mmc_init(bd_t *bis)
  516. {
  517. __maybe_unused struct mmc *mmc0, *mmc1;
  518. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
  519. mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
  520. if (!mmc0)
  521. return -1;
  522. #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
  523. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
  524. mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
  525. if (!mmc1)
  526. return -1;
  527. #endif
  528. return 0;
  529. }
  530. #endif
  531. #ifdef CONFIG_SPL_BUILD
  532. static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
  533. {
  534. struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
  535. if (spl == INVALID_SPL_HEADER)
  536. return;
  537. /* Promote the header version for U-Boot proper, if needed. */
  538. if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
  539. spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
  540. spl->dram_size = dram_size >> 20;
  541. }
  542. void sunxi_board_init(void)
  543. {
  544. int power_failed = 0;
  545. #ifdef CONFIG_SY8106A_POWER
  546. power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
  547. #endif
  548. #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
  549. defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  550. defined CONFIG_AXP818_POWER
  551. power_failed = axp_init();
  552. #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  553. defined CONFIG_AXP818_POWER
  554. power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
  555. #endif
  556. power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
  557. power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
  558. #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
  559. power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
  560. #endif
  561. #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  562. defined CONFIG_AXP818_POWER
  563. power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
  564. #endif
  565. #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  566. defined CONFIG_AXP818_POWER
  567. power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
  568. #endif
  569. power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
  570. #if !defined(CONFIG_AXP152_POWER)
  571. power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
  572. #endif
  573. #ifdef CONFIG_AXP209_POWER
  574. power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
  575. #endif
  576. #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
  577. defined(CONFIG_AXP818_POWER)
  578. power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
  579. power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
  580. #if !defined CONFIG_AXP809_POWER
  581. power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
  582. power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
  583. #endif
  584. power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
  585. power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
  586. power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
  587. #endif
  588. #ifdef CONFIG_AXP818_POWER
  589. power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
  590. power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
  591. power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
  592. #endif
  593. #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
  594. power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
  595. #endif
  596. #endif
  597. printf("DRAM:");
  598. gd->ram_size = sunxi_dram_init();
  599. printf(" %d MiB\n", (int)(gd->ram_size >> 20));
  600. if (!gd->ram_size)
  601. hang();
  602. sunxi_spl_store_dram_size(gd->ram_size);
  603. /*
  604. * Only clock up the CPU to full speed if we are reasonably
  605. * assured it's being powered with suitable core voltage
  606. */
  607. if (!power_failed)
  608. clock_set_pll1(CONFIG_SYS_CLK_FREQ);
  609. else
  610. printf("Failed to set core voltage! Can't set CPU frequency\n");
  611. }
  612. #endif
  613. #ifdef CONFIG_USB_GADGET
  614. int g_dnl_board_usb_cable_connected(void)
  615. {
  616. struct udevice *dev;
  617. struct phy phy;
  618. int ret;
  619. ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
  620. if (ret) {
  621. pr_err("%s: Cannot find USB device\n", __func__);
  622. return ret;
  623. }
  624. ret = generic_phy_get_by_name(dev, "usb", &phy);
  625. if (ret) {
  626. pr_err("failed to get %s USB PHY\n", dev->name);
  627. return ret;
  628. }
  629. ret = generic_phy_init(&phy);
  630. if (ret) {
  631. pr_err("failed to init %s USB PHY\n", dev->name);
  632. return ret;
  633. }
  634. ret = sun4i_usb_phy_vbus_detect(&phy);
  635. if (ret == 1) {
  636. pr_err("A charger is plugged into the OTG\n");
  637. return -ENODEV;
  638. }
  639. return ret;
  640. }
  641. #endif
  642. #ifdef CONFIG_SERIAL_TAG
  643. void get_board_serial(struct tag_serialnr *serialnr)
  644. {
  645. char *serial_string;
  646. unsigned long long serial;
  647. serial_string = env_get("serial#");
  648. if (serial_string) {
  649. serial = simple_strtoull(serial_string, NULL, 16);
  650. serialnr->high = (unsigned int) (serial >> 32);
  651. serialnr->low = (unsigned int) (serial & 0xffffffff);
  652. } else {
  653. serialnr->high = 0;
  654. serialnr->low = 0;
  655. }
  656. }
  657. #endif
  658. /*
  659. * Check the SPL header for the "sunxi" variant. If found: parse values
  660. * that might have been passed by the loader ("fel" utility), and update
  661. * the environment accordingly.
  662. */
  663. static void parse_spl_header(const uint32_t spl_addr)
  664. {
  665. struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
  666. if (spl == INVALID_SPL_HEADER)
  667. return;
  668. if (!spl->fel_script_address)
  669. return;
  670. if (spl->fel_uEnv_length != 0) {
  671. /*
  672. * data is expected in uEnv.txt compatible format, so "env
  673. * import -t" the string(s) at fel_script_address right away.
  674. */
  675. himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
  676. spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
  677. return;
  678. }
  679. /* otherwise assume .scr format (mkimage-type script) */
  680. env_set_hex("fel_scriptaddr", spl->fel_script_address);
  681. }
  682. /*
  683. * Note this function gets called multiple times.
  684. * It must not make any changes to env variables which already exist.
  685. */
  686. static void setup_environment(const void *fdt)
  687. {
  688. char serial_string[17] = { 0 };
  689. unsigned int sid[4];
  690. uint8_t mac_addr[6];
  691. char ethaddr[16];
  692. int i, ret;
  693. ret = sunxi_get_sid(sid);
  694. if (ret == 0 && sid[0] != 0) {
  695. /*
  696. * The single words 1 - 3 of the SID have quite a few bits
  697. * which are the same on many models, so we take a crc32
  698. * of all 3 words, to get a more unique value.
  699. *
  700. * Note we only do this on newer SoCs as we cannot change
  701. * the algorithm on older SoCs since those have been using
  702. * fixed mac-addresses based on only using word 3 for a
  703. * long time and changing a fixed mac-address with an
  704. * u-boot update is not good.
  705. */
  706. #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
  707. !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
  708. !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
  709. sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
  710. #endif
  711. /* Ensure the NIC specific bytes of the mac are not all 0 */
  712. if ((sid[3] & 0xffffff) == 0)
  713. sid[3] |= 0x800000;
  714. for (i = 0; i < 4; i++) {
  715. sprintf(ethaddr, "ethernet%d", i);
  716. if (!fdt_get_alias(fdt, ethaddr))
  717. continue;
  718. if (i == 0)
  719. strcpy(ethaddr, "ethaddr");
  720. else
  721. sprintf(ethaddr, "eth%daddr", i);
  722. if (env_get(ethaddr))
  723. continue;
  724. /* Non OUI / registered MAC address */
  725. mac_addr[0] = (i << 4) | 0x02;
  726. mac_addr[1] = (sid[0] >> 0) & 0xff;
  727. mac_addr[2] = (sid[3] >> 24) & 0xff;
  728. mac_addr[3] = (sid[3] >> 16) & 0xff;
  729. mac_addr[4] = (sid[3] >> 8) & 0xff;
  730. mac_addr[5] = (sid[3] >> 0) & 0xff;
  731. eth_env_set_enetaddr(ethaddr, mac_addr);
  732. }
  733. if (!env_get("serial#")) {
  734. snprintf(serial_string, sizeof(serial_string),
  735. "%08x%08x", sid[0], sid[3]);
  736. env_set("serial#", serial_string);
  737. }
  738. }
  739. }
  740. int misc_init_r(void)
  741. {
  742. uint boot;
  743. env_set("fel_booted", NULL);
  744. env_set("fel_scriptaddr", NULL);
  745. env_set("mmc_bootdev", NULL);
  746. boot = sunxi_get_boot_device();
  747. /* determine if we are running in FEL mode */
  748. if (boot == BOOT_DEVICE_BOARD) {
  749. env_set("fel_booted", "1");
  750. parse_spl_header(SPL_ADDR);
  751. /* or if we booted from MMC, and which one */
  752. } else if (boot == BOOT_DEVICE_MMC1) {
  753. env_set("mmc_bootdev", "0");
  754. } else if (boot == BOOT_DEVICE_MMC2) {
  755. env_set("mmc_bootdev", "1");
  756. }
  757. setup_environment(gd->fdt_blob);
  758. #ifdef CONFIG_USB_ETHER
  759. usb_ether_init();
  760. #endif
  761. return 0;
  762. }
  763. int ft_board_setup(void *blob, bd_t *bd)
  764. {
  765. int __maybe_unused r;
  766. /*
  767. * Call setup_environment again in case the boot fdt has
  768. * ethernet aliases the u-boot copy does not have.
  769. */
  770. setup_environment(blob);
  771. #ifdef CONFIG_VIDEO_DT_SIMPLEFB
  772. r = sunxi_simplefb_setup(blob);
  773. if (r)
  774. return r;
  775. #endif
  776. return 0;
  777. }
  778. #ifdef CONFIG_SPL_LOAD_FIT
  779. int board_fit_config_name_match(const char *name)
  780. {
  781. struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
  782. const char *cmp_str = (const char *)spl;
  783. /* Check if there is a DT name stored in the SPL header and use that. */
  784. if (spl != INVALID_SPL_HEADER && spl->dt_name_offset) {
  785. cmp_str += spl->dt_name_offset;
  786. } else {
  787. #ifdef CONFIG_DEFAULT_DEVICE_TREE
  788. cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
  789. #else
  790. return 0;
  791. #endif
  792. };
  793. #ifdef CONFIG_PINE64_DT_SELECTION
  794. /* Differentiate the two Pine64 board DTs by their DRAM size. */
  795. if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
  796. if ((gd->ram_size > 512 * 1024 * 1024))
  797. return !strstr(name, "plus");
  798. else
  799. return !!strstr(name, "plus");
  800. } else {
  801. return strcmp(name, cmp_str);
  802. }
  803. #endif
  804. return strcmp(name, cmp_str);
  805. }
  806. #endif