controlcenterd.c 9.6 KB

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  1. /*
  2. * (C) Copyright 2013
  3. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <command.h>
  25. #include <env.h>
  26. #include <pci.h>
  27. #include <asm/processor.h>
  28. #include <asm/mmu.h>
  29. #include <asm/cache.h>
  30. #include <asm/immap_85xx.h>
  31. #include <asm/fsl_pci.h>
  32. #include <fsl_ddr_sdram.h>
  33. #include <asm/fsl_serdes.h>
  34. #include <asm/io.h>
  35. #include <linux/libfdt.h>
  36. #include <fdt_support.h>
  37. #include <fsl_mdio.h>
  38. #include <tsec.h>
  39. #include <asm/fsl_law.h>
  40. #include <netdev.h>
  41. #include <i2c.h>
  42. #include <pca9698.h>
  43. #include <watchdog.h>
  44. #include "../common/dp501.h"
  45. #include "controlcenterd-id.h"
  46. enum {
  47. HWVER_100 = 0,
  48. HWVER_110 = 1,
  49. HWVER_120 = 2,
  50. };
  51. struct ihs_fpga {
  52. u32 reflection_low; /* 0x0000 */
  53. u32 versions; /* 0x0004 */
  54. u32 fpga_version; /* 0x0008 */
  55. u32 fpga_features; /* 0x000c */
  56. u32 reserved[4]; /* 0x0010 */
  57. u32 control; /* 0x0020 */
  58. };
  59. #ifndef CONFIG_TRAILBLAZER
  60. static struct pci_device_id hydra_supported[] = {
  61. { 0x6d5e, 0xcdc0 },
  62. {}
  63. };
  64. static void hydra_initialize(void);
  65. #endif
  66. int board_early_init_f(void)
  67. {
  68. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  69. ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
  70. /* Reset eLBC_DIU and SPI_eLBC in case we are booting from SD */
  71. clrsetbits_be32(&gur->pmuxcr, 0x00600000, 0x80000000);
  72. /* Set pmuxcr to allow both i2c1 and i2c2 */
  73. setbits_be32(&gur->pmuxcr, 0x00001000);
  74. /* Set pmuxcr to enable GPIO 3_11-3_13 */
  75. setbits_be32(&gur->pmuxcr, 0x00000010);
  76. /* Set pmuxcr to enable GPIO 2_31,3_9+10 */
  77. setbits_be32(&gur->pmuxcr, 0x00000020);
  78. /* Set pmuxcr to enable GPIO 2_28-2_30 */
  79. setbits_be32(&gur->pmuxcr, 0x000000c0);
  80. /* Set pmuxcr to enable GPIO 3_20-3_22 */
  81. setbits_be32(&gur->pmuxcr2, 0x03000000);
  82. /* Set pmuxcr to enable IRQ0-2 */
  83. clrbits_be32(&gur->pmuxcr, 0x00000300);
  84. /* Set pmuxcr to disable IRQ3-11 */
  85. setbits_be32(&gur->pmuxcr, 0x000000F0);
  86. /* Read back the register to synchronize the write. */
  87. in_be32(&gur->pmuxcr);
  88. /* Set the pin muxing to enable ETSEC2. */
  89. clrbits_be32(&gur->pmuxcr2, 0x001F8000);
  90. #ifdef CONFIG_TRAILBLAZER
  91. /*
  92. * GPIO3_10 SPERRTRIGGER
  93. */
  94. setbits_be32(&pgpio->gpdir, 0x00200000);
  95. clrbits_be32(&pgpio->gpdat, 0x00200000);
  96. udelay(100);
  97. setbits_be32(&pgpio->gpdat, 0x00200000);
  98. udelay(100);
  99. clrbits_be32(&pgpio->gpdat, 0x00200000);
  100. #endif
  101. /*
  102. * GPIO3_11 CPU-TO-FPGA-RESET#
  103. */
  104. setbits_be32(&pgpio->gpdir, 0x00100000);
  105. clrbits_be32(&pgpio->gpdat, 0x00100000);
  106. /*
  107. * GPIO3_21 CPU-STATUS-WATCHDOG-TRIGGER#
  108. */
  109. setbits_be32(&pgpio->gpdir, 0x00000400);
  110. return 0;
  111. }
  112. int checkboard(void)
  113. {
  114. printf("Board: ControlCenter DIGITAL\n");
  115. return 0;
  116. }
  117. int misc_init_r(void)
  118. {
  119. return 0;
  120. }
  121. /*
  122. * A list of PCI and SATA slots
  123. */
  124. enum slot_id {
  125. SLOT_PCIE1 = 1,
  126. SLOT_PCIE2,
  127. SLOT_PCIE3,
  128. SLOT_PCIE4,
  129. SLOT_PCIE5,
  130. SLOT_SATA1,
  131. SLOT_SATA2
  132. };
  133. /*
  134. * This array maps the slot identifiers to their names on the P1022DS board.
  135. */
  136. static const char * const slot_names[] = {
  137. [SLOT_PCIE1] = "Slot 1",
  138. [SLOT_PCIE2] = "Slot 2",
  139. [SLOT_PCIE3] = "Slot 3",
  140. [SLOT_PCIE4] = "Slot 4",
  141. [SLOT_PCIE5] = "Mini-PCIe",
  142. [SLOT_SATA1] = "SATA 1",
  143. [SLOT_SATA2] = "SATA 2",
  144. };
  145. /*
  146. * This array maps a given SERDES configuration and SERDES device to the PCI or
  147. * SATA slot that it connects to. This mapping is hard-coded in the FPGA.
  148. */
  149. static u8 serdes_dev_slot[][SATA2 + 1] = {
  150. [0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
  151. [0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  152. [0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
  153. [PCIE2] = SLOT_PCIE5 },
  154. [0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
  155. [PCIE2] = SLOT_PCIE3,
  156. [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  157. [0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
  158. [PCIE2] = SLOT_PCIE3 },
  159. [0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
  160. [PCIE2] = SLOT_PCIE3,
  161. [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  162. [0x1c] = { [PCIE1] = SLOT_PCIE1,
  163. [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
  164. [0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
  165. [0x1f] = { [PCIE1] = SLOT_PCIE1 },
  166. };
  167. /*
  168. * Returns the name of the slot to which the PCIe or SATA controller is
  169. * connected
  170. */
  171. const char *board_serdes_name(enum srds_prtcl device)
  172. {
  173. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  174. u32 pordevsr = in_be32(&gur->pordevsr);
  175. unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
  176. MPC85xx_PORDEVSR_IO_SEL_SHIFT;
  177. enum slot_id slot = serdes_dev_slot[srds_cfg][device];
  178. const char *name = slot_names[slot];
  179. if (name)
  180. return name;
  181. else
  182. return "Nothing";
  183. }
  184. void hw_watchdog_reset(void)
  185. {
  186. ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
  187. clrbits_be32(&pgpio->gpdat, 0x00000400);
  188. setbits_be32(&pgpio->gpdat, 0x00000400);
  189. }
  190. #ifdef CONFIG_TRAILBLAZER
  191. int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  192. {
  193. return run_command(env_get("bootcmd"), flag);
  194. }
  195. int board_early_init_r(void)
  196. {
  197. ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
  198. /*
  199. * GPIO3_12 PPC_SYSTEMREADY#
  200. */
  201. setbits_be32(&pgpio->gpdir, 0x00080000);
  202. setbits_be32(&pgpio->gpodr, 0x00080000);
  203. clrbits_be32(&pgpio->gpdat, 0x00080000);
  204. return ccdm_compute_self_hash();
  205. }
  206. int last_stage_init(void)
  207. {
  208. startup_ccdm_id_module();
  209. return 0;
  210. }
  211. #else
  212. void pci_init_board(void)
  213. {
  214. fsl_pcie_init_board(0);
  215. hydra_initialize();
  216. }
  217. int board_early_init_r(void)
  218. {
  219. unsigned int k = 0;
  220. ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
  221. /* wait for FPGA configuration to finish */
  222. while (!pca9698_get_value(0x22, 11) && (k++ < 30))
  223. udelay(100000);
  224. if (k > 30) {
  225. puts("FPGA configuration timed out.\n");
  226. } else {
  227. /* clear FPGA reset */
  228. udelay(1000);
  229. setbits_be32(&pgpio->gpdat, 0x00100000);
  230. }
  231. /* give time for PCIe link training */
  232. udelay(100000);
  233. /*
  234. * GPIO3_12 PPC_SYSTEMREADY#
  235. */
  236. setbits_be32(&pgpio->gpdir, 0x00080000);
  237. setbits_be32(&pgpio->gpodr, 0x00080000);
  238. clrbits_be32(&pgpio->gpdat, 0x00080000);
  239. return 0;
  240. }
  241. int last_stage_init(void)
  242. {
  243. /* Turn on Parade DP501 */
  244. pca9698_direction_output(0x22, 7, 1);
  245. udelay(500000);
  246. dp501_powerup(0x08);
  247. startup_ccdm_id_module();
  248. return 0;
  249. }
  250. /*
  251. * Initialize on-board and/or PCI Ethernet devices
  252. *
  253. * Returns:
  254. * <0, error
  255. * 0, no ethernet devices found
  256. * >0, number of ethernet devices initialized
  257. */
  258. int board_eth_init(bd_t *bis)
  259. {
  260. struct fsl_pq_mdio_info mdio_info;
  261. struct tsec_info_struct tsec_info[2];
  262. unsigned int num = 0;
  263. #ifdef CONFIG_TSEC1
  264. SET_STD_TSEC_INFO(tsec_info[num], 1);
  265. num++;
  266. #endif
  267. #ifdef CONFIG_TSEC2
  268. SET_STD_TSEC_INFO(tsec_info[num], 2);
  269. num++;
  270. #endif
  271. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  272. mdio_info.name = DEFAULT_MII_NAME;
  273. fsl_pq_mdio_init(bis, &mdio_info);
  274. return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
  275. }
  276. #ifdef CONFIG_OF_BOARD_SETUP
  277. int ft_board_setup(void *blob, bd_t *bd)
  278. {
  279. phys_addr_t base;
  280. phys_size_t size;
  281. ft_cpu_setup(blob, bd);
  282. base = env_get_bootm_low();
  283. size = env_get_bootm_size();
  284. fdt_fixup_memory(blob, (u64)base, (u64)size);
  285. #ifdef CONFIG_HAS_FSL_DR_USB
  286. fsl_fdt_fixup_dr_usb(blob, bd);
  287. #endif
  288. FT_FSL_PCI_SETUP;
  289. return 0;
  290. }
  291. #endif
  292. static void hydra_initialize(void)
  293. {
  294. unsigned int i;
  295. pci_dev_t devno;
  296. /* Find and probe all the matching PCI devices */
  297. for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) {
  298. u32 val;
  299. struct ihs_fpga *fpga;
  300. u32 versions;
  301. u32 fpga_version;
  302. u32 fpga_features;
  303. unsigned hardware_version;
  304. unsigned feature_uart_channels;
  305. unsigned feature_sb_channels;
  306. /* Try to enable I/O accesses and bus-mastering */
  307. val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  308. pci_write_config_dword(devno, PCI_COMMAND, val);
  309. /* Make sure it worked */
  310. pci_read_config_dword(devno, PCI_COMMAND, &val);
  311. if (!(val & PCI_COMMAND_MEMORY)) {
  312. puts("Can't enable I/O memory\n");
  313. continue;
  314. }
  315. if (!(val & PCI_COMMAND_MASTER)) {
  316. puts("Can't enable bus-mastering\n");
  317. continue;
  318. }
  319. /* read FPGA details */
  320. fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
  321. PCI_REGION_MEM);
  322. /* disable sideband clocks */
  323. writel(1, &fpga->control);
  324. versions = readl(&fpga->versions);
  325. fpga_version = readl(&fpga->fpga_version);
  326. fpga_features = readl(&fpga->fpga_features);
  327. hardware_version = versions & 0xf;
  328. feature_uart_channels = (fpga_features >> 6) & 0x1f;
  329. feature_sb_channels = fpga_features & 0x1f;
  330. printf("FPGA%d: ", i);
  331. switch (hardware_version) {
  332. case HWVER_100:
  333. printf("HW-Ver 1.00\n");
  334. break;
  335. case HWVER_110:
  336. printf("HW-Ver 1.10\n");
  337. break;
  338. case HWVER_120:
  339. printf("HW-Ver 1.20\n");
  340. break;
  341. default:
  342. printf("HW-Ver %d(not supported)\n",
  343. hardware_version);
  344. break;
  345. }
  346. printf(" FPGA V %d.%02d, features:",
  347. fpga_version / 100, fpga_version % 100);
  348. printf(" %d uart channel(s)", feature_uart_channels);
  349. printf(" %d sideband channel(s)\n", feature_sb_channels);
  350. }
  351. }
  352. #endif