pfuze.c 3.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <errno.h>
  7. #include <power/pmic.h>
  8. #include <power/pfuze100_pmic.h>
  9. #ifndef CONFIG_DM_PMIC_PFUZE100
  10. int pfuze_mode_init(struct pmic *p, u32 mode)
  11. {
  12. unsigned char offset, i, switch_num;
  13. u32 id;
  14. int ret;
  15. pmic_reg_read(p, PFUZE100_DEVICEID, &id);
  16. id = id & 0xf;
  17. if (id == 0) {
  18. switch_num = 6;
  19. offset = PFUZE100_SW1CMODE;
  20. } else if (id == 1) {
  21. switch_num = 4;
  22. offset = PFUZE100_SW2MODE;
  23. } else {
  24. printf("Not supported, id=%d\n", id);
  25. return -EINVAL;
  26. }
  27. ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
  28. if (ret < 0) {
  29. printf("Set SW1AB mode error!\n");
  30. return ret;
  31. }
  32. for (i = 0; i < switch_num - 1; i++) {
  33. ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
  34. if (ret < 0) {
  35. printf("Set switch 0x%x mode error!\n",
  36. offset + i * SWITCH_SIZE);
  37. return ret;
  38. }
  39. }
  40. return ret;
  41. }
  42. struct pmic *pfuze_common_init(unsigned char i2cbus)
  43. {
  44. struct pmic *p;
  45. int ret;
  46. unsigned int reg;
  47. ret = power_pfuze100_init(i2cbus);
  48. if (ret)
  49. return NULL;
  50. p = pmic_get("PFUZE100");
  51. ret = pmic_probe(p);
  52. if (ret)
  53. return NULL;
  54. pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
  55. printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
  56. /* Set SW1AB stanby volage to 0.975V */
  57. pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
  58. reg &= ~SW1x_STBY_MASK;
  59. reg |= SW1x_0_975V;
  60. pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
  61. /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
  62. pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
  63. reg &= ~SW1xCONF_DVSSPEED_MASK;
  64. reg |= SW1xCONF_DVSSPEED_4US;
  65. pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
  66. /* Set SW1C standby voltage to 0.975V */
  67. pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
  68. reg &= ~SW1x_STBY_MASK;
  69. reg |= SW1x_0_975V;
  70. pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
  71. /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
  72. pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
  73. reg &= ~SW1xCONF_DVSSPEED_MASK;
  74. reg |= SW1xCONF_DVSSPEED_4US;
  75. pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
  76. return p;
  77. }
  78. #else
  79. int pfuze_mode_init(struct udevice *dev, u32 mode)
  80. {
  81. unsigned char offset, i, switch_num;
  82. u32 id;
  83. int ret;
  84. id = pmic_reg_read(dev, PFUZE100_DEVICEID);
  85. id = id & 0xf;
  86. if (id == 0) {
  87. switch_num = 6;
  88. offset = PFUZE100_SW1CMODE;
  89. } else if (id == 1) {
  90. switch_num = 4;
  91. offset = PFUZE100_SW2MODE;
  92. } else {
  93. printf("Not supported, id=%d\n", id);
  94. return -EINVAL;
  95. }
  96. ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode);
  97. if (ret < 0) {
  98. printf("Set SW1AB mode error!\n");
  99. return ret;
  100. }
  101. for (i = 0; i < switch_num - 1; i++) {
  102. ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode);
  103. if (ret < 0) {
  104. printf("Set switch 0x%x mode error!\n",
  105. offset + i * SWITCH_SIZE);
  106. return ret;
  107. }
  108. }
  109. return ret;
  110. }
  111. struct udevice *pfuze_common_init(void)
  112. {
  113. struct udevice *dev;
  114. int ret;
  115. unsigned int reg, dev_id, rev_id;
  116. ret = pmic_get("pfuze100", &dev);
  117. if (ret == -ENODEV)
  118. return NULL;
  119. dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
  120. rev_id = pmic_reg_read(dev, PFUZE100_REVID);
  121. printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
  122. /* Set SW1AB stanby volage to 0.975V */
  123. reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
  124. reg &= ~SW1x_STBY_MASK;
  125. reg |= SW1x_0_975V;
  126. pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
  127. /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
  128. reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
  129. reg &= ~SW1xCONF_DVSSPEED_MASK;
  130. reg |= SW1xCONF_DVSSPEED_4US;
  131. pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
  132. /* Set SW1C standby voltage to 0.975V */
  133. reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
  134. reg &= ~SW1x_STBY_MASK;
  135. reg |= SW1x_0_975V;
  136. pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
  137. /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
  138. reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
  139. reg &= ~SW1xCONF_DVSSPEED_MASK;
  140. reg |= SW1xCONF_DVSSPEED_4US;
  141. pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
  142. return dev;
  143. }
  144. #endif