ics307_clk.c 3.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. #include "ics307_clk.h"
  8. #if defined(CONFIG_FSL_NGPIXIS)
  9. #include "ngpixis.h"
  10. #define fpga_reg pixis
  11. #elif defined(CONFIG_FSL_QIXIS)
  12. #include "qixis.h"
  13. #define fpga_reg ((struct qixis *)QIXIS_BASE)
  14. #else
  15. #include "pixis.h"
  16. #define fpga_reg pixis
  17. #endif
  18. /* define for SYS CLK or CLK1Frequency */
  19. #define TTL 1
  20. #define CLK2 0
  21. #define CRYSTAL 0
  22. #define MAX_VDW (511 + 8)
  23. #define MAX_RDW (127 + 2)
  24. #define MIN_VDW (4 + 8)
  25. #define MIN_RDW (1 + 2)
  26. #define NUM_OD_SETTING 8
  27. /*
  28. * These defines cover the industrial temperature range part,
  29. * for commercial, change below to 400000 and 55000, respectively
  30. */
  31. #define MAX_VCO 360000
  32. #define MIN_VCO 60000
  33. /* decode S[0-2] to Output Divider (OD) */
  34. static u8 ics307_s_to_od[] = {
  35. 10, 2, 8, 4, 5, 7, 3, 6
  36. };
  37. /*
  38. * Find one solution to generate required frequency for SYSCLK
  39. * out_freq: KHz, required frequency to the SYSCLK
  40. * the result will be retuned with component RDW, VDW, OD, TTL,
  41. * CLK2 and crystal
  42. */
  43. unsigned long ics307_sysclk_calculator(unsigned long out_freq)
  44. {
  45. const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
  46. unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od;
  47. unsigned long tmp_out, diff, result = 0;
  48. int found = 0;
  49. for (odp = 0; odp < NUM_OD_SETTING; odp++) {
  50. od = ics307_s_to_od[odp];
  51. if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO)
  52. continue;
  53. for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) {
  54. /* Calculate the VDW */
  55. vdw = out_freq * 1000 * od * rdw / (input_freq * 2);
  56. if (vdw > MAX_VDW)
  57. vdw = MAX_VDW;
  58. if (vdw < MIN_VDW)
  59. continue;
  60. /* Calculate the temp out frequency */
  61. tmp_out = input_freq * 2 * vdw / (rdw * od * 1000);
  62. diff = max(out_freq, tmp_out) - min(out_freq, tmp_out);
  63. /*
  64. * calculate the percent, the precision is 1/1000
  65. * If greater than 1/1000, continue
  66. * otherwise, we think the solution is we required
  67. */
  68. if (diff * 1000 / out_freq > 1)
  69. continue;
  70. else {
  71. s_vdw = vdw;
  72. s_rdw = rdw;
  73. s_odp = odp;
  74. found = 1;
  75. break;
  76. }
  77. }
  78. }
  79. if (found)
  80. result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 |
  81. CLK2 << 19 | TTL << 21 | CRYSTAL << 22;
  82. debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8,
  83. ics307_s_to_od[s_odp]);
  84. return result;
  85. }
  86. /*
  87. * Calculate frequency being generated by ICS307-02 clock chip based upon
  88. * the control bytes being programmed into it.
  89. */
  90. static unsigned long ics307_clk_freq(u8 cw0, u8 cw1, u8 cw2)
  91. {
  92. const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
  93. unsigned long vdw = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
  94. unsigned long rdw = cw2 & 0x7F;
  95. unsigned long od = ics307_s_to_od[cw0 & 0x7];
  96. unsigned long freq;
  97. /*
  98. * CLK1 Freq = Input Frequency * 2 * (VDW + 8) / ((RDW + 2) * OD)
  99. *
  100. * cw0: C1 C0 TTL F1 F0 S2 S1 S0
  101. * cw1: V8 V7 V6 V5 V4 V3 V2 V1
  102. * cw2: V0 R6 R5 R4 R3 R2 R1 R0
  103. *
  104. * R6:R0 = Reference Divider Word (RDW)
  105. * V8:V0 = VCO Divider Word (VDW)
  106. * S2:S0 = Output Divider Select (OD)
  107. * F1:F0 = Function of CLK2 Output
  108. * TTL = duty cycle
  109. * C1:C0 = internal load capacitance for cyrstal
  110. *
  111. */
  112. freq = input_freq * 2 * (vdw + 8) / ((rdw + 2) * od);
  113. debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
  114. freq);
  115. return freq;
  116. }
  117. unsigned long get_board_sys_clk(void)
  118. {
  119. return ics307_clk_freq(
  120. in_8(&fpga_reg->sclk[0]),
  121. in_8(&fpga_reg->sclk[1]),
  122. in_8(&fpga_reg->sclk[2]));
  123. }
  124. unsigned long get_board_ddr_clk(void)
  125. {
  126. return ics307_clk_freq(
  127. in_8(&fpga_reg->dclk[0]),
  128. in_8(&fpga_reg->dclk[1]),
  129. in_8(&fpga_reg->dclk[2]));
  130. }