turris_omnia.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
  4. * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
  5. *
  6. * Derived from the code for
  7. * Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
  8. */
  9. #include <common.h>
  10. #include <env.h>
  11. #include <i2c.h>
  12. #include <miiphy.h>
  13. #include <netdev.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/cpu.h>
  16. #include <asm/arch/soc.h>
  17. #include <dm/uclass.h>
  18. #include <fdt_support.h>
  19. #include <time.h>
  20. #include <u-boot/crc.h>
  21. # include <atsha204a-i2c.h>
  22. #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
  23. #include <../serdes/a38x/high_speed_env_spec.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0"
  26. #define OMNIA_I2C_MCU_CHIP_ADDR 0x2a
  27. #define OMNIA_I2C_MCU_CHIP_LEN 1
  28. #define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54
  29. #define OMNIA_I2C_EEPROM_CHIP_LEN 2
  30. #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
  31. enum mcu_commands {
  32. CMD_GET_STATUS_WORD = 0x01,
  33. CMD_GET_RESET = 0x09,
  34. CMD_WATCHDOG_STATE = 0x0b,
  35. };
  36. enum status_word_bits {
  37. CARD_DET_STSBIT = 0x0010,
  38. MSATA_IND_STSBIT = 0x0020,
  39. };
  40. #define OMNIA_ATSHA204_OTP_VERSION 0
  41. #define OMNIA_ATSHA204_OTP_SERIAL 1
  42. #define OMNIA_ATSHA204_OTP_MAC0 3
  43. #define OMNIA_ATSHA204_OTP_MAC1 4
  44. /*
  45. * Those values and defines are taken from the Marvell U-Boot version
  46. * "u-boot-2013.01-2014_T3.0"
  47. */
  48. #define OMNIA_GPP_OUT_ENA_LOW \
  49. (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
  50. BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
  51. BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
  52. #define OMNIA_GPP_OUT_ENA_MID \
  53. (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
  54. BIT(16) | BIT(17) | BIT(18)))
  55. #define OMNIA_GPP_OUT_VAL_LOW 0x0
  56. #define OMNIA_GPP_OUT_VAL_MID 0x0
  57. #define OMNIA_GPP_POL_LOW 0x0
  58. #define OMNIA_GPP_POL_MID 0x0
  59. static struct serdes_map board_serdes_map_pex[] = {
  60. {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  61. {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  62. {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  63. {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  64. {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  65. {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  66. };
  67. static struct serdes_map board_serdes_map_sata[] = {
  68. {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  69. {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  70. {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  71. {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
  72. {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
  73. {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
  74. };
  75. static struct udevice *omnia_get_i2c_chip(const char *name, uint addr,
  76. uint offset_len)
  77. {
  78. struct udevice *bus, *dev;
  79. int ret;
  80. ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus);
  81. if (ret) {
  82. printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n",
  83. OMNIA_I2C_BUS_NAME, ret);
  84. return NULL;
  85. }
  86. ret = i2c_get_chip(bus, addr, offset_len, &dev);
  87. if (ret) {
  88. printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n",
  89. name, ret);
  90. return NULL;
  91. }
  92. return dev;
  93. }
  94. static int omnia_mcu_read(u8 cmd, void *buf, int len)
  95. {
  96. struct udevice *chip;
  97. chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
  98. OMNIA_I2C_MCU_CHIP_LEN);
  99. if (!chip)
  100. return -ENODEV;
  101. return dm_i2c_read(chip, cmd, buf, len);
  102. }
  103. #ifndef CONFIG_SPL_BUILD
  104. static int omnia_mcu_write(u8 cmd, const void *buf, int len)
  105. {
  106. struct udevice *chip;
  107. chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
  108. OMNIA_I2C_MCU_CHIP_LEN);
  109. if (!chip)
  110. return -ENODEV;
  111. return dm_i2c_write(chip, cmd, buf, len);
  112. }
  113. static bool disable_mcu_watchdog(void)
  114. {
  115. int ret;
  116. puts("Disabling MCU watchdog... ");
  117. ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
  118. if (ret) {
  119. printf("omnia_mcu_write failed: %i\n", ret);
  120. return false;
  121. }
  122. puts("disabled\n");
  123. return true;
  124. }
  125. #endif
  126. static bool omnia_detect_sata(void)
  127. {
  128. int ret;
  129. u16 stsword;
  130. puts("MiniPCIe/mSATA card detection... ");
  131. ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
  132. if (ret) {
  133. printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n",
  134. ret);
  135. return false;
  136. }
  137. if (!(stsword & CARD_DET_STSBIT)) {
  138. puts("none\n");
  139. return false;
  140. }
  141. if (stsword & MSATA_IND_STSBIT)
  142. puts("mSATA\n");
  143. else
  144. puts("MiniPCIe\n");
  145. return stsword & MSATA_IND_STSBIT ? true : false;
  146. }
  147. int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
  148. {
  149. if (omnia_detect_sata()) {
  150. *serdes_map_array = board_serdes_map_sata;
  151. *count = ARRAY_SIZE(board_serdes_map_sata);
  152. } else {
  153. *serdes_map_array = board_serdes_map_pex;
  154. *count = ARRAY_SIZE(board_serdes_map_pex);
  155. }
  156. return 0;
  157. }
  158. struct omnia_eeprom {
  159. u32 magic;
  160. u32 ramsize;
  161. char region[4];
  162. u32 crc;
  163. };
  164. static bool omnia_read_eeprom(struct omnia_eeprom *oep)
  165. {
  166. struct udevice *chip;
  167. u32 crc;
  168. int ret;
  169. chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
  170. OMNIA_I2C_EEPROM_CHIP_LEN);
  171. if (!chip)
  172. return false;
  173. ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
  174. if (ret) {
  175. printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
  176. return false;
  177. }
  178. if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
  179. printf("bad EEPROM magic number (%08x, should be %08x)\n",
  180. oep->magic, OMNIA_I2C_EEPROM_MAGIC);
  181. return false;
  182. }
  183. crc = crc32(0, (void *)oep, sizeof(*oep) - 4);
  184. if (crc != oep->crc) {
  185. printf("bad EEPROM CRC (stored %08x, computed %08x)\n",
  186. oep->crc, crc);
  187. return false;
  188. }
  189. return true;
  190. }
  191. static int omnia_get_ram_size_gb(void)
  192. {
  193. static int ram_size;
  194. struct omnia_eeprom oep;
  195. if (!ram_size) {
  196. /* Get the board config from EEPROM */
  197. if (omnia_read_eeprom(&oep)) {
  198. debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
  199. if (oep.ramsize == 0x2)
  200. ram_size = 2;
  201. else
  202. ram_size = 1;
  203. } else {
  204. /* Hardcoded fallback */
  205. puts("Memory config from EEPROM read failed!\n");
  206. puts("Falling back to default 1 GiB!\n");
  207. ram_size = 1;
  208. }
  209. }
  210. return ram_size;
  211. }
  212. /*
  213. * Define the DDR layout / topology here in the board file. This will
  214. * be used by the DDR3 init code in the SPL U-Boot version to configure
  215. * the DDR3 controller.
  216. */
  217. static struct mv_ddr_topology_map board_topology_map_1g = {
  218. DEBUG_LEVEL_ERROR,
  219. 0x1, /* active interfaces */
  220. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  221. { { { {0x1, 0, 0, 0},
  222. {0x1, 0, 0, 0},
  223. {0x1, 0, 0, 0},
  224. {0x1, 0, 0, 0},
  225. {0x1, 0, 0, 0} },
  226. SPEED_BIN_DDR_1600K, /* speed_bin */
  227. MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
  228. MV_DDR_DIE_CAP_4GBIT, /* mem_size */
  229. MV_DDR_FREQ_800, /* frequency */
  230. 0, 0, /* cas_wl cas_l */
  231. MV_DDR_TEMP_NORMAL, /* temperature */
  232. MV_DDR_TIM_2T} }, /* timing */
  233. BUS_MASK_32BIT, /* Busses mask */
  234. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  235. { {0} }, /* raw spd data */
  236. {0} /* timing parameters */
  237. };
  238. static struct mv_ddr_topology_map board_topology_map_2g = {
  239. DEBUG_LEVEL_ERROR,
  240. 0x1, /* active interfaces */
  241. /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
  242. { { { {0x1, 0, 0, 0},
  243. {0x1, 0, 0, 0},
  244. {0x1, 0, 0, 0},
  245. {0x1, 0, 0, 0},
  246. {0x1, 0, 0, 0} },
  247. SPEED_BIN_DDR_1600K, /* speed_bin */
  248. MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
  249. MV_DDR_DIE_CAP_8GBIT, /* mem_size */
  250. MV_DDR_FREQ_800, /* frequency */
  251. 0, 0, /* cas_wl cas_l */
  252. MV_DDR_TEMP_NORMAL, /* temperature */
  253. MV_DDR_TIM_2T} }, /* timing */
  254. BUS_MASK_32BIT, /* Busses mask */
  255. MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
  256. { {0} }, /* raw spd data */
  257. {0} /* timing parameters */
  258. };
  259. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
  260. {
  261. if (omnia_get_ram_size_gb() == 2)
  262. return &board_topology_map_2g;
  263. else
  264. return &board_topology_map_1g;
  265. }
  266. #ifndef CONFIG_SPL_BUILD
  267. static int set_regdomain(void)
  268. {
  269. struct omnia_eeprom oep;
  270. char rd[3] = {' ', ' ', 0};
  271. if (omnia_read_eeprom(&oep))
  272. memcpy(rd, &oep.region, 2);
  273. else
  274. puts("EEPROM regdomain read failed.\n");
  275. printf("Regdomain set to %s\n", rd);
  276. return env_set("regdomain", rd);
  277. }
  278. /*
  279. * default factory reset bootcommand on Omnia first sets all the front LEDs
  280. * to green and then tries to load the rescue image from SPI flash memory and
  281. * boot it
  282. */
  283. #define OMNIA_FACTORY_RESET_BOOTCMD \
  284. "i2c dev 2; " \
  285. "i2c mw 0x2a.1 0x3 0x1c 1; " \
  286. "i2c mw 0x2a.1 0x4 0x1c 1; " \
  287. "mw.l 0x01000000 0x00ff000c; " \
  288. "i2c write 0x01000000 0x2a.1 0x5 4 -s; " \
  289. "setenv bootargs \"earlyprintk console=ttyS0,115200" \
  290. " omniarescue=$omnia_reset\"; " \
  291. "sf probe; " \
  292. "sf read 0x1000000 0x100000 0x700000; " \
  293. "bootm 0x1000000; " \
  294. "bootz 0x1000000"
  295. static void handle_reset_button(void)
  296. {
  297. int ret;
  298. u8 reset_status;
  299. ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
  300. if (ret) {
  301. printf("omnia_mcu_read failed: %i, reset status unknown!\n",
  302. ret);
  303. return;
  304. }
  305. env_set_ulong("omnia_reset", reset_status);
  306. if (reset_status) {
  307. printf("RESET button was pressed, overwriting bootcmd!\n");
  308. env_set("bootcmd", OMNIA_FACTORY_RESET_BOOTCMD);
  309. }
  310. }
  311. #endif
  312. int board_early_init_f(void)
  313. {
  314. /* Configure MPP */
  315. writel(0x11111111, MVEBU_MPP_BASE + 0x00);
  316. writel(0x11111111, MVEBU_MPP_BASE + 0x04);
  317. writel(0x11244011, MVEBU_MPP_BASE + 0x08);
  318. writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
  319. writel(0x22200002, MVEBU_MPP_BASE + 0x10);
  320. writel(0x30042022, MVEBU_MPP_BASE + 0x14);
  321. writel(0x55550555, MVEBU_MPP_BASE + 0x18);
  322. writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
  323. /* Set GPP Out value */
  324. writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
  325. writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
  326. /* Set GPP Polarity */
  327. writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
  328. writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
  329. /* Set GPP Out Enable */
  330. writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
  331. writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
  332. return 0;
  333. }
  334. int board_init(void)
  335. {
  336. /* address of boot parameters */
  337. gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  338. #ifndef CONFIG_SPL_BUILD
  339. disable_mcu_watchdog();
  340. #endif
  341. return 0;
  342. }
  343. int board_late_init(void)
  344. {
  345. #ifndef CONFIG_SPL_BUILD
  346. set_regdomain();
  347. handle_reset_button();
  348. #endif
  349. pci_init();
  350. return 0;
  351. }
  352. static struct udevice *get_atsha204a_dev(void)
  353. {
  354. static struct udevice *dev;
  355. if (dev)
  356. return dev;
  357. if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
  358. puts("Cannot find ATSHA204A on I2C bus!\n");
  359. dev = NULL;
  360. }
  361. return dev;
  362. }
  363. int checkboard(void)
  364. {
  365. u32 version_num, serial_num;
  366. int err = 1;
  367. struct udevice *dev = get_atsha204a_dev();
  368. if (dev) {
  369. err = atsha204a_wakeup(dev);
  370. if (err)
  371. goto out;
  372. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  373. OMNIA_ATSHA204_OTP_VERSION,
  374. (u8 *)&version_num);
  375. if (err)
  376. goto out;
  377. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  378. OMNIA_ATSHA204_OTP_SERIAL,
  379. (u8 *)&serial_num);
  380. if (err)
  381. goto out;
  382. atsha204a_sleep(dev);
  383. }
  384. out:
  385. printf("Turris Omnia:\n");
  386. printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
  387. if (err)
  388. printf(" Serial Number: unknown\n");
  389. else
  390. printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num),
  391. be32_to_cpu(serial_num));
  392. return 0;
  393. }
  394. static void increment_mac(u8 *mac)
  395. {
  396. int i;
  397. for (i = 5; i >= 3; i--) {
  398. mac[i] += 1;
  399. if (mac[i])
  400. break;
  401. }
  402. }
  403. int misc_init_r(void)
  404. {
  405. int err;
  406. struct udevice *dev = get_atsha204a_dev();
  407. u8 mac0[4], mac1[4], mac[6];
  408. if (!dev)
  409. goto out;
  410. err = atsha204a_wakeup(dev);
  411. if (err)
  412. goto out;
  413. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  414. OMNIA_ATSHA204_OTP_MAC0, mac0);
  415. if (err)
  416. goto out;
  417. err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
  418. OMNIA_ATSHA204_OTP_MAC1, mac1);
  419. if (err)
  420. goto out;
  421. atsha204a_sleep(dev);
  422. mac[0] = mac0[1];
  423. mac[1] = mac0[2];
  424. mac[2] = mac0[3];
  425. mac[3] = mac1[1];
  426. mac[4] = mac1[2];
  427. mac[5] = mac1[3];
  428. if (is_valid_ethaddr(mac))
  429. eth_env_set_enetaddr("eth1addr", mac);
  430. increment_mac(mac);
  431. if (is_valid_ethaddr(mac))
  432. eth_env_set_enetaddr("eth2addr", mac);
  433. increment_mac(mac);
  434. if (is_valid_ethaddr(mac))
  435. eth_env_set_enetaddr("ethaddr", mac);
  436. out:
  437. return 0;
  438. }