board-gx.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
  4. * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #include <common.h>
  7. #include <asm/arch/boot.h>
  8. #include <asm/arch/eth.h>
  9. #include <asm/arch/gx.h>
  10. #include <asm/arch/mem.h>
  11. #include <asm/arch/meson-vpu.h>
  12. #include <asm/io.h>
  13. #include <asm/armv8/mmu.h>
  14. #include <linux/sizes.h>
  15. #include <phy.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. int meson_get_boot_device(void)
  18. {
  19. return readl(GX_AO_SEC_GP_CFG0) & GX_AO_BOOT_DEVICE;
  20. }
  21. /* Configure the reserved memory zones exported by the secure registers
  22. * into EFI and DTB reserved memory entries.
  23. */
  24. void meson_init_reserved_memory(void *fdt)
  25. {
  26. u64 bl31_size, bl31_start;
  27. u64 bl32_size, bl32_start;
  28. u32 reg;
  29. /*
  30. * Get ARM Trusted Firmware reserved memory zones in :
  31. * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
  32. * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
  33. * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
  34. */
  35. reg = readl(GX_AO_SEC_GP_CFG3);
  36. bl31_size = ((reg & GX_AO_BL31_RSVMEM_SIZE_MASK)
  37. >> GX_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
  38. bl32_size = (reg & GX_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
  39. bl31_start = readl(GX_AO_SEC_GP_CFG5);
  40. bl32_start = readl(GX_AO_SEC_GP_CFG4);
  41. /*
  42. * Early Meson GX Firmware revisions did not provide the reserved
  43. * memory zones in the registers, keep fixed memory zone handling.
  44. */
  45. if (IS_ENABLED(CONFIG_MESON_GX) &&
  46. !reg && !bl31_start && !bl32_start) {
  47. bl31_start = 0x10000000;
  48. bl31_size = 0x200000;
  49. }
  50. /* Add first 16MiB reserved zone */
  51. meson_board_add_reserved_memory(fdt, 0, GX_FIRMWARE_MEM_SIZE);
  52. /* Add BL31 reserved zone */
  53. if (bl31_start && bl31_size)
  54. meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
  55. /* Add BL32 reserved zone */
  56. if (bl32_start && bl32_size)
  57. meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
  58. #if defined(CONFIG_VIDEO_MESON)
  59. meson_vpu_rsv_fb(fdt);
  60. #endif
  61. }
  62. phys_size_t get_effective_memsize(void)
  63. {
  64. /* Size is reported in MiB, convert it in bytes */
  65. return ((readl(GX_AO_SEC_GP_CFG0) & GX_AO_MEM_SIZE_MASK)
  66. >> GX_AO_MEM_SIZE_SHIFT) * SZ_1M;
  67. }
  68. static struct mm_region gx_mem_map[] = {
  69. {
  70. .virt = 0x0UL,
  71. .phys = 0x0UL,
  72. .size = 0xc0000000UL,
  73. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  74. PTE_BLOCK_INNER_SHARE
  75. }, {
  76. .virt = 0xc0000000UL,
  77. .phys = 0xc0000000UL,
  78. .size = 0x30000000UL,
  79. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  80. PTE_BLOCK_NON_SHARE |
  81. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  82. }, {
  83. /* List terminator */
  84. 0,
  85. }
  86. };
  87. struct mm_region *mem_map = gx_mem_map;
  88. /* Configure the Ethernet MAC with the requested interface mode
  89. * with some optional flags.
  90. */
  91. void meson_eth_init(phy_interface_t mode, unsigned int flags)
  92. {
  93. switch (mode) {
  94. case PHY_INTERFACE_MODE_RGMII:
  95. case PHY_INTERFACE_MODE_RGMII_ID:
  96. case PHY_INTERFACE_MODE_RGMII_RXID:
  97. case PHY_INTERFACE_MODE_RGMII_TXID:
  98. /* Set RGMII mode */
  99. setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
  100. GX_ETH_REG_0_TX_PHASE(1) |
  101. GX_ETH_REG_0_TX_RATIO(4) |
  102. GX_ETH_REG_0_PHY_CLK_EN |
  103. GX_ETH_REG_0_CLK_EN);
  104. /* Reset to external PHY */
  105. if(!IS_ENABLED(CONFIG_MESON_GXBB))
  106. writel(0x2009087f, GX_ETH_REG_3);
  107. break;
  108. case PHY_INTERFACE_MODE_RMII:
  109. /* Set RMII mode */
  110. out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
  111. GX_ETH_REG_0_CLK_EN);
  112. /* Use GXL RMII Internal PHY (also on GXM) */
  113. if (!IS_ENABLED(CONFIG_MESON_GXBB)) {
  114. if ((flags & MESON_USE_INTERNAL_RMII_PHY)) {
  115. writel(0x10110181, GX_ETH_REG_2);
  116. writel(0xe40908ff, GX_ETH_REG_3);
  117. } else
  118. writel(0x2009087f, GX_ETH_REG_3);
  119. }
  120. break;
  121. default:
  122. printf("Invalid Ethernet interface mode\n");
  123. return;
  124. }
  125. /* Enable power gate */
  126. clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
  127. }