board-g12a.c 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
  4. * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #include <common.h>
  7. #include <asm/arch/boot.h>
  8. #include <asm/arch/eth.h>
  9. #include <asm/arch/g12a.h>
  10. #include <asm/arch/mem.h>
  11. #include <asm/arch/meson-vpu.h>
  12. #include <asm/io.h>
  13. #include <asm/armv8/mmu.h>
  14. #include <linux/sizes.h>
  15. #include <usb.h>
  16. #include <linux/usb/otg.h>
  17. #include <asm/arch/usb.h>
  18. #include <usb/dwc2_udc.h>
  19. #include <phy.h>
  20. #include <clk.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. int meson_get_boot_device(void)
  23. {
  24. return readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_BOOT_DEVICE;
  25. }
  26. /* Configure the reserved memory zones exported by the secure registers
  27. * into EFI and DTB reserved memory entries.
  28. */
  29. void meson_init_reserved_memory(void *fdt)
  30. {
  31. u64 bl31_size, bl31_start;
  32. u64 bl32_size, bl32_start;
  33. u32 reg;
  34. /*
  35. * Get ARM Trusted Firmware reserved memory zones in :
  36. * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
  37. * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
  38. * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
  39. */
  40. reg = readl(G12A_AO_SEC_GP_CFG3);
  41. bl31_size = ((reg & G12A_AO_BL31_RSVMEM_SIZE_MASK)
  42. >> G12A_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
  43. bl32_size = (reg & G12A_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
  44. bl31_start = readl(G12A_AO_SEC_GP_CFG5);
  45. bl32_start = readl(G12A_AO_SEC_GP_CFG4);
  46. /* Add BL31 reserved zone */
  47. if (bl31_start && bl31_size)
  48. meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
  49. /* Add BL32 reserved zone */
  50. if (bl32_start && bl32_size)
  51. meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
  52. #if defined(CONFIG_VIDEO_MESON)
  53. meson_vpu_rsv_fb(fdt);
  54. #endif
  55. }
  56. phys_size_t get_effective_memsize(void)
  57. {
  58. /* Size is reported in MiB, convert it in bytes */
  59. return min(((readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_MEM_SIZE_MASK)
  60. >> G12A_AO_MEM_SIZE_SHIFT) * SZ_1M, 0xf5000000);
  61. }
  62. static struct mm_region g12a_mem_map[] = {
  63. {
  64. .virt = 0x0UL,
  65. .phys = 0x0UL,
  66. .size = 0xf5000000UL,
  67. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  68. PTE_BLOCK_INNER_SHARE
  69. }, {
  70. .virt = 0xf5000000UL,
  71. .phys = 0xf5000000UL,
  72. .size = 0x0b000000UL,
  73. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  74. PTE_BLOCK_NON_SHARE |
  75. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  76. }, {
  77. /* List terminator */
  78. 0,
  79. }
  80. };
  81. struct mm_region *mem_map = g12a_mem_map;
  82. static void g12a_enable_external_mdio(void)
  83. {
  84. writel(0x0, ETH_PHY_CNTL2);
  85. }
  86. static void g12a_enable_internal_mdio(void)
  87. {
  88. /* Fire up the PHY PLL */
  89. writel(0x29c0040a, ETH_PLL_CNTL0);
  90. writel(0x927e0000, ETH_PLL_CNTL1);
  91. writel(0xac5f49e5, ETH_PLL_CNTL2);
  92. writel(0x00000000, ETH_PLL_CNTL3);
  93. writel(0x00000000, ETH_PLL_CNTL4);
  94. writel(0x20200000, ETH_PLL_CNTL5);
  95. writel(0x0000c002, ETH_PLL_CNTL6);
  96. writel(0x00000023, ETH_PLL_CNTL7);
  97. writel(0x39c0040a, ETH_PLL_CNTL0);
  98. writel(0x19c0040a, ETH_PLL_CNTL0);
  99. /* Select the internal MDIO */
  100. writel(0x33000180, ETH_PHY_CNTL0);
  101. writel(0x00074043, ETH_PHY_CNTL1);
  102. writel(0x00000260, ETH_PHY_CNTL2);
  103. }
  104. /* Configure the Ethernet MAC with the requested interface mode
  105. * with some optional flags.
  106. */
  107. void meson_eth_init(phy_interface_t mode, unsigned int flags)
  108. {
  109. switch (mode) {
  110. case PHY_INTERFACE_MODE_RGMII:
  111. case PHY_INTERFACE_MODE_RGMII_ID:
  112. case PHY_INTERFACE_MODE_RGMII_RXID:
  113. case PHY_INTERFACE_MODE_RGMII_TXID:
  114. /* Set RGMII mode */
  115. setbits_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RGMII |
  116. G12A_ETH_REG_0_TX_PHASE(1) |
  117. G12A_ETH_REG_0_TX_RATIO(4) |
  118. G12A_ETH_REG_0_PHY_CLK_EN |
  119. G12A_ETH_REG_0_CLK_EN);
  120. g12a_enable_external_mdio();
  121. break;
  122. case PHY_INTERFACE_MODE_RMII:
  123. /* Set RMII mode */
  124. out_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RMII |
  125. G12A_ETH_REG_0_INVERT_RMII_CLK |
  126. G12A_ETH_REG_0_CLK_EN);
  127. /* Use G12A RMII Internal PHY */
  128. if (flags & MESON_USE_INTERNAL_RMII_PHY)
  129. g12a_enable_internal_mdio();
  130. else
  131. g12a_enable_external_mdio();
  132. break;
  133. default:
  134. printf("Invalid Ethernet interface mode\n");
  135. return;
  136. }
  137. /* Enable power gate */
  138. clrbits_le32(G12A_MEM_PD_REG_0, G12A_MEM_PD_REG_0_ETH_MASK);
  139. }
  140. #if CONFIG_IS_ENABLED(USB_DWC3_MESON_G12A) && \
  141. CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
  142. static struct dwc2_plat_otg_data meson_g12a_dwc2_data;
  143. int board_usb_init(int index, enum usb_init_type init)
  144. {
  145. struct fdtdec_phandle_args args;
  146. const void *blob = gd->fdt_blob;
  147. int node, dwc2_node;
  148. struct udevice *dev, *clk_dev;
  149. struct clk clk;
  150. int ret;
  151. /* find the usb glue node */
  152. node = fdt_node_offset_by_compatible(blob, -1,
  153. "amlogic,meson-g12a-usb-ctrl");
  154. if (node < 0) {
  155. debug("Not found usb-control node\n");
  156. return -ENODEV;
  157. }
  158. if (!fdtdec_get_is_enabled(blob, node)) {
  159. debug("usb is disabled in the device tree\n");
  160. return -ENODEV;
  161. }
  162. ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
  163. if (ret) {
  164. debug("Not found usb-control device\n");
  165. return ret;
  166. }
  167. /* find the dwc2 node */
  168. dwc2_node = fdt_node_offset_by_compatible(blob, node,
  169. "amlogic,meson-g12a-usb");
  170. if (dwc2_node < 0) {
  171. debug("Not found dwc2 node\n");
  172. return -ENODEV;
  173. }
  174. if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
  175. debug("dwc2 is disabled in the device tree\n");
  176. return -ENODEV;
  177. }
  178. meson_g12a_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
  179. if (meson_g12a_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
  180. debug("usbotg: can't get base address\n");
  181. return -ENODATA;
  182. }
  183. /* Enable clock */
  184. ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
  185. "#clock-cells", 0, 0, &args);
  186. if (ret) {
  187. debug("usbotg has no clocks defined in the device tree\n");
  188. return ret;
  189. }
  190. ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
  191. if (ret)
  192. return ret;
  193. if (args.args_count != 1) {
  194. debug("Can't find clock ID in the device tree\n");
  195. return -ENODATA;
  196. }
  197. clk.dev = clk_dev;
  198. clk.id = args.args[0];
  199. ret = clk_enable(&clk);
  200. if (ret) {
  201. debug("Failed to enable usbotg clock\n");
  202. return ret;
  203. }
  204. meson_g12a_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  205. "g-rx-fifo-size", 0);
  206. meson_g12a_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  207. "g-np-tx-fifo-size", 0);
  208. meson_g12a_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
  209. "g-tx-fifo-size", 0);
  210. /* Switch to peripheral mode */
  211. ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_PERIPHERAL);
  212. if (ret)
  213. return ret;
  214. return dwc2_udc_probe(&meson_g12a_dwc2_data);
  215. }
  216. int board_usb_cleanup(int index, enum usb_init_type init)
  217. {
  218. const void *blob = gd->fdt_blob;
  219. struct udevice *dev;
  220. int node;
  221. int ret;
  222. /* find the usb glue node */
  223. node = fdt_node_offset_by_compatible(blob, -1,
  224. "amlogic,meson-g12a-usb-ctrl");
  225. if (node < 0)
  226. return -ENODEV;
  227. if (!fdtdec_get_is_enabled(blob, node))
  228. return -ENODEV;
  229. ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
  230. if (ret)
  231. return ret;
  232. /* Switch to OTG mode */
  233. ret = dwc3_meson_g12a_force_mode(dev, USB_DR_MODE_HOST);
  234. if (ret)
  235. return ret;
  236. return 0;
  237. }
  238. #endif