board-axg.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
  4. * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #include <common.h>
  7. #include <asm/arch/boot.h>
  8. #include <asm/arch/eth.h>
  9. #include <asm/arch/axg.h>
  10. #include <asm/arch/mem.h>
  11. #include <asm/io.h>
  12. #include <asm/armv8/mmu.h>
  13. #include <linux/sizes.h>
  14. #include <phy.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. int meson_get_boot_device(void)
  17. {
  18. return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE;
  19. }
  20. /* Configure the reserved memory zones exported by the secure registers
  21. * into EFI and DTB reserved memory entries.
  22. */
  23. void meson_init_reserved_memory(void *fdt)
  24. {
  25. u64 bl31_size, bl31_start;
  26. u64 bl32_size, bl32_start;
  27. u32 reg;
  28. /*
  29. * Get ARM Trusted Firmware reserved memory zones in :
  30. * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
  31. * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
  32. * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
  33. */
  34. reg = readl(AXG_AO_SEC_GP_CFG3);
  35. bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK)
  36. >> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
  37. bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
  38. bl31_start = readl(AXG_AO_SEC_GP_CFG5);
  39. bl32_start = readl(AXG_AO_SEC_GP_CFG4);
  40. /* Add BL31 reserved zone */
  41. if (bl31_start && bl31_size)
  42. meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
  43. /* Add BL32 reserved zone */
  44. if (bl32_start && bl32_size)
  45. meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
  46. }
  47. phys_size_t get_effective_memsize(void)
  48. {
  49. /* Size is reported in MiB, convert it in bytes */
  50. return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK)
  51. >> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M;
  52. }
  53. static struct mm_region axg_mem_map[] = {
  54. {
  55. .virt = 0x0UL,
  56. .phys = 0x0UL,
  57. .size = 0x80000000UL,
  58. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  59. PTE_BLOCK_INNER_SHARE
  60. }, {
  61. .virt = 0xf0000000UL,
  62. .phys = 0xf0000000UL,
  63. .size = 0x10000000UL,
  64. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  65. PTE_BLOCK_NON_SHARE |
  66. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  67. }, {
  68. /* List terminator */
  69. 0,
  70. }
  71. };
  72. struct mm_region *mem_map = axg_mem_map;
  73. /* Configure the Ethernet MAC with the requested interface mode
  74. * with some optional flags.
  75. */
  76. void meson_eth_init(phy_interface_t mode, unsigned int flags)
  77. {
  78. switch (mode) {
  79. case PHY_INTERFACE_MODE_RGMII:
  80. case PHY_INTERFACE_MODE_RGMII_ID:
  81. case PHY_INTERFACE_MODE_RGMII_RXID:
  82. case PHY_INTERFACE_MODE_RGMII_TXID:
  83. /* Set RGMII mode */
  84. setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
  85. AXG_ETH_REG_0_TX_PHASE(1) |
  86. AXG_ETH_REG_0_TX_RATIO(4) |
  87. AXG_ETH_REG_0_PHY_CLK_EN |
  88. AXG_ETH_REG_0_CLK_EN);
  89. break;
  90. case PHY_INTERFACE_MODE_RMII:
  91. /* Set RMII mode */
  92. out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
  93. AXG_ETH_REG_0_INVERT_RMII_CLK |
  94. AXG_ETH_REG_0_CLK_EN);
  95. break;
  96. default:
  97. printf("Invalid Ethernet interface mode\n");
  98. return;
  99. }
  100. /* Enable power gate */
  101. clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);
  102. }