mx6sxsabresd.c 9.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  6. */
  7. #include <init.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/crm_regs.h>
  10. #include <asm/arch/iomux.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/gpio.h>
  15. #include <asm/mach-imx/iomux-v3.h>
  16. #include <asm/io.h>
  17. #include <asm/mach-imx/mxc_i2c.h>
  18. #include <env.h>
  19. #include <linux/sizes.h>
  20. #include <common.h>
  21. #include <fsl_esdhc_imx.h>
  22. #include <mmc.h>
  23. #include <i2c.h>
  24. #include <miiphy.h>
  25. #include <netdev.h>
  26. #include <power/pmic.h>
  27. #include <power/pfuze100_pmic.h>
  28. #include "../common/pfuze.h"
  29. DECLARE_GLOBAL_DATA_PTR;
  30. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  31. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  32. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  33. #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  34. PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  35. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  36. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  37. PAD_CTL_SPEED_HIGH | \
  38. PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  39. #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  40. PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  41. #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  42. PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
  43. #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  44. PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  45. #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
  46. PAD_CTL_DSE_40ohm)
  47. int dram_init(void)
  48. {
  49. gd->ram_size = imx_ddr_size();
  50. return 0;
  51. }
  52. static iomux_v3_cfg_t const uart1_pads[] = {
  53. MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  54. MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  55. };
  56. static iomux_v3_cfg_t const wdog_b_pad = {
  57. MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  58. };
  59. static iomux_v3_cfg_t const fec1_pads[] = {
  60. MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  61. MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  62. MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  63. MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  64. MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  65. MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  66. MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  67. MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  68. MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  69. MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  70. MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  71. MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  72. MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  73. MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  74. };
  75. static iomux_v3_cfg_t const peri_3v3_pads[] = {
  76. MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
  77. };
  78. static iomux_v3_cfg_t const phy_control_pads[] = {
  79. /* 25MHz Ethernet PHY Clock */
  80. MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  81. /* ENET PHY Power */
  82. MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
  83. /* AR8031 PHY Reset */
  84. MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
  85. };
  86. static void setup_iomux_uart(void)
  87. {
  88. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  89. }
  90. static int setup_fec(void)
  91. {
  92. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  93. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  94. int reg, ret;
  95. /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
  96. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
  97. ret = enable_fec_anatop_clock(0, ENET_125MHZ);
  98. if (ret)
  99. return ret;
  100. imx_iomux_v3_setup_multiple_pads(phy_control_pads,
  101. ARRAY_SIZE(phy_control_pads));
  102. /* Enable the ENET power, active low */
  103. gpio_request(IMX_GPIO_NR(2, 6), "enet_rst");
  104. gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
  105. /* Reset AR8031 PHY */
  106. gpio_request(IMX_GPIO_NR(2, 7), "phy_rst");
  107. gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
  108. mdelay(10);
  109. gpio_set_value(IMX_GPIO_NR(2, 7), 1);
  110. reg = readl(&anatop->pll_enet);
  111. reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
  112. writel(reg, &anatop->pll_enet);
  113. return 0;
  114. }
  115. int board_eth_init(bd_t *bis)
  116. {
  117. imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
  118. setup_fec();
  119. return cpu_eth_init(bis);
  120. }
  121. int power_init_board(void)
  122. {
  123. struct udevice *dev;
  124. unsigned int reg;
  125. int ret;
  126. dev = pfuze_common_init();
  127. if (!dev)
  128. return -ENODEV;
  129. ret = pfuze_mode_init(dev, APS_PFM);
  130. if (ret < 0)
  131. return ret;
  132. /* Enable power of VGEN5 3V3, needed for SD3 */
  133. reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
  134. reg &= ~LDO_VOL_MASK;
  135. reg |= (LDOB_3_30V | (1 << LDO_EN));
  136. pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
  137. return 0;
  138. }
  139. int board_phy_config(struct phy_device *phydev)
  140. {
  141. /*
  142. * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
  143. * Phy control debug reg 0
  144. */
  145. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  146. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  147. /* rgmii tx clock delay enable */
  148. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  149. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  150. if (phydev->drv->config)
  151. phydev->drv->config(phydev);
  152. return 0;
  153. }
  154. int board_early_init_f(void)
  155. {
  156. setup_iomux_uart();
  157. /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
  158. imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
  159. ARRAY_SIZE(peri_3v3_pads));
  160. return 0;
  161. }
  162. int board_mmc_get_env_dev(int devno)
  163. {
  164. return devno;
  165. }
  166. #ifdef CONFIG_FSL_QSPI
  167. int board_qspi_init(void)
  168. {
  169. /* Set the clock */
  170. enable_qspi_clk(1);
  171. return 0;
  172. }
  173. #endif
  174. #ifdef CONFIG_VIDEO_MXS
  175. static iomux_v3_cfg_t const lcd_pads[] = {
  176. MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
  177. MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
  178. MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  179. MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  180. MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  181. MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  182. MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  183. MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  184. MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  185. MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  186. MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  187. MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  188. MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  189. MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  190. MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  191. MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  192. MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  193. MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  194. MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  195. MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  196. MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  197. MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  198. MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  199. MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  200. MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  201. MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  202. MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  203. MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  204. MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
  205. /* Use GPIO for Brightness adjustment, duty cycle = period */
  206. MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
  207. };
  208. static int setup_lcd(void)
  209. {
  210. enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
  211. imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
  212. /* Reset the LCD */
  213. gpio_request(IMX_GPIO_NR(3, 27), "lcd_rst");
  214. gpio_direction_output(IMX_GPIO_NR(3, 27) , 0);
  215. udelay(500);
  216. gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
  217. /* Set Brightness to high */
  218. gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright");
  219. gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
  220. return 0;
  221. }
  222. #endif
  223. int board_init(void)
  224. {
  225. /* Address of boot parameters */
  226. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  227. /*
  228. * Because kernel set WDOG_B mux before pad with the common pinctrl
  229. * framwork now and wdog reset will be triggered once set WDOG_B mux
  230. * with default pad setting, we set pad setting here to workaround this.
  231. * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
  232. * as GPIO mux firstly here to workaround it.
  233. */
  234. imx_iomux_v3_setup_pad(wdog_b_pad);
  235. /* Active high for ncp692 */
  236. gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en");
  237. gpio_direction_output(IMX_GPIO_NR(4, 16), 1);
  238. #ifdef CONFIG_FSL_QSPI
  239. board_qspi_init();
  240. #endif
  241. #ifdef CONFIG_VIDEO_MXS
  242. setup_lcd();
  243. #endif
  244. return 0;
  245. }
  246. static bool is_reva(void)
  247. {
  248. return (nxp_board_rev() == 1);
  249. }
  250. int board_late_init(void)
  251. {
  252. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  253. if (is_reva())
  254. env_set("board_rev", "REVA");
  255. #endif
  256. return 0;
  257. }
  258. int checkboard(void)
  259. {
  260. printf("Board: MX6SX SABRE SDB rev%c\n", nxp_board_rev_string());
  261. return 0;
  262. }