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- // SPDX-License-Identifier: GPL-2.0+
- /*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- */
- #include <init.h>
- #include <asm/arch/clock.h>
- #include <asm/arch/crm_regs.h>
- #include <asm/arch/iomux.h>
- #include <asm/arch/imx-regs.h>
- #include <asm/arch/mx6-pins.h>
- #include <asm/arch/sys_proto.h>
- #include <asm/gpio.h>
- #include <asm/mach-imx/iomux-v3.h>
- #include <asm/io.h>
- #include <asm/mach-imx/mxc_i2c.h>
- #include <env.h>
- #include <linux/sizes.h>
- #include <common.h>
- #include <fsl_esdhc_imx.h>
- #include <mmc.h>
- #include <i2c.h>
- #include <miiphy.h>
- #include <netdev.h>
- #include <power/pmic.h>
- #include <power/pfuze100_pmic.h>
- #include "../common/pfuze.h"
- DECLARE_GLOBAL_DATA_PTR;
- #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
- #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
- PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
- #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
- PAD_CTL_SPEED_HIGH | \
- PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
- #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
- #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
- #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
- PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
- #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm)
- int dram_init(void)
- {
- gd->ram_size = imx_ddr_size();
- return 0;
- }
- static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
- };
- static iomux_v3_cfg_t const wdog_b_pad = {
- MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
- };
- static iomux_v3_cfg_t const fec1_pads[] = {
- MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
- MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- };
- static iomux_v3_cfg_t const peri_3v3_pads[] = {
- MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
- };
- static iomux_v3_cfg_t const phy_control_pads[] = {
- /* 25MHz Ethernet PHY Clock */
- MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
- /* ENET PHY Power */
- MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* AR8031 PHY Reset */
- MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
- };
- static void setup_iomux_uart(void)
- {
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
- }
- static int setup_fec(void)
- {
- struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- int reg, ret;
- /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
- ret = enable_fec_anatop_clock(0, ENET_125MHZ);
- if (ret)
- return ret;
- imx_iomux_v3_setup_multiple_pads(phy_control_pads,
- ARRAY_SIZE(phy_control_pads));
- /* Enable the ENET power, active low */
- gpio_request(IMX_GPIO_NR(2, 6), "enet_rst");
- gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
- /* Reset AR8031 PHY */
- gpio_request(IMX_GPIO_NR(2, 7), "phy_rst");
- gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
- mdelay(10);
- gpio_set_value(IMX_GPIO_NR(2, 7), 1);
- reg = readl(&anatop->pll_enet);
- reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
- writel(reg, &anatop->pll_enet);
- return 0;
- }
- int board_eth_init(bd_t *bis)
- {
- imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
- setup_fec();
- return cpu_eth_init(bis);
- }
- int power_init_board(void)
- {
- struct udevice *dev;
- unsigned int reg;
- int ret;
- dev = pfuze_common_init();
- if (!dev)
- return -ENODEV;
- ret = pfuze_mode_init(dev, APS_PFM);
- if (ret < 0)
- return ret;
- /* Enable power of VGEN5 3V3, needed for SD3 */
- reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
- reg &= ~LDO_VOL_MASK;
- reg |= (LDOB_3_30V | (1 << LDO_EN));
- pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
- return 0;
- }
- int board_phy_config(struct phy_device *phydev)
- {
- /*
- * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
- * Phy control debug reg 0
- */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
- /* rgmii tx clock delay enable */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
- if (phydev->drv->config)
- phydev->drv->config(phydev);
- return 0;
- }
- int board_early_init_f(void)
- {
- setup_iomux_uart();
- /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
- imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
- ARRAY_SIZE(peri_3v3_pads));
- return 0;
- }
- int board_mmc_get_env_dev(int devno)
- {
- return devno;
- }
- #ifdef CONFIG_FSL_QSPI
- int board_qspi_init(void)
- {
- /* Set the clock */
- enable_qspi_clk(1);
- return 0;
- }
- #endif
- #ifdef CONFIG_VIDEO_MXS
- static iomux_v3_cfg_t const lcd_pads[] = {
- MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
- MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* Use GPIO for Brightness adjustment, duty cycle = period */
- MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
- };
- static int setup_lcd(void)
- {
- enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
- imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
- /* Reset the LCD */
- gpio_request(IMX_GPIO_NR(3, 27), "lcd_rst");
- gpio_direction_output(IMX_GPIO_NR(3, 27) , 0);
- udelay(500);
- gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
- /* Set Brightness to high */
- gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright");
- gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
- return 0;
- }
- #endif
- int board_init(void)
- {
- /* Address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
- /*
- * Because kernel set WDOG_B mux before pad with the common pinctrl
- * framwork now and wdog reset will be triggered once set WDOG_B mux
- * with default pad setting, we set pad setting here to workaround this.
- * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
- * as GPIO mux firstly here to workaround it.
- */
- imx_iomux_v3_setup_pad(wdog_b_pad);
- /* Active high for ncp692 */
- gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en");
- gpio_direction_output(IMX_GPIO_NR(4, 16), 1);
- #ifdef CONFIG_FSL_QSPI
- board_qspi_init();
- #endif
- #ifdef CONFIG_VIDEO_MXS
- setup_lcd();
- #endif
- return 0;
- }
- static bool is_reva(void)
- {
- return (nxp_board_rev() == 1);
- }
- int board_late_init(void)
- {
- #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- if (is_reva())
- env_set("board_rev", "REVA");
- #endif
- return 0;
- }
- int checkboard(void)
- {
- printf("Board: MX6SX SABRE SDB rev%c\n", nxp_board_rev_string());
- return 0;
- }
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