cpu.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #define LOG_CATEGORY LOGC_ARCH
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <cpu_func.h>
  9. #include <debug_uart.h>
  10. #include <env.h>
  11. #include <init.h>
  12. #include <log.h>
  13. #include <lmb.h>
  14. #include <misc.h>
  15. #include <net.h>
  16. #include <asm/io.h>
  17. #include <asm/arch/bsec.h>
  18. #include <asm/arch/stm32.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <asm/global_data.h>
  21. #include <dm/device.h>
  22. #include <dm/uclass.h>
  23. #include <linux/bitops.h>
  24. /* RCC register */
  25. #define RCC_TZCR (STM32_RCC_BASE + 0x00)
  26. #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
  27. #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
  28. #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
  29. #define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
  30. #define RCC_BDCR_VSWRST BIT(31)
  31. #define RCC_BDCR_RTCSRC GENMASK(17, 16)
  32. #define RCC_DBGCFGR_DBGCKEN BIT(8)
  33. /* Security register */
  34. #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
  35. #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
  36. #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
  37. #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
  38. #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
  39. #define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
  40. #define PWR_CR1 (STM32_PWR_BASE + 0x00)
  41. #define PWR_MCUCR (STM32_PWR_BASE + 0x14)
  42. #define PWR_CR1_DBP BIT(8)
  43. #define PWR_MCUCR_SBF BIT(6)
  44. /* DBGMCU register */
  45. #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
  46. #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
  47. #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
  48. #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
  49. #define DBGMCU_IDC_DEV_ID_SHIFT 0
  50. #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
  51. #define DBGMCU_IDC_REV_ID_SHIFT 16
  52. /* GPIOZ registers */
  53. #define GPIOZ_SECCFGR 0x54004030
  54. /* boot interface from Bootrom
  55. * - boot instance = bit 31:16
  56. * - boot device = bit 15:0
  57. */
  58. #define BOOTROM_PARAM_ADDR 0x2FFC0078
  59. #define BOOTROM_MODE_MASK GENMASK(15, 0)
  60. #define BOOTROM_MODE_SHIFT 0
  61. #define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
  62. #define BOOTROM_INSTANCE_SHIFT 16
  63. /* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
  64. #define RPN_SHIFT 0
  65. #define RPN_MASK GENMASK(7, 0)
  66. /* Package = bit 27:29 of OTP16
  67. * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
  68. * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
  69. * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
  70. * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
  71. * - others: Reserved
  72. */
  73. #define PKG_SHIFT 27
  74. #define PKG_MASK GENMASK(2, 0)
  75. /*
  76. * early TLB into the .data section so that it not get cleared
  77. * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
  78. */
  79. u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
  80. struct lmb lmb;
  81. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  82. #ifndef CONFIG_TFABOOT
  83. static void security_init(void)
  84. {
  85. /* Disable the backup domain write protection */
  86. /* the protection is enable at each reset by hardware */
  87. /* And must be disable by software */
  88. setbits_le32(PWR_CR1, PWR_CR1_DBP);
  89. while (!(readl(PWR_CR1) & PWR_CR1_DBP))
  90. ;
  91. /* If RTC clock isn't enable so this is a cold boot then we need
  92. * to reset the backup domain
  93. */
  94. if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
  95. setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
  96. while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
  97. ;
  98. clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
  99. }
  100. /* allow non secure access in Write/Read for all peripheral */
  101. writel(GENMASK(25, 0), ETZPC_DECPROT0);
  102. /* Open SYSRAM for no secure access */
  103. writel(0x0, ETZPC_TZMA1_SIZE);
  104. /* enable TZC1 TZC2 clock */
  105. writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
  106. /* Region 0 set to no access by default */
  107. /* bit 0 / 16 => nsaid0 read/write Enable
  108. * bit 1 / 17 => nsaid1 read/write Enable
  109. * ...
  110. * bit 15 / 31 => nsaid15 read/write Enable
  111. */
  112. writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
  113. /* bit 30 / 31 => Secure Global Enable : write/read */
  114. /* bit 0 / 1 => Region Enable for filter 0/1 */
  115. writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
  116. /* Enable Filter 0 and 1 */
  117. setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
  118. /* RCC trust zone deactivated */
  119. writel(0x0, RCC_TZCR);
  120. /* TAMP: deactivate the internal tamper
  121. * Bit 23 ITAMP8E: monotonic counter overflow
  122. * Bit 20 ITAMP5E: RTC calendar overflow
  123. * Bit 19 ITAMP4E: HSE monitoring
  124. * Bit 18 ITAMP3E: LSE monitoring
  125. * Bit 16 ITAMP1E: RTC power domain supply monitoring
  126. */
  127. writel(0x0, TAMP_CR1);
  128. /* GPIOZ: deactivate the security */
  129. writel(BIT(0), RCC_MP_AHB5ENSETR);
  130. writel(0x0, GPIOZ_SECCFGR);
  131. }
  132. #endif /* CONFIG_TFABOOT */
  133. /*
  134. * Debug init
  135. */
  136. static void dbgmcu_init(void)
  137. {
  138. /*
  139. * Freeze IWDG2 if Cortex-A7 is in debug mode
  140. * done in TF-A for TRUSTED boot and
  141. * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE
  142. */
  143. if (!IS_ENABLED(CONFIG_TFABOOT) && bsec_dbgswenable()) {
  144. setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
  145. setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
  146. }
  147. }
  148. void spl_board_init(void)
  149. {
  150. dbgmcu_init();
  151. }
  152. #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
  153. #if !defined(CONFIG_TFABOOT) && \
  154. (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  155. /* get bootmode from ROM code boot context: saved in TAMP register */
  156. static void update_bootmode(void)
  157. {
  158. u32 boot_mode;
  159. u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
  160. u32 bootrom_device, bootrom_instance;
  161. /* enable TAMP clock = RTCAPBEN */
  162. writel(BIT(8), RCC_MP_APB5ENSETR);
  163. /* read bootrom context */
  164. bootrom_device =
  165. (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
  166. bootrom_instance =
  167. (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
  168. boot_mode =
  169. ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
  170. ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
  171. BOOT_INSTANCE_MASK);
  172. /* save the boot mode in TAMP backup register */
  173. clrsetbits_le32(TAMP_BOOT_CONTEXT,
  174. TAMP_BOOT_MODE_MASK,
  175. boot_mode << TAMP_BOOT_MODE_SHIFT);
  176. }
  177. #endif
  178. u32 get_bootmode(void)
  179. {
  180. /* read bootmode from TAMP backup register */
  181. return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
  182. TAMP_BOOT_MODE_SHIFT;
  183. }
  184. /*
  185. * weak function overidde: set the DDR/SYSRAM executable before to enable the
  186. * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc)
  187. */
  188. void dram_bank_mmu_setup(int bank)
  189. {
  190. struct bd_info *bd = gd->bd;
  191. int i;
  192. phys_addr_t start;
  193. phys_size_t size;
  194. bool use_lmb = false;
  195. enum dcache_option option;
  196. if (IS_ENABLED(CONFIG_SPL_BUILD)) {
  197. start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
  198. size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE);
  199. } else if (gd->flags & GD_FLG_RELOC) {
  200. /* bd->bi_dram is available only after relocation */
  201. start = bd->bi_dram[bank].start;
  202. size = bd->bi_dram[bank].size;
  203. use_lmb = true;
  204. } else {
  205. /* mark cacheable and executable the beggining of the DDR */
  206. start = STM32_DDR_BASE;
  207. size = CONFIG_DDR_CACHEABLE_SIZE;
  208. }
  209. for (i = start >> MMU_SECTION_SHIFT;
  210. i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
  211. i++) {
  212. option = DCACHE_DEFAULT_OPTION;
  213. if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP))
  214. option = 0; /* INVALID ENTRY in TLB */
  215. set_section_dcache(i, option);
  216. }
  217. }
  218. /*
  219. * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
  220. * MMU/TLB is updated in enable_caches() for U-Boot after relocation
  221. * or is deactivated in U-Boot entry function start.S::cpu_init_cp15
  222. */
  223. static void early_enable_caches(void)
  224. {
  225. /* I-cache is already enabled in start.S: cpu_init_cp15 */
  226. if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
  227. return;
  228. if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
  229. gd->arch.tlb_size = PGTABLE_SIZE;
  230. gd->arch.tlb_addr = (unsigned long)&early_tlb;
  231. }
  232. /* enable MMU (default configuration) */
  233. dcache_enable();
  234. }
  235. /*
  236. * Early system init
  237. */
  238. int arch_cpu_init(void)
  239. {
  240. u32 boot_mode;
  241. early_enable_caches();
  242. /* early armv7 timer init: needed for polling */
  243. timer_init();
  244. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  245. #ifndef CONFIG_TFABOOT
  246. security_init();
  247. update_bootmode();
  248. #endif
  249. /* Reset Coprocessor state unless it wakes up from Standby power mode */
  250. if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
  251. writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
  252. writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
  253. }
  254. #endif
  255. boot_mode = get_bootmode();
  256. if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) &&
  257. (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
  258. gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
  259. #if defined(CONFIG_DEBUG_UART) && \
  260. !defined(CONFIG_TFABOOT) && \
  261. (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  262. else
  263. debug_uart_init();
  264. #endif
  265. return 0;
  266. }
  267. void enable_caches(void)
  268. {
  269. /* parse device tree when data cache is still activated */
  270. lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
  271. /* I-cache is already enabled in start.S: icache_enable() not needed */
  272. /* deactivate the data cache, early enabled in arch_cpu_init() */
  273. dcache_disable();
  274. /*
  275. * update MMU after relocation and enable the data cache
  276. * warning: the TLB location udpated in board_f.c::reserve_mmu
  277. */
  278. dcache_enable();
  279. }
  280. static u32 read_idc(void)
  281. {
  282. /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */
  283. if (bsec_dbgswenable()) {
  284. setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
  285. return readl(DBGMCU_IDC);
  286. }
  287. if (CONFIG_IS_ENABLED(STM32MP15x))
  288. return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */
  289. else
  290. return 0x0;
  291. }
  292. u32 get_cpu_dev(void)
  293. {
  294. return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
  295. }
  296. u32 get_cpu_rev(void)
  297. {
  298. return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
  299. }
  300. static u32 get_otp(int index, int shift, int mask)
  301. {
  302. int ret;
  303. struct udevice *dev;
  304. u32 otp = 0;
  305. ret = uclass_get_device_by_driver(UCLASS_MISC,
  306. DM_DRIVER_GET(stm32mp_bsec),
  307. &dev);
  308. if (!ret)
  309. ret = misc_read(dev, STM32_BSEC_SHADOW(index),
  310. &otp, sizeof(otp));
  311. return (otp >> shift) & mask;
  312. }
  313. /* Get Device Part Number (RPN) from OTP */
  314. static u32 get_cpu_rpn(void)
  315. {
  316. return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
  317. }
  318. u32 get_cpu_type(void)
  319. {
  320. return (get_cpu_dev() << 16) | get_cpu_rpn();
  321. }
  322. /* Get Package options from OTP */
  323. u32 get_cpu_package(void)
  324. {
  325. return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
  326. }
  327. static const char * const soc_type[] = {
  328. "????",
  329. "151C", "151A", "151F", "151D",
  330. "153C", "153A", "153F", "153D",
  331. "157C", "157A", "157F", "157D"
  332. };
  333. static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" };
  334. static const char * const soc_rev[] = { "?", "A", "B", "Z" };
  335. static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg,
  336. unsigned int *rev)
  337. {
  338. u32 cpu_type = get_cpu_type();
  339. u32 ct = cpu_type & ~(BIT(7) | BIT(0));
  340. u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0));
  341. u32 cp = get_cpu_package();
  342. /* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */
  343. switch (ct) {
  344. case CPU_STM32MP151Cxx:
  345. *type = cm + 1;
  346. break;
  347. case CPU_STM32MP153Cxx:
  348. *type = cm + 5;
  349. break;
  350. case CPU_STM32MP157Cxx:
  351. *type = cm + 9;
  352. break;
  353. default:
  354. *type = 0;
  355. break;
  356. }
  357. /* Package */
  358. switch (cp) {
  359. case PKG_AA_LBGA448:
  360. case PKG_AB_LBGA354:
  361. case PKG_AC_TFBGA361:
  362. case PKG_AD_TFBGA257:
  363. *pkg = cp;
  364. break;
  365. default:
  366. *pkg = 0;
  367. break;
  368. }
  369. /* Revision */
  370. switch (get_cpu_rev()) {
  371. case CPU_REVA:
  372. *rev = 1;
  373. break;
  374. case CPU_REVB:
  375. *rev = 2;
  376. break;
  377. case CPU_REVZ:
  378. *rev = 3;
  379. break;
  380. default:
  381. *rev = 0;
  382. break;
  383. }
  384. }
  385. void get_soc_name(char name[SOC_NAME_SIZE])
  386. {
  387. unsigned int type, pkg, rev;
  388. get_cpu_string_offsets(&type, &pkg, &rev);
  389. snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s",
  390. soc_type[type], soc_pkg[pkg], soc_rev[rev]);
  391. }
  392. #if defined(CONFIG_DISPLAY_CPUINFO)
  393. int print_cpuinfo(void)
  394. {
  395. char name[SOC_NAME_SIZE];
  396. get_soc_name(name);
  397. printf("CPU: %s\n", name);
  398. return 0;
  399. }
  400. #endif /* CONFIG_DISPLAY_CPUINFO */
  401. static void setup_boot_mode(void)
  402. {
  403. const u32 serial_addr[] = {
  404. STM32_USART1_BASE,
  405. STM32_USART2_BASE,
  406. STM32_USART3_BASE,
  407. STM32_UART4_BASE,
  408. STM32_UART5_BASE,
  409. STM32_USART6_BASE,
  410. STM32_UART7_BASE,
  411. STM32_UART8_BASE
  412. };
  413. const u32 sdmmc_addr[] = {
  414. STM32_SDMMC1_BASE,
  415. STM32_SDMMC2_BASE,
  416. STM32_SDMMC3_BASE
  417. };
  418. char cmd[60];
  419. u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
  420. u32 boot_mode =
  421. (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
  422. unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
  423. u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
  424. struct udevice *dev;
  425. log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
  426. __func__, boot_ctx, boot_mode, instance, forced_mode);
  427. switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
  428. case BOOT_SERIAL_UART:
  429. if (instance > ARRAY_SIZE(serial_addr))
  430. break;
  431. /* serial : search associated node in devicetree */
  432. sprintf(cmd, "serial@%x", serial_addr[instance]);
  433. if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) {
  434. /* restore console on error */
  435. if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL))
  436. gd->flags &= ~(GD_FLG_SILENT |
  437. GD_FLG_DISABLE_CONSOLE);
  438. log_err("uart%d = %s not found in device tree!\n",
  439. instance + 1, cmd);
  440. break;
  441. }
  442. sprintf(cmd, "%d", dev_seq(dev));
  443. env_set("boot_device", "serial");
  444. env_set("boot_instance", cmd);
  445. /* restore console on uart when not used */
  446. if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) {
  447. gd->flags &= ~(GD_FLG_SILENT |
  448. GD_FLG_DISABLE_CONSOLE);
  449. log_info("serial boot with console enabled!\n");
  450. }
  451. break;
  452. case BOOT_SERIAL_USB:
  453. env_set("boot_device", "usb");
  454. env_set("boot_instance", "0");
  455. break;
  456. case BOOT_FLASH_SD:
  457. case BOOT_FLASH_EMMC:
  458. if (instance > ARRAY_SIZE(sdmmc_addr))
  459. break;
  460. /* search associated sdmmc node in devicetree */
  461. sprintf(cmd, "mmc@%x", sdmmc_addr[instance]);
  462. if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) {
  463. printf("mmc%d = %s not found in device tree!\n",
  464. instance, cmd);
  465. break;
  466. }
  467. sprintf(cmd, "%d", dev_seq(dev));
  468. env_set("boot_device", "mmc");
  469. env_set("boot_instance", cmd);
  470. break;
  471. case BOOT_FLASH_NAND:
  472. env_set("boot_device", "nand");
  473. env_set("boot_instance", "0");
  474. break;
  475. case BOOT_FLASH_SPINAND:
  476. env_set("boot_device", "spi-nand");
  477. env_set("boot_instance", "0");
  478. break;
  479. case BOOT_FLASH_NOR:
  480. env_set("boot_device", "nor");
  481. env_set("boot_instance", "0");
  482. break;
  483. default:
  484. log_debug("unexpected boot mode = %x\n", boot_mode);
  485. break;
  486. }
  487. switch (forced_mode) {
  488. case BOOT_FASTBOOT:
  489. log_info("Enter fastboot!\n");
  490. env_set("preboot", "env set preboot; fastboot 0");
  491. break;
  492. case BOOT_STM32PROG:
  493. env_set("boot_device", "usb");
  494. env_set("boot_instance", "0");
  495. break;
  496. case BOOT_UMS_MMC0:
  497. case BOOT_UMS_MMC1:
  498. case BOOT_UMS_MMC2:
  499. log_info("Enter UMS!\n");
  500. instance = forced_mode - BOOT_UMS_MMC0;
  501. sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
  502. env_set("preboot", cmd);
  503. break;
  504. case BOOT_RECOVERY:
  505. env_set("preboot", "env set preboot; run altbootcmd");
  506. break;
  507. case BOOT_NORMAL:
  508. break;
  509. default:
  510. log_debug("unexpected forced boot mode = %x\n", forced_mode);
  511. break;
  512. }
  513. /* clear TAMP for next reboot */
  514. clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
  515. }
  516. /*
  517. * If there is no MAC address in the environment, then it will be initialized
  518. * (silently) from the value in the OTP.
  519. */
  520. __weak int setup_mac_address(void)
  521. {
  522. #if defined(CONFIG_NET)
  523. int ret;
  524. int i;
  525. u32 otp[2];
  526. uchar enetaddr[6];
  527. struct udevice *dev;
  528. /* MAC already in environment */
  529. if (eth_env_get_enetaddr("ethaddr", enetaddr))
  530. return 0;
  531. ret = uclass_get_device_by_driver(UCLASS_MISC,
  532. DM_DRIVER_GET(stm32mp_bsec),
  533. &dev);
  534. if (ret)
  535. return ret;
  536. ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC),
  537. otp, sizeof(otp));
  538. if (ret < 0)
  539. return ret;
  540. for (i = 0; i < 6; i++)
  541. enetaddr[i] = ((uint8_t *)&otp)[i];
  542. if (!is_valid_ethaddr(enetaddr)) {
  543. log_err("invalid MAC address in OTP %pM\n", enetaddr);
  544. return -EINVAL;
  545. }
  546. log_debug("OTP MAC address = %pM\n", enetaddr);
  547. ret = eth_env_set_enetaddr("ethaddr", enetaddr);
  548. if (ret)
  549. log_err("Failed to set mac address %pM from OTP: %d\n", enetaddr, ret);
  550. #endif
  551. return 0;
  552. }
  553. static int setup_serial_number(void)
  554. {
  555. char serial_string[25];
  556. u32 otp[3] = {0, 0, 0 };
  557. struct udevice *dev;
  558. int ret;
  559. if (env_get("serial#"))
  560. return 0;
  561. ret = uclass_get_device_by_driver(UCLASS_MISC,
  562. DM_DRIVER_GET(stm32mp_bsec),
  563. &dev);
  564. if (ret)
  565. return ret;
  566. ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
  567. otp, sizeof(otp));
  568. if (ret < 0)
  569. return ret;
  570. sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
  571. env_set("serial#", serial_string);
  572. return 0;
  573. }
  574. static void setup_soc_type_pkg_rev(void)
  575. {
  576. unsigned int type, pkg, rev;
  577. get_cpu_string_offsets(&type, &pkg, &rev);
  578. env_set("soc_type", soc_type[type]);
  579. env_set("soc_pkg", soc_pkg[pkg]);
  580. env_set("soc_rev", soc_rev[rev]);
  581. }
  582. int arch_misc_init(void)
  583. {
  584. setup_boot_mode();
  585. setup_mac_address();
  586. setup_serial_number();
  587. setup_soc_type_pkg_rev();
  588. return 0;
  589. }