mtrr.h 5.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2014 Google, Inc
  4. *
  5. * From Coreboot file of the same name
  6. */
  7. #ifndef _ASM_MTRR_H
  8. #define _ASM_MTRR_H
  9. /* MTRR region types */
  10. #define MTRR_TYPE_UNCACHEABLE 0
  11. #define MTRR_TYPE_WRCOMB 1
  12. #define MTRR_TYPE_WRTHROUGH 4
  13. #define MTRR_TYPE_WRPROT 5
  14. #define MTRR_TYPE_WRBACK 6
  15. #define MTRR_TYPE_COUNT 7
  16. #define MTRR_CAP_MSR 0x0fe
  17. #define MTRR_DEF_TYPE_MSR 0x2ff
  18. #define MTRR_CAP_SMRR (1 << 11)
  19. #define MTRR_CAP_WC (1 << 10)
  20. #define MTRR_CAP_FIX (1 << 8)
  21. #define MTRR_CAP_VCNT_MASK 0xff
  22. #define MTRR_DEF_TYPE_MASK 0xff
  23. #define MTRR_DEF_TYPE_EN (1 << 11)
  24. #define MTRR_DEF_TYPE_FIX_EN (1 << 10)
  25. #define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
  26. #define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)
  27. #define MTRR_PHYS_MASK_VALID (1 << 11)
  28. #define MTRR_BASE_TYPE_MASK 0x7
  29. /* Maximum number of MTRRs supported - see also mtrr_get_var_count() */
  30. #define MTRR_MAX_COUNT 10
  31. #define NUM_FIXED_MTRRS 11
  32. #define RANGES_PER_FIXED_MTRR 8
  33. #define NUM_FIXED_RANGES (NUM_FIXED_MTRRS * RANGES_PER_FIXED_MTRR)
  34. #define MTRR_FIX_64K_00000_MSR 0x250
  35. #define MTRR_FIX_16K_80000_MSR 0x258
  36. #define MTRR_FIX_16K_A0000_MSR 0x259
  37. #define MTRR_FIX_4K_C0000_MSR 0x268
  38. #define MTRR_FIX_4K_C8000_MSR 0x269
  39. #define MTRR_FIX_4K_D0000_MSR 0x26a
  40. #define MTRR_FIX_4K_D8000_MSR 0x26b
  41. #define MTRR_FIX_4K_E0000_MSR 0x26c
  42. #define MTRR_FIX_4K_E8000_MSR 0x26d
  43. #define MTRR_FIX_4K_F0000_MSR 0x26e
  44. #define MTRR_FIX_4K_F8000_MSR 0x26f
  45. #define MTRR_FIX_TYPE(t) ((t << 24) | (t << 16) | (t << 8) | t)
  46. #if !defined(__ASSEMBLY__)
  47. /**
  48. * Information about the previous MTRR state, set up by mtrr_open()
  49. *
  50. * @deftype: Previous value of MTRR_DEF_TYPE_MSR
  51. * @enable_cache: true if cache was enabled
  52. */
  53. struct mtrr_state {
  54. uint64_t deftype;
  55. bool enable_cache;
  56. };
  57. /**
  58. * struct mtrr - Information about a single MTRR
  59. *
  60. * @base: Base address and MTRR_BASE_TYPE_MASK
  61. * @mask: Mask and MTRR_PHYS_MASK_VALID
  62. */
  63. struct mtrr {
  64. u64 base;
  65. u64 mask;
  66. };
  67. /**
  68. * struct mtrr_info - Information about all MTRRs
  69. *
  70. * @mtrr: Information about each mtrr
  71. */
  72. struct mtrr_info {
  73. struct mtrr mtrr[MTRR_MAX_COUNT];
  74. };
  75. /**
  76. * mtrr_open() - Prepare to adjust MTRRs
  77. *
  78. * Use mtrr_open() passing in a structure - this function will init it. Then
  79. * when done, pass the same structure to mtrr_close() to re-enable MTRRs and
  80. * possibly the cache.
  81. *
  82. * @state: Empty structure to pass in to hold settings
  83. * @do_caches: true to disable caches before opening
  84. */
  85. void mtrr_open(struct mtrr_state *state, bool do_caches);
  86. /**
  87. * mtrr_close() - Clean up after adjusting MTRRs, and enable them
  88. *
  89. * This uses the structure containing information returned from mtrr_open().
  90. *
  91. * @state: Structure from mtrr_open()
  92. * @state: true to restore cache state to that before mtrr_open()
  93. */
  94. void mtrr_close(struct mtrr_state *state, bool do_caches);
  95. /**
  96. * mtrr_add_request() - Add a new MTRR request
  97. *
  98. * This adds a request for a memory region to be set up in a particular way.
  99. *
  100. * @type: Requested type (MTRR_TYPE_)
  101. * @start: Start address
  102. * @size: Size, must be power of 2
  103. *
  104. * @return: 0 on success, non-zero on failure
  105. */
  106. int mtrr_add_request(int type, uint64_t start, uint64_t size);
  107. /**
  108. * mtrr_commit() - set up the MTRR registers based on current requests
  109. *
  110. * This sets up MTRRs for the available DRAM and the requests received so far.
  111. * It must be called with caches disabled.
  112. *
  113. * @do_caches: true if caches are currently on
  114. *
  115. * @return: 0 on success, non-zero on failure
  116. */
  117. int mtrr_commit(bool do_caches);
  118. /**
  119. * mtrr_set_next_var() - set up a variable MTRR
  120. *
  121. * This finds the first free variable MTRR and sets to the given area
  122. *
  123. * @type: Requested type (MTRR_TYPE_)
  124. * @start: Start address
  125. * @size: Size, must be power of 2
  126. * @return 0 on success, -EINVAL if size is not power of 2,
  127. * -ENOSPC if there are no more MTRRs
  128. */
  129. int mtrr_set_next_var(uint type, uint64_t base, uint64_t size);
  130. /**
  131. * mtrr_read_all() - Save all the MTRRs
  132. *
  133. * This reads all MTRRs from the boot CPU into a struct so they can be loaded
  134. * onto other CPUs
  135. *
  136. * @info: Place to put the MTRR info
  137. */
  138. void mtrr_read_all(struct mtrr_info *info);
  139. /**
  140. * mtrr_set_valid() - Set the valid flag for a selected MTRR and CPU(s)
  141. *
  142. * @cpu_select: Selected CPUs (either a CPU number or MP_SELECT_...)
  143. * @reg: MTRR register to write (0-7)
  144. * @valid: Valid flag to write
  145. * @return 0 on success, -ve on error
  146. */
  147. int mtrr_set_valid(int cpu_select, int reg, bool valid);
  148. /**
  149. * mtrr_set() - Set the base address and mask for a selected MTRR and CPU(s)
  150. *
  151. * @cpu_select: Selected CPUs (either a CPU number or MP_SELECT_...)
  152. * @reg: MTRR register to write (0-7)
  153. * @base: Base address and MTRR_BASE_TYPE_MASK
  154. * @mask: Mask and MTRR_PHYS_MASK_VALID
  155. * @return 0 on success, -ve on error
  156. */
  157. int mtrr_set(int cpu_select, int reg, u64 base, u64 mask);
  158. /**
  159. * mtrr_get_var_count() - Get the number of variable MTRRs
  160. *
  161. * Some CPUs have more than 8 MTRRs. This function returns the actual number
  162. *
  163. * @return number of variable MTRRs
  164. */
  165. int mtrr_get_var_count(void);
  166. #endif
  167. #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
  168. # error "CONFIG_XIP_ROM_SIZE is not a power of 2"
  169. #endif
  170. #if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0)
  171. # error "CONFIG_CACHE_ROM_SIZE is not a power of 2"
  172. #endif
  173. #define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12)
  174. #endif