minnowmax.dts 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
  4. */
  5. /dts-v1/;
  6. #include <asm/arch-baytrail/fsp/fsp_configs.h>
  7. #include <dt-bindings/gpio/x86-gpio.h>
  8. #include <dt-bindings/interrupt-router/intel-irq.h>
  9. /include/ "skeleton.dtsi"
  10. /include/ "serial.dtsi"
  11. /include/ "reset.dtsi"
  12. /include/ "rtc.dtsi"
  13. #include "tsc_timer.dtsi"
  14. #include "smbios.dtsi"
  15. / {
  16. model = "Intel Minnowboard Max";
  17. compatible = "intel,minnowmax", "intel,baytrail";
  18. aliases {
  19. serial0 = &serial;
  20. spi0 = &spi;
  21. };
  22. config {
  23. silent_console = <0>;
  24. };
  25. pch_pinctrl {
  26. compatible = "intel,x86-pinctrl";
  27. reg = <0 0>;
  28. /* GPIO E0 */
  29. soc_gpio_s5_0@0 {
  30. gpio-offset = <0x80 0>;
  31. mode-gpio;
  32. output-value = <0>;
  33. direction = <PIN_OUTPUT>;
  34. };
  35. /* GPIO E1 */
  36. soc_gpio_s5_1@0 {
  37. gpio-offset = <0x80 1>;
  38. mode-gpio;
  39. output-value = <0>;
  40. direction = <PIN_OUTPUT>;
  41. };
  42. /* GPIO E2 */
  43. soc_gpio_s5_2@0 {
  44. gpio-offset = <0x80 2>;
  45. mode-gpio;
  46. output-value = <0>;
  47. direction = <PIN_OUTPUT>;
  48. };
  49. pin_usb_host_en0@0 {
  50. gpio-offset = <0x80 8>;
  51. mode-gpio;
  52. output-value = <1>;
  53. direction = <PIN_OUTPUT>;
  54. };
  55. pin_usb_host_en1@0 {
  56. gpio-offset = <0x80 9>;
  57. mode-gpio;
  58. output-value = <1>;
  59. direction = <PIN_OUTPUT>;
  60. };
  61. /*
  62. * As of today, the latest version FSP (gold4) for BayTrail
  63. * misses the PAD configuration of the SD controller's Card
  64. * Detect signal. The default PAD value for the CD pin sets
  65. * the pin to work in GPIO mode, which causes card detect
  66. * status cannot be reflected by the Present State register
  67. * in the SD controller (bit 16 & bit 18 are always zero).
  68. *
  69. * Configure this pin to function 1 (SD controller).
  70. */
  71. sdmmc3_cd@0 {
  72. pad-offset = <0x3a0>;
  73. mode-func = <1>;
  74. };
  75. };
  76. chosen {
  77. stdout-path = "/serial";
  78. };
  79. cpus {
  80. #address-cells = <1>;
  81. #size-cells = <0>;
  82. cpu@0 {
  83. device_type = "cpu";
  84. compatible = "intel,baytrail-cpu";
  85. reg = <0>;
  86. intel,apic-id = <0>;
  87. };
  88. cpu@1 {
  89. device_type = "cpu";
  90. compatible = "intel,baytrail-cpu";
  91. reg = <1>;
  92. intel,apic-id = <4>;
  93. };
  94. };
  95. pci {
  96. compatible = "intel,pci-baytrail", "pci-x86";
  97. #address-cells = <3>;
  98. #size-cells = <2>;
  99. u-boot,dm-pre-reloc;
  100. ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
  101. 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
  102. 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  103. pch@1f,0 {
  104. reg = <0x0000f800 0 0 0 0>;
  105. compatible = "pci8086,0f1c", "intel,pch9";
  106. #address-cells = <1>;
  107. #size-cells = <1>;
  108. irq-router {
  109. compatible = "intel,irq-router";
  110. intel,pirq-config = "ibase";
  111. intel,ibase-offset = <0x50>;
  112. intel,actl-addr = <0>;
  113. intel,pirq-link = <8 8>;
  114. intel,pirq-mask = <0xdee0>;
  115. intel,pirq-routing = <
  116. /* BayTrail PCI devices */
  117. PCI_BDF(0, 2, 0) INTA PIRQA
  118. PCI_BDF(0, 3, 0) INTA PIRQA
  119. PCI_BDF(0, 16, 0) INTA PIRQA
  120. PCI_BDF(0, 17, 0) INTA PIRQA
  121. PCI_BDF(0, 18, 0) INTA PIRQA
  122. PCI_BDF(0, 19, 0) INTA PIRQA
  123. PCI_BDF(0, 20, 0) INTA PIRQA
  124. PCI_BDF(0, 21, 0) INTA PIRQA
  125. PCI_BDF(0, 22, 0) INTA PIRQA
  126. PCI_BDF(0, 23, 0) INTA PIRQA
  127. PCI_BDF(0, 24, 0) INTA PIRQA
  128. PCI_BDF(0, 24, 1) INTC PIRQC
  129. PCI_BDF(0, 24, 2) INTD PIRQD
  130. PCI_BDF(0, 24, 3) INTB PIRQB
  131. PCI_BDF(0, 24, 4) INTA PIRQA
  132. PCI_BDF(0, 24, 5) INTC PIRQC
  133. PCI_BDF(0, 24, 6) INTD PIRQD
  134. PCI_BDF(0, 24, 7) INTB PIRQB
  135. PCI_BDF(0, 26, 0) INTA PIRQA
  136. PCI_BDF(0, 27, 0) INTA PIRQA
  137. PCI_BDF(0, 28, 0) INTA PIRQA
  138. PCI_BDF(0, 28, 1) INTB PIRQB
  139. PCI_BDF(0, 28, 2) INTC PIRQC
  140. PCI_BDF(0, 28, 3) INTD PIRQD
  141. PCI_BDF(0, 29, 0) INTA PIRQA
  142. PCI_BDF(0, 30, 0) INTA PIRQA
  143. PCI_BDF(0, 30, 1) INTD PIRQD
  144. PCI_BDF(0, 30, 2) INTB PIRQB
  145. PCI_BDF(0, 30, 3) INTC PIRQC
  146. PCI_BDF(0, 30, 4) INTD PIRQD
  147. PCI_BDF(0, 30, 5) INTB PIRQB
  148. PCI_BDF(0, 31, 3) INTB PIRQB
  149. /*
  150. * PCIe root ports downstream
  151. * interrupts
  152. */
  153. PCI_BDF(1, 0, 0) INTA PIRQA
  154. PCI_BDF(1, 0, 0) INTB PIRQB
  155. PCI_BDF(1, 0, 0) INTC PIRQC
  156. PCI_BDF(1, 0, 0) INTD PIRQD
  157. PCI_BDF(2, 0, 0) INTA PIRQB
  158. PCI_BDF(2, 0, 0) INTB PIRQC
  159. PCI_BDF(2, 0, 0) INTC PIRQD
  160. PCI_BDF(2, 0, 0) INTD PIRQA
  161. PCI_BDF(3, 0, 0) INTA PIRQC
  162. PCI_BDF(3, 0, 0) INTB PIRQD
  163. PCI_BDF(3, 0, 0) INTC PIRQA
  164. PCI_BDF(3, 0, 0) INTD PIRQB
  165. PCI_BDF(4, 0, 0) INTA PIRQD
  166. PCI_BDF(4, 0, 0) INTB PIRQA
  167. PCI_BDF(4, 0, 0) INTC PIRQB
  168. PCI_BDF(4, 0, 0) INTD PIRQC
  169. >;
  170. };
  171. spi: spi {
  172. #address-cells = <1>;
  173. #size-cells = <0>;
  174. compatible = "intel,ich9-spi";
  175. spi-flash@0 {
  176. #address-cells = <1>;
  177. #size-cells = <1>;
  178. reg = <0>;
  179. m25p,fast-read;
  180. compatible = "stmicro,n25q064a",
  181. "jedec,spi-nor";
  182. memory-map = <0xff800000 0x00800000>;
  183. rw-mrc-cache {
  184. label = "rw-mrc-cache";
  185. reg = <0x006f0000 0x00010000>;
  186. };
  187. };
  188. };
  189. gpioa {
  190. compatible = "intel,ich6-gpio";
  191. u-boot,dm-pre-reloc;
  192. reg = <0 0x20>;
  193. bank-name = "A";
  194. use-lvl-write-cache;
  195. };
  196. gpiob {
  197. compatible = "intel,ich6-gpio";
  198. u-boot,dm-pre-reloc;
  199. reg = <0x20 0x20>;
  200. bank-name = "B";
  201. use-lvl-write-cache;
  202. };
  203. gpioc {
  204. compatible = "intel,ich6-gpio";
  205. u-boot,dm-pre-reloc;
  206. reg = <0x40 0x20>;
  207. bank-name = "C";
  208. use-lvl-write-cache;
  209. };
  210. gpiod {
  211. compatible = "intel,ich6-gpio";
  212. u-boot,dm-pre-reloc;
  213. reg = <0x60 0x20>;
  214. bank-name = "D";
  215. use-lvl-write-cache;
  216. };
  217. gpioe {
  218. compatible = "intel,ich6-gpio";
  219. u-boot,dm-pre-reloc;
  220. reg = <0x80 0x20>;
  221. bank-name = "E";
  222. use-lvl-write-cache;
  223. };
  224. gpiof {
  225. compatible = "intel,ich6-gpio";
  226. u-boot,dm-pre-reloc;
  227. reg = <0xA0 0x20>;
  228. bank-name = "F";
  229. use-lvl-write-cache;
  230. };
  231. };
  232. };
  233. fsp {
  234. compatible = "intel,baytrail-fsp";
  235. fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
  236. fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
  237. fsp,mrc-init-spd-addr1 = <0xa0>;
  238. fsp,mrc-init-spd-addr2 = <0xa2>;
  239. fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
  240. fsp,enable-sdio;
  241. fsp,enable-sdcard;
  242. fsp,enable-hsuart1;
  243. fsp,enable-spi;
  244. fsp,enable-sata;
  245. fsp,sata-mode = <SATA_MODE_AHCI>;
  246. #ifdef CONFIG_USB_XHCI_HCD
  247. fsp,enable-xhci;
  248. #endif
  249. fsp,lpe-mode = <LPE_MODE_PCI>;
  250. fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
  251. fsp,enable-dma0;
  252. fsp,enable-dma1;
  253. fsp,enable-i2c0;
  254. fsp,enable-i2c1;
  255. fsp,enable-i2c2;
  256. fsp,enable-i2c3;
  257. fsp,enable-i2c4;
  258. fsp,enable-i2c5;
  259. fsp,enable-i2c6;
  260. fsp,enable-pwm0;
  261. fsp,enable-pwm1;
  262. fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
  263. fsp,aperture-size = <APERTURE_SIZE_256MB>;
  264. fsp,gtt-size = <GTT_SIZE_2MB>;
  265. fsp,scc-mode = <SCC_MODE_PCI>;
  266. fsp,os-selection = <OS_SELECTION_LINUX>;
  267. fsp,emmc45-ddr50-enabled;
  268. fsp,emmc45-retune-timer-value = <8>;
  269. fsp,enable-igd;
  270. fsp,enable-memory-down;
  271. fsp,memory-down-params {
  272. compatible = "intel,baytrail-fsp-mdp";
  273. fsp,dram-speed = <DRAM_SPEED_1066MTS>;
  274. fsp,dram-type = <DRAM_TYPE_DDR3L>;
  275. fsp,dimm-0-enable;
  276. fsp,dimm-width = <DIMM_WIDTH_X16>;
  277. fsp,dimm-density = <DIMM_DENSITY_4GBIT>;
  278. fsp,dimm-bus-width = <DIMM_BUS_WIDTH_64BITS>;
  279. fsp,dimm-sides = <DIMM_SIDES_1RANKS>;
  280. fsp,dimm-tcl = <0xb>;
  281. fsp,dimm-trpt-rcd = <0xb>;
  282. fsp,dimm-twr = <0xc>;
  283. fsp,dimm-twtr = <6>;
  284. fsp,dimm-trrd = <6>;
  285. fsp,dimm-trtp = <6>;
  286. fsp,dimm-tfaw = <0x14>;
  287. };
  288. };
  289. microcode {
  290. update@0 {
  291. #include "microcode/m0130673325.dtsi"
  292. };
  293. update@1 {
  294. #include "microcode/m0130679907.dtsi"
  295. };
  296. };
  297. };