galileo.dts 4.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  4. */
  5. /dts-v1/;
  6. #include <dt-bindings/mrc/quark.h>
  7. #include <dt-bindings/interrupt-router/intel-irq.h>
  8. /include/ "skeleton.dtsi"
  9. /include/ "reset.dtsi"
  10. /include/ "rtc.dtsi"
  11. #include "tsc_timer.dtsi"
  12. / {
  13. model = "Intel Galileo";
  14. compatible = "intel,galileo", "intel,quark";
  15. aliases {
  16. spi0 = &spi;
  17. };
  18. config {
  19. silent_console = <0>;
  20. };
  21. chosen {
  22. stdout-path = &pciuart0;
  23. };
  24. cpus {
  25. #address-cells = <1>;
  26. #size-cells = <0>;
  27. cpu@0 {
  28. device_type = "cpu";
  29. compatible = "cpu-x86";
  30. reg = <0>;
  31. intel,apic-id = <0>;
  32. };
  33. };
  34. mrc {
  35. compatible = "intel,quark-mrc";
  36. flags = <MRC_FLAG_SCRAMBLE_EN>;
  37. dram-width = <DRAM_WIDTH_X8>;
  38. dram-speed = <DRAM_FREQ_800>;
  39. dram-type = <DRAM_TYPE_DDR3>;
  40. rank-mask = <DRAM_RANK(0)>;
  41. chan-mask = <DRAM_CHANNEL(0)>;
  42. chan-width = <DRAM_CHANNEL_WIDTH_X16>;
  43. addr-mode = <DRAM_ADDR_MODE0>;
  44. refresh-rate = <DRAM_REFRESH_RATE_785US>;
  45. sr-temp-range = <DRAM_SRT_RANGE_NORMAL>;
  46. ron-value = <DRAM_RON_34OHM>;
  47. rtt-nom-value = <DRAM_RTT_NOM_120OHM>;
  48. rd-odt-value = <DRAM_RD_ODT_OFF>;
  49. dram-density = <DRAM_DENSITY_1G>;
  50. dram-cl = <6>;
  51. dram-ras = <0x0000927c>;
  52. dram-wtr = <0x00002710>;
  53. dram-rrd = <0x00002710>;
  54. dram-faw = <0x00009c40>;
  55. };
  56. pci {
  57. #address-cells = <3>;
  58. #size-cells = <2>;
  59. compatible = "pci-x86";
  60. u-boot,dm-pre-reloc;
  61. ranges = <0x02000000 0x0 0x90000000 0x90000000 0 0x20000000
  62. 0x42000000 0x0 0xb0000000 0xb0000000 0 0x20000000
  63. 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  64. pciuart0: uart@14,5 {
  65. compatible = "pci8086,0936.00",
  66. "pci8086,0936",
  67. "pciclass,070002",
  68. "pciclass,0700",
  69. "ns16550";
  70. u-boot,dm-pre-reloc;
  71. reg = <0x0000a500 0x0 0x0 0x0 0x0
  72. 0x0200a510 0x0 0x0 0x0 0x0>;
  73. reg-shift = <2>;
  74. clock-frequency = <44236800>;
  75. current-speed = <115200>;
  76. };
  77. pch@1f,0 {
  78. reg = <0x0000f800 0 0 0 0>;
  79. compatible = "intel,pch7";
  80. #address-cells = <1>;
  81. #size-cells = <1>;
  82. irq-router {
  83. compatible = "intel,irq-router";
  84. intel,pirq-config = "pci";
  85. intel,actl-addr = <0x58>;
  86. intel,pirq-link = <0x60 8>;
  87. intel,pirq-mask = <0xdef8>;
  88. intel,pirq-routing = <
  89. PCI_BDF(0, 20, 0) INTA PIRQE
  90. PCI_BDF(0, 20, 1) INTB PIRQF
  91. PCI_BDF(0, 20, 2) INTC PIRQG
  92. PCI_BDF(0, 20, 3) INTD PIRQH
  93. PCI_BDF(0, 20, 4) INTA PIRQE
  94. PCI_BDF(0, 20, 5) INTB PIRQF
  95. PCI_BDF(0, 20, 6) INTC PIRQG
  96. PCI_BDF(0, 20, 7) INTD PIRQH
  97. PCI_BDF(0, 21, 0) INTA PIRQE
  98. PCI_BDF(0, 21, 1) INTB PIRQF
  99. PCI_BDF(0, 21, 2) INTC PIRQG
  100. PCI_BDF(0, 23, 0) INTA PIRQA
  101. PCI_BDF(0, 23, 1) INTB PIRQB
  102. /* PCIe root ports downstream interrupts */
  103. PCI_BDF(1, 0, 0) INTA PIRQA
  104. PCI_BDF(1, 0, 0) INTB PIRQB
  105. PCI_BDF(1, 0, 0) INTC PIRQC
  106. PCI_BDF(1, 0, 0) INTD PIRQD
  107. PCI_BDF(2, 0, 0) INTA PIRQB
  108. PCI_BDF(2, 0, 0) INTB PIRQC
  109. PCI_BDF(2, 0, 0) INTC PIRQD
  110. PCI_BDF(2, 0, 0) INTD PIRQA
  111. >;
  112. };
  113. spi: spi {
  114. #address-cells = <1>;
  115. #size-cells = <0>;
  116. compatible = "intel,ich7-spi";
  117. spi-flash@0 {
  118. #size-cells = <1>;
  119. #address-cells = <1>;
  120. reg = <0>;
  121. compatible = "winbond,w25q64",
  122. "jedec,spi-nor";
  123. memory-map = <0xff800000 0x00800000>;
  124. rw-mrc-cache {
  125. label = "rw-mrc-cache";
  126. reg = <0x00010000 0x00010000>;
  127. };
  128. };
  129. };
  130. gpioa {
  131. compatible = "intel,ich6-gpio";
  132. u-boot,dm-pre-reloc;
  133. reg = <0 0x20>;
  134. bank-name = "A";
  135. };
  136. gpiob {
  137. compatible = "intel,ich6-gpio";
  138. u-boot,dm-pre-reloc;
  139. reg = <0x20 0x20>;
  140. bank-name = "B";
  141. };
  142. };
  143. };
  144. smbios {
  145. compatible = "u-boot,sysinfo-smbios";
  146. /*
  147. * Override the default product name U-Boot reports in the
  148. * SMBIOS table, to be compatible with the Intel provided UEFI
  149. * BIOS, as Linux kernel drivers
  150. * (drivers/mfd/intel_quark_i2c_gpio.c and
  151. * drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of
  152. * it to do different board level configuration.
  153. *
  154. * This can be "Galileo" for GEN1 Galileo board.
  155. */
  156. smbios {
  157. system {
  158. product = "GalileoGen2";
  159. };
  160. baseboard {
  161. product = "GalileoGen2";
  162. };
  163. chassis {
  164. product = "GalileoGen2";
  165. };
  166. };
  167. };
  168. };