crownbay.dts 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
  4. */
  5. /dts-v1/;
  6. #include <dt-bindings/interrupt-router/intel-irq.h>
  7. /include/ "skeleton.dtsi"
  8. /include/ "serial.dtsi"
  9. /include/ "keyboard.dtsi"
  10. /include/ "pcspkr.dtsi"
  11. /include/ "reset.dtsi"
  12. /include/ "rtc.dtsi"
  13. #include "tsc_timer.dtsi"
  14. #include "smbios.dtsi"
  15. / {
  16. model = "Intel Crown Bay";
  17. compatible = "intel,crownbay", "intel,queensbay";
  18. aliases {
  19. spi0 = &spi;
  20. };
  21. config {
  22. silent_console = <0>;
  23. };
  24. cpus {
  25. #address-cells = <1>;
  26. #size-cells = <0>;
  27. cpu@0 {
  28. device_type = "cpu";
  29. compatible = "cpu-x86";
  30. reg = <0>;
  31. intel,apic-id = <0>;
  32. };
  33. cpu@1 {
  34. device_type = "cpu";
  35. compatible = "cpu-x86";
  36. reg = <1>;
  37. intel,apic-id = <1>;
  38. };
  39. };
  40. chosen {
  41. /*
  42. * By default the legacy superio serial port is used as the
  43. * U-Boot serial console. If we want to use UART from Topcliff
  44. * PCH as the console, change this property to &pciuart#.
  45. *
  46. * For example, stdout-path = &pciuart0 will use the first
  47. * UART on Topcliff PCH.
  48. */
  49. stdout-path = "/serial";
  50. };
  51. microcode {
  52. update@0 {
  53. #include "microcode/m0220661105_cv.dtsi"
  54. };
  55. };
  56. pci {
  57. #address-cells = <3>;
  58. #size-cells = <2>;
  59. compatible = "pci-x86";
  60. u-boot,dm-pre-reloc;
  61. ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000
  62. 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
  63. 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  64. pcie@17,0 {
  65. #address-cells = <3>;
  66. #size-cells = <2>;
  67. compatible = "pci-bridge";
  68. u-boot,dm-pre-reloc;
  69. reg = <0x0000b800 0x0 0x0 0x0 0x0>;
  70. topcliff@0,0 {
  71. #address-cells = <3>;
  72. #size-cells = <2>;
  73. compatible = "pci-bridge";
  74. u-boot,dm-pre-reloc;
  75. reg = <0x00010000 0x0 0x0 0x0 0x0>;
  76. pciuart0: uart@a,1 {
  77. compatible = "pci8086,8811.00",
  78. "pci8086,8811",
  79. "pciclass,070002",
  80. "pciclass,0700",
  81. "ns16550";
  82. u-boot,dm-pre-reloc;
  83. reg = <0x00025100 0x0 0x0 0x0 0x0
  84. 0x01025110 0x0 0x0 0x0 0x0>;
  85. reg-shift = <0>;
  86. clock-frequency = <1843200>;
  87. current-speed = <115200>;
  88. };
  89. pciuart1: uart@a,2 {
  90. compatible = "pci8086,8812.00",
  91. "pci8086,8812",
  92. "pciclass,070002",
  93. "pciclass,0700",
  94. "ns16550";
  95. u-boot,dm-pre-reloc;
  96. reg = <0x00025200 0x0 0x0 0x0 0x0
  97. 0x01025210 0x0 0x0 0x0 0x0>;
  98. reg-shift = <0>;
  99. clock-frequency = <1843200>;
  100. current-speed = <115200>;
  101. };
  102. pciuart2: uart@a,3 {
  103. compatible = "pci8086,8813.00",
  104. "pci8086,8813",
  105. "pciclass,070002",
  106. "pciclass,0700",
  107. "ns16550";
  108. u-boot,dm-pre-reloc;
  109. reg = <0x00025300 0x0 0x0 0x0 0x0
  110. 0x01025310 0x0 0x0 0x0 0x0>;
  111. reg-shift = <0>;
  112. clock-frequency = <1843200>;
  113. current-speed = <115200>;
  114. };
  115. pciuart3: uart@a,4 {
  116. compatible = "pci8086,8814.00",
  117. "pci8086,8814",
  118. "pciclass,070002",
  119. "pciclass,0700",
  120. "ns16550";
  121. u-boot,dm-pre-reloc;
  122. reg = <0x00025400 0x0 0x0 0x0 0x0
  123. 0x01025410 0x0 0x0 0x0 0x0>;
  124. reg-shift = <0>;
  125. clock-frequency = <1843200>;
  126. current-speed = <115200>;
  127. };
  128. };
  129. };
  130. pch@1f,0 {
  131. reg = <0x0000f800 0 0 0 0>;
  132. compatible = "intel,pch7";
  133. #address-cells = <1>;
  134. #size-cells = <1>;
  135. irq-router {
  136. compatible = "intel,irq-router";
  137. intel,pirq-config = "pci";
  138. intel,actl-addr = <0x58>;
  139. intel,pirq-link = <0x60 8>;
  140. intel,pirq-mask = <0xcee0>;
  141. intel,pirq-routing = <
  142. /* TunnelCreek PCI devices */
  143. PCI_BDF(0, 2, 0) INTA PIRQE
  144. PCI_BDF(0, 3, 0) INTA PIRQF
  145. PCI_BDF(0, 23, 0) INTA PIRQA
  146. PCI_BDF(0, 23, 0) INTB PIRQB
  147. PCI_BDF(0, 23, 0) INTC PIRQC
  148. PCI_BDF(0, 23, 0) INTD PIRQD
  149. PCI_BDF(0, 24, 0) INTA PIRQB
  150. PCI_BDF(0, 24, 0) INTB PIRQC
  151. PCI_BDF(0, 24, 0) INTC PIRQD
  152. PCI_BDF(0, 24, 0) INTD PIRQA
  153. PCI_BDF(0, 25, 0) INTA PIRQC
  154. PCI_BDF(0, 25, 0) INTB PIRQD
  155. PCI_BDF(0, 25, 0) INTC PIRQA
  156. PCI_BDF(0, 25, 0) INTD PIRQB
  157. PCI_BDF(0, 26, 0) INTA PIRQD
  158. PCI_BDF(0, 26, 0) INTB PIRQA
  159. PCI_BDF(0, 26, 0) INTC PIRQB
  160. PCI_BDF(0, 26, 0) INTD PIRQC
  161. PCI_BDF(0, 27, 0) INTA PIRQG
  162. /*
  163. * Topcliff PCI devices
  164. *
  165. * Note on the Crown Bay board, Topcliff
  166. * chipset is connected to TunnelCreek
  167. * PCIe port 0, so its bus number is 1
  168. * for its PCIe port and 2 for its PCI
  169. * devices per U-Boot current PCI bus
  170. * enumeration algorithm.
  171. */
  172. PCI_BDF(1, 0, 0) INTA PIRQA
  173. PCI_BDF(2, 0, 1) INTA PIRQA
  174. PCI_BDF(2, 0, 2) INTA PIRQA
  175. PCI_BDF(2, 2, 0) INTB PIRQD
  176. PCI_BDF(2, 2, 1) INTB PIRQD
  177. PCI_BDF(2, 2, 2) INTB PIRQD
  178. PCI_BDF(2, 2, 3) INTB PIRQD
  179. PCI_BDF(2, 2, 4) INTB PIRQD
  180. PCI_BDF(2, 4, 0) INTC PIRQC
  181. PCI_BDF(2, 4, 1) INTC PIRQC
  182. PCI_BDF(2, 6, 0) INTD PIRQB
  183. PCI_BDF(2, 8, 0) INTA PIRQA
  184. PCI_BDF(2, 8, 1) INTA PIRQA
  185. PCI_BDF(2, 8, 2) INTA PIRQA
  186. PCI_BDF(2, 8, 3) INTA PIRQA
  187. PCI_BDF(2, 10, 0) INTB PIRQD
  188. PCI_BDF(2, 10, 1) INTB PIRQD
  189. PCI_BDF(2, 10, 2) INTB PIRQD
  190. PCI_BDF(2, 10, 3) INTB PIRQD
  191. PCI_BDF(2, 10, 4) INTB PIRQD
  192. PCI_BDF(2, 12, 0) INTC PIRQC
  193. PCI_BDF(2, 12, 1) INTC PIRQC
  194. PCI_BDF(2, 12, 2) INTC PIRQC
  195. PCI_BDF(2, 12, 3) INTC PIRQC
  196. PCI_BDF(2, 12, 4) INTC PIRQC
  197. >;
  198. };
  199. spi: spi {
  200. #address-cells = <1>;
  201. #size-cells = <0>;
  202. compatible = "intel,ich7-spi";
  203. spi-flash@0 {
  204. reg = <0>;
  205. compatible = "sst,25vf016b",
  206. "jedec,spi-nor";
  207. memory-map = <0xffe00000 0x00200000>;
  208. };
  209. };
  210. gpioa {
  211. compatible = "intel,ich6-gpio";
  212. u-boot,dm-pre-reloc;
  213. reg = <0 0x20>;
  214. bank-name = "A";
  215. };
  216. gpiob {
  217. compatible = "intel,ich6-gpio";
  218. u-boot,dm-pre-reloc;
  219. reg = <0x20 0x20>;
  220. bank-name = "B";
  221. };
  222. };
  223. };
  224. };