cougarcanyon2.dts 3.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
  4. */
  5. /dts-v1/;
  6. #include <dt-bindings/interrupt-router/intel-irq.h>
  7. /include/ "skeleton.dtsi"
  8. /include/ "serial.dtsi"
  9. /include/ "keyboard.dtsi"
  10. /include/ "reset.dtsi"
  11. /include/ "rtc.dtsi"
  12. #include "tsc_timer.dtsi"
  13. #include "smbios.dtsi"
  14. / {
  15. model = "Intel Cougar Canyon 2";
  16. compatible = "intel,cougarcanyon2", "intel,chiefriver";
  17. aliases {
  18. spi0 = &spi0;
  19. };
  20. config {
  21. silent_console = <0>;
  22. };
  23. chosen {
  24. stdout-path = "/serial";
  25. };
  26. cpus {
  27. #address-cells = <1>;
  28. #size-cells = <0>;
  29. cpu@0 {
  30. device_type = "cpu";
  31. compatible = "intel,core-gen3";
  32. reg = <0>;
  33. intel,apic-id = <0>;
  34. };
  35. cpu@1 {
  36. device_type = "cpu";
  37. compatible = "intel,core-gen3";
  38. reg = <1>;
  39. intel,apic-id = <1>;
  40. };
  41. cpu@2 {
  42. device_type = "cpu";
  43. compatible = "intel,core-gen3";
  44. reg = <2>;
  45. intel,apic-id = <2>;
  46. };
  47. cpu@3 {
  48. device_type = "cpu";
  49. compatible = "intel,core-gen3";
  50. reg = <3>;
  51. intel,apic-id = <3>;
  52. };
  53. };
  54. microcode {
  55. update@0 {
  56. #include "microcode/m12306a2_00000008.dtsi"
  57. };
  58. update@1 {
  59. #include "microcode/m12306a4_00000007.dtsi"
  60. };
  61. update@2 {
  62. #include "microcode/m12306a5_00000007.dtsi"
  63. };
  64. update@3 {
  65. #include "microcode/m12306a8_00000010.dtsi"
  66. };
  67. update@4 {
  68. #include "microcode/m12306a9_0000001b.dtsi"
  69. };
  70. };
  71. fsp {
  72. compatible = "intel,ivybridge-fsp";
  73. fsp,enable-ht;
  74. };
  75. pci {
  76. #address-cells = <3>;
  77. #size-cells = <2>;
  78. compatible = "pci-x86";
  79. u-boot,dm-pre-reloc;
  80. ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
  81. 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
  82. 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  83. pch@1f,0 {
  84. reg = <0x0000f800 0 0 0 0>;
  85. compatible = "intel,bd82x6x";
  86. u-boot,dm-pre-reloc;
  87. #address-cells = <1>;
  88. #size-cells = <1>;
  89. irq-router {
  90. compatible = "intel,irq-router";
  91. intel,pirq-config = "pci";
  92. intel,actl-8bit;
  93. intel,actl-addr = <0x44>;
  94. intel,pirq-link = <0x60 8>;
  95. intel,pirq-regmap = <
  96. PIRQA 0
  97. PIRQB 1
  98. PIRQC 2
  99. PIRQD 3
  100. PIRQE 8
  101. PIRQF 9
  102. PIRQG 10
  103. PIRQH 11
  104. >;
  105. intel,pirq-mask = <0xcee0>;
  106. intel,pirq-routing = <
  107. /* Panther Point PCI devices */
  108. PCI_BDF(0, 2, 0) INTA PIRQA
  109. PCI_BDF(0, 20, 0) INTA PIRQA
  110. PCI_BDF(0, 22, 0) INTA PIRQA
  111. PCI_BDF(0, 22, 1) INTB PIRQB
  112. PCI_BDF(0, 22, 2) INTC PIRQC
  113. PCI_BDF(0, 22, 3) INTD PIRQD
  114. PCI_BDF(0, 25, 0) INTA PIRQA
  115. PCI_BDF(0, 26, 0) INTA PIRQA
  116. PCI_BDF(0, 27, 0) INTB PIRQA
  117. PCI_BDF(0, 28, 0) INTA PIRQA
  118. PCI_BDF(0, 28, 1) INTB PIRQB
  119. PCI_BDF(0, 28, 2) INTC PIRQC
  120. PCI_BDF(0, 28, 3) INTD PIRQD
  121. PCI_BDF(0, 28, 4) INTA PIRQA
  122. PCI_BDF(0, 28, 5) INTB PIRQB
  123. PCI_BDF(0, 28, 6) INTC PIRQC
  124. PCI_BDF(0, 28, 7) INTD PIRQD
  125. PCI_BDF(0, 29, 0) INTA PIRQA
  126. PCI_BDF(0, 31, 2) INTB PIRQB
  127. PCI_BDF(0, 31, 3) INTC PIRQC
  128. PCI_BDF(0, 31, 5) INTB PIRQB
  129. PCI_BDF(0, 31, 6) INTC PIRQC
  130. >;
  131. };
  132. spi0: spi {
  133. #address-cells = <1>;
  134. #size-cells = <0>;
  135. compatible = "intel,ich9-spi";
  136. intel,spi-lock-down;
  137. spi-flash@0 {
  138. reg = <0>;
  139. m25p,fast-read;
  140. compatible = "winbond,w25q64bv", "jedec,spi-nor";
  141. memory-map = <0xff800000 0x00800000>;
  142. };
  143. };
  144. gpioa {
  145. compatible = "intel,ich6-gpio";
  146. u-boot,dm-pre-reloc;
  147. reg = <0 0x10>;
  148. bank-name = "A";
  149. };
  150. gpiob {
  151. compatible = "intel,ich6-gpio";
  152. u-boot,dm-pre-reloc;
  153. reg = <0x30 0x10>;
  154. bank-name = "B";
  155. };
  156. gpioc {
  157. compatible = "intel,ich6-gpio";
  158. u-boot,dm-pre-reloc;
  159. reg = <0x40 0x10>;
  160. bank-name = "C";
  161. };
  162. };
  163. };
  164. };