chromebox_panther.dts 1.6 KB

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  1. /dts-v1/;
  2. /include/ "skeleton.dtsi"
  3. /include/ "serial.dtsi"
  4. /include/ "reset.dtsi"
  5. /include/ "rtc.dtsi"
  6. #include "tsc_timer.dtsi"
  7. #include "smbios.dtsi"
  8. / {
  9. model = "Google Panther";
  10. compatible = "google,panther", "intel,haswell";
  11. aliases {
  12. spi0 = &spi;
  13. };
  14. config {
  15. silent-console = <0>;
  16. no-keyboard;
  17. };
  18. chosen {
  19. stdout-path = "/serial";
  20. };
  21. pci {
  22. compatible = "pci-x86";
  23. #address-cells = <3>;
  24. #size-cells = <2>;
  25. u-boot,dm-pre-reloc;
  26. ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
  27. 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
  28. 0x01000000 0x0 0x1000 0x1000 0 0xf000>;
  29. pch@1f,0 {
  30. reg = <0x0000f800 0 0 0 0>;
  31. compatible = "intel,pch9";
  32. #address-cells = <1>;
  33. #size-cells = <1>;
  34. spi: spi {
  35. #address-cells = <1>;
  36. #size-cells = <0>;
  37. compatible = "intel,ich9-spi";
  38. spi-flash@0 {
  39. #size-cells = <1>;
  40. #address-cells = <1>;
  41. reg = <0>;
  42. m25p,fast-read;
  43. compatible = "winbond,w25q64",
  44. "jedec,spi-nor";
  45. memory-map = <0xff800000 0x00800000>;
  46. rw-mrc-cache {
  47. label = "rw-mrc-cache";
  48. reg = <0x003e0000 0x00010000>;
  49. };
  50. };
  51. };
  52. gpioa {
  53. compatible = "intel,ich6-gpio";
  54. u-boot,dm-pre-reloc;
  55. reg = <0 0x10>;
  56. bank-name = "A";
  57. };
  58. gpiob {
  59. compatible = "intel,ich6-gpio";
  60. u-boot,dm-pre-reloc;
  61. reg = <0x30 0x10>;
  62. bank-name = "B";
  63. };
  64. gpioc {
  65. compatible = "intel,ich6-gpio";
  66. u-boot,dm-pre-reloc;
  67. reg = <0x40 0x10>;
  68. bank-name = "C";
  69. };
  70. };
  71. };
  72. tpm {
  73. reg = <0xfed40000 0x5000>;
  74. compatible = "infineon,slb9635lpc";
  75. };
  76. };