chromebook_coral.dts 39 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /dts-v1/;
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include <dt-bindings/gpio/x86-gpio.h>
  5. /include/ "skeleton.dtsi"
  6. /include/ "keyboard.dtsi"
  7. /include/ "reset.dtsi"
  8. /include/ "rtc.dtsi"
  9. #include "tsc_timer.dtsi"
  10. #if defined(CONFIG_CHROMEOS_VBOOT) && defined(CONFIG_ROM_SIZE)
  11. #include "chromeos-x86.dtsi"
  12. #include "flashmap-x86-ro.dtsi"
  13. #include "flashmap-16mb-rw.dtsi"
  14. #endif
  15. #include <dt-bindings/clock/intel-clock.h>
  16. #include <dt-bindings/interrupt-controller/irq.h>
  17. #include <dt-bindings/interrupt-controller/x86-irq.h>
  18. #include <asm/e820.h>
  19. #include <asm/intel_pinctrl_defs.h>
  20. #include <asm/arch-apollolake/cpu.h>
  21. #include <asm/arch-apollolake/gpe.h>
  22. #include <asm/arch-apollolake/gpio.h>
  23. #include <asm/arch-apollolake/iomap.h>
  24. #include <asm/arch-apollolake/pm.h>
  25. #include <dt-bindings/clock/intel-clock.h>
  26. #include <asm/arch-apollolake/fsp/fsp_m_upd.h>
  27. #include <asm/arch-apollolake/fsp/fsp_s_upd.h>
  28. #include <dt-bindings/sound/nhlt.h>
  29. / {
  30. model = "Google Coral";
  31. compatible = "google,coral", "intel,apollolake";
  32. aliases {
  33. cros-ec0 = &cros_ec;
  34. fsp = &fsp_s;
  35. spi0 = &spi;
  36. i2c0 = &i2c_0;
  37. i2c1 = &i2c_1;
  38. i2c2 = &i2c_2;
  39. i2c3 = &i2c_3;
  40. i2c4 = &i2c_4;
  41. i2c5 = &i2c_5;
  42. i2c6 = &i2c_6;
  43. i2c7 = &i2c_7;
  44. mmc0 = &emmc;
  45. mmc1 = &sdmmc;
  46. };
  47. board: board {
  48. compatible = "google,coral";
  49. recovery-gpios = <&gpio_nw (-1) GPIO_ACTIVE_LOW>;
  50. write-protect-gpios = <&gpio_nw GPIO_75 GPIO_ACTIVE_HIGH>;
  51. phase-enforce-gpios = <&gpio_n GPIO_10 GPIO_ACTIVE_HIGH>;
  52. memconfig-gpios = <&gpio_nw GPIO_101 GPIO_ACTIVE_HIGH
  53. &gpio_nw GPIO_102 GPIO_ACTIVE_HIGH
  54. &gpio_n GPIO_38 GPIO_ACTIVE_HIGH
  55. &gpio_n GPIO_45 GPIO_ACTIVE_HIGH>;
  56. /*
  57. * This is used for reef only:
  58. *
  59. * skuconfig-gpios = <&gpio_nw GPIO_16 GPIO_ACTIVE_HIGH
  60. * &gpio_nw GPIO_17 GPIO_ACTIVE_HIGH>;
  61. */
  62. smbios {
  63. /* Type 1 table */
  64. system {
  65. manufacturer = "Google";
  66. product = "Coral";
  67. version = "rev2";
  68. serial = "123456789";
  69. sku = "sku3";
  70. family = "Google_Coral";
  71. };
  72. /* Type 2 table */
  73. baseboard {
  74. manufacturer = "Google";
  75. product = "Coral";
  76. asset-tag = "ABC123";
  77. };
  78. /* Type 3 table */
  79. chassis {
  80. manufacturer = "Google";
  81. };
  82. };
  83. };
  84. config {
  85. silent_console = <0>;
  86. };
  87. chosen {
  88. stdout-path = &serial;
  89. e820-entries = /bits/ 64 <
  90. IOMAP_P2SB_BAR IOMAP_P2SB_SIZE E820_RESERVED
  91. MCH_BASE_ADDRESS MCH_SIZE E820_RESERVED>;
  92. u-boot,acpi-ssdt-order = <&cpu_0 &cpu_1 &cpu_2 &cpu_3
  93. &i2c_0 &i2c_1 &i2c_2 &i2c_3 &i2c_4 &i2c_5
  94. &sdmmc &maxim_codec &wifi &da_codec &tpm
  95. &elan_touchscreen &raydium_touchscreen
  96. &elan_touchpad &synaptics_touchpad &wacom_digitizer>;
  97. u-boot,acpi-dsdt-order = <&board &lpc>;
  98. };
  99. clk: clock {
  100. compatible = "intel,apl-clk";
  101. #clock-cells = <1>;
  102. u-boot,dm-pre-proper;
  103. };
  104. cpus {
  105. u-boot,dm-pre-proper;
  106. #address-cells = <1>;
  107. #size-cells = <0>;
  108. cpu_0: cpu@0 {
  109. u-boot,dm-pre-proper;
  110. u-boot,dm-spl;
  111. device_type = "cpu";
  112. compatible = "intel,apl-cpu";
  113. reg = <0>;
  114. intel,apic-id = <0>;
  115. };
  116. cpu_1: cpu@1 {
  117. device_type = "cpu";
  118. compatible = "intel,apl-cpu";
  119. reg = <1>;
  120. intel,apic-id = <2>;
  121. };
  122. cpu_2: cpu@2 {
  123. device_type = "cpu";
  124. compatible = "intel,apl-cpu";
  125. reg = <2>;
  126. intel,apic-id = <4>;
  127. };
  128. cpu_3: cpu@3 {
  129. device_type = "cpu";
  130. compatible = "intel,apl-cpu";
  131. reg = <3>;
  132. intel,apic-id = <6>;
  133. };
  134. };
  135. acpi_gpe: general-purpose-events {
  136. u-boot,dm-pre-proper;
  137. reg = <IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
  138. compatible = "intel,acpi-gpe";
  139. interrupt-controller;
  140. #interrupt-cells = <2>;
  141. };
  142. coreboot-video {
  143. /* This will only activate when booted from coreboot */
  144. compatible = "coreboot-fb";
  145. };
  146. keyboard {
  147. intel,duplicate-por;
  148. };
  149. pci {
  150. compatible = "pci-x86";
  151. #address-cells = <3>;
  152. #size-cells = <2>;
  153. u-boot,dm-pre-reloc;
  154. ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
  155. 0x42000000 0x0 0xb0000000 0xb0000000 0 0x10000000
  156. 0x01000000 0x0 0x1000 0x1000 0 0xefff>;
  157. u-boot,skip-auto-config-until-reloc;
  158. host_bridge: host-bridge@0,0 {
  159. u-boot,dm-pre-reloc;
  160. reg = <0x00000000 0 0 0 0>;
  161. compatible = "intel,apl-hostbridge";
  162. pciex-region-size = <0x10000000>;
  163. fspm,training-delay = <21>;
  164. /*
  165. * Parameters used by the FSP-S binary blob. This is
  166. * really unfortunate since these parameters mostly
  167. * relate to drivers but we need them in one place. We
  168. * could put them in the driver nodes easily, but then
  169. * would have to scan each node to find them. So just
  170. * dump them here for now.
  171. */
  172. fsp_s: fsp-s {
  173. };
  174. fsp_m: fsp-m {
  175. u-boot,dm-spl;
  176. };
  177. nhlt {
  178. intel,dmic-channels = <4>;
  179. };
  180. };
  181. punit@0,1 {
  182. u-boot,dm-pre-proper;
  183. u-boot,dm-spl;
  184. reg = <0x00000800 0 0 0 0>;
  185. compatible = "intel,apl-punit";
  186. };
  187. gma@2,0 {
  188. u-boot,dm-pre-proper;
  189. reg = <0x00001000 0 0 0 0>;
  190. compatible = "fsp-fb";
  191. };
  192. p2sb: p2sb@d,0 {
  193. u-boot,dm-pre-reloc;
  194. reg = <0x02006810 0 0 0 0>;
  195. compatible = "intel,p2sb";
  196. early-regs = <IOMAP_P2SB_BAR 0x100000>;
  197. pci,no-autoconfig;
  198. n {
  199. compatible = "intel,apl-pinctrl";
  200. u-boot,dm-pre-reloc;
  201. intel,p2sb-port-id = <PID_GPIO_N>;
  202. acpi,path = "\\_SB.GPO0";
  203. gpio_n: gpio-n {
  204. compatible = "intel,gpio";
  205. u-boot,dm-pre-reloc;
  206. gpio-controller;
  207. #gpio-cells = <2>;
  208. linux-name = "INT3452:00";
  209. };
  210. };
  211. nw {
  212. u-boot,dm-pre-reloc;
  213. compatible = "intel,apl-pinctrl";
  214. intel,p2sb-port-id = <PID_GPIO_NW>;
  215. #gpio-cells = <2>;
  216. acpi,path = "\\_SB.GPO1";
  217. gpio_nw: gpio-nw {
  218. compatible = "intel,gpio";
  219. u-boot,dm-pre-reloc;
  220. gpio-controller;
  221. #gpio-cells = <2>;
  222. linux-name = "INT3452:01";
  223. };
  224. };
  225. w {
  226. u-boot,dm-pre-reloc;
  227. compatible = "intel,apl-pinctrl";
  228. intel,p2sb-port-id = <PID_GPIO_W>;
  229. #gpio-cells = <2>;
  230. acpi,path = "\\_SB.GPO2";
  231. gpio_w: gpio-w {
  232. compatible = "intel,gpio";
  233. u-boot,dm-pre-reloc;
  234. gpio-controller;
  235. #gpio-cells = <2>;
  236. linux-name = "INT3452:02";
  237. };
  238. };
  239. sw {
  240. u-boot,dm-pre-reloc;
  241. compatible = "intel,apl-pinctrl";
  242. intel,p2sb-port-id = <PID_GPIO_SW>;
  243. #gpio-cells = <2>;
  244. acpi,path = "\\_SB.GPO3";
  245. gpio_sw: gpio-sw {
  246. compatible = "intel,gpio";
  247. u-boot,dm-pre-reloc;
  248. gpio-controller;
  249. #gpio-cells = <2>;
  250. linux-name = "INT3452:03";
  251. };
  252. };
  253. itss {
  254. u-boot,dm-pre-reloc;
  255. compatible = "intel,itss";
  256. intel,p2sb-port-id = <PID_ITSS>;
  257. intel,pmc-routes = <
  258. PMC_GPE_SW_31_0 GPIO_GPE_SW_31_0
  259. PMC_GPE_SW_63_32 GPIO_GPE_SW_63_32
  260. PMC_GPE_NW_31_0 GPIO_GPE_NW_31_0
  261. PMC_GPE_NW_63_32 GPIO_GPE_NW_63_32
  262. PMC_GPE_NW_95_64 GPIO_GPE_NW_95_64
  263. PMC_GPE_N_31_0 GPIO_GPE_N_31_0
  264. PMC_GPE_N_63_32 GPIO_GPE_N_63_32
  265. PMC_GPE_W_31_0 GPIO_GPE_W_31_0>;
  266. };
  267. };
  268. pmc@d,1 {
  269. u-boot,dm-pre-reloc;
  270. reg = <0x6900 0 0 0 0>;
  271. /*
  272. * Values for BAR0, BAR2 and ACPI_BASE for when PCI
  273. * auto-configure is not available
  274. */
  275. early-regs = <0xfe042000 0x2000
  276. 0xfe044000 0x2000
  277. IOMAP_ACPI_BASE IOMAP_ACPI_SIZE>;
  278. compatible = "intel,apl-pmc";
  279. gpe0-dwx-mask = <0xf>;
  280. gpe0-dwx-shift-base = <4>;
  281. /*
  282. * GPE configuration
  283. * Note that GPE events called out in ASL code rely on
  284. * this route, i.e., if this route changes then the
  285. * affected GPE * offset bits also need to be changed.
  286. * This sets the PMC register GPE_CFG fields.
  287. */
  288. gpe0-dw = <PMC_GPE_N_31_0
  289. PMC_GPE_N_63_32
  290. PMC_GPE_SW_31_0>;
  291. gpe0-sts = <0x20>;
  292. gpe0-en = <0x30>;
  293. };
  294. audio@e,0 {
  295. reg = <0x7000 0 0 0 0>;
  296. compatible = "simple-bus";
  297. acpi,name = "HDAS";
  298. i2s {
  299. compatible = "fred";
  300. };
  301. maxim_codec: maxim-codec {
  302. compatible = "maxim,max98357a";
  303. acpi,ddn = "Maxim Integrated 98357A Amplifier";
  304. sdmode-gpios = <&gpio_n GPIO_76 GPIO_ACTIVE_HIGH>;
  305. sdmode-delay = <5>;
  306. acpi,name = "MAXM";
  307. acpi,hid = "MX98357A";
  308. acpi,audio-link = <AUDIO_LINK_SSP5>;
  309. };
  310. };
  311. spi: fast-spi@d,2 {
  312. u-boot,dm-pre-proper;
  313. u-boot,dm-spl;
  314. reg = <0x02006a10 0 0 0 0>;
  315. #address-cells = <1>;
  316. #size-cells = <0>;
  317. compatible = "intel,fast-spi";
  318. early-regs = <IOMAP_SPI_BASE 0x1000>;
  319. intel,hardware-seq = <1>;
  320. fwstore_spi: spi-flash@0 {
  321. #size-cells = <1>;
  322. #address-cells = <1>;
  323. u-boot,dm-pre-proper;
  324. u-boot,dm-spl;
  325. reg = <0>;
  326. m25p,fast-read;
  327. compatible = "winbond,w25q128fw",
  328. "jedec,spi-nor";
  329. rw-mrc-cache {
  330. label = "rw-mrc-cache";
  331. reg = <0x008e0000 0x00010000>;
  332. u-boot,dm-pre-reloc;
  333. };
  334. rw-var-mrc-cache {
  335. label = "rw-mrc-cache";
  336. reg = <0x008f0000 0x0001000>;
  337. u-boot,dm-pre-reloc;
  338. };
  339. };
  340. };
  341. /* WiFi */
  342. pcie-a0@14,0 {
  343. reg = <0x0000a000 0 0 0 0>;
  344. acpi,name = "RP01";
  345. wifi: wifi {
  346. compatible = "intel,generic-wifi";
  347. acpi,ddn = "Intel WiFi";
  348. acpi,name = "WF00";
  349. acpi,wake = <GPE0_DW3_00>;
  350. interrupts-extended = <&acpi_gpe 0x3c 0>;
  351. };
  352. };
  353. i2c_0: i2c2@16,0 {
  354. compatible = "intel,apl-i2c";
  355. reg = <0x0200b010 0 0 0 0>;
  356. clocks = <&clk CLK_I2C>;
  357. i2c-scl-rising-time-ns = <104>;
  358. i2c-scl-falling-time-ns = <52>;
  359. clock-frequency = <400000>;
  360. i2c,speeds = <100000 400000 1000000>;
  361. #address-cells = <1>;
  362. #size-cells = <0>;
  363. da_codec: da-codec {
  364. reg = <0x1a>;
  365. compatible = "dlg,da7219";
  366. interrupts-extended = <&acpi_gpe GPIO_116_IRQ
  367. (IRQ_TYPE_LEVEL_LOW | X86_IRQ_TYPE_SHARED)>;
  368. acpi,name = "DLG7";
  369. acpi,ddn = "Dialog Semiconductor DA7219 Audio Codec";
  370. acpi,audio-link = <AUDIO_LINK_SSP1>;
  371. dlg,micbias-lvl = <2600>;
  372. dlg,mic-amp-in-sel = "diff";
  373. da7219_aad {
  374. dlg,btn-cfg = <50>;
  375. dlg,mic-det-thr = <500>;
  376. dlg,jack-ins-deb = <20>;
  377. dlg,jack-det-rate = "32ms_64ms";
  378. dlg,jack-rem-deb = <1>;
  379. dlg,a-d-btn-thr = <0xa>;
  380. dlg,d-b-btn-thr = <0x16>;
  381. dlg,b-c-btn-thr = <0x21>;
  382. dlg,c-mic-btn-thr = <0x3e>;
  383. dlg,btn-avg = <4>;
  384. dlg,adc-1bit-rpt = <1>;
  385. };
  386. };
  387. };
  388. i2c_1: i2c2@16,1 {
  389. compatible = "intel,apl-i2c";
  390. reg = <0x0200b110 0 0 0 0>;
  391. clocks = <&clk CLK_I2C>;
  392. clock-frequency = <400000>;
  393. i2c,speeds = <100000 400000 1000000 3400000>;
  394. i2c-scl-rising-time-ns = <52>;
  395. i2c-scl-falling-time-ns = <52>;
  396. };
  397. i2c_2: i2c2@16,2 {
  398. compatible = "intel,apl-i2c", "snps,designware-i2c-pci";
  399. reg = <0x0200b210 0 0 0 0>;
  400. early-regs = <IOMAP_I2C2_BASE 0x1000>;
  401. u-boot,dm-pre-proper;
  402. #address-cells = <1>;
  403. #size-cells = <0>;
  404. clock-frequency = <400000>;
  405. i2c,speeds = <100000 400000 1000000>;
  406. clocks = <&clk CLK_I2C>;
  407. i2c-scl-rising-time-ns = <57>;
  408. i2c-scl-falling-time-ns = <28>;
  409. tpm: tpm@50 {
  410. reg = <0x50>;
  411. compatible = "google,cr50";
  412. u-boot,dm-pre-proper;
  413. u-boot,i2c-offset-len = <0>;
  414. ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>;
  415. interrupts-extended = <&acpi_gpe GPIO_28_IRQ
  416. IRQ_TYPE_EDGE_FALLING>;
  417. acpi,hid = "GOOG0005";
  418. acpi,ddn = "I2C TPM";
  419. acpi,name = "TPMI";
  420. };
  421. };
  422. i2c_3: i2c2@16,3 {
  423. compatible = "intel,apl-i2c";
  424. reg = <0x0200b310 0 0 0 0>;
  425. #address-cells = <1>;
  426. #size-cells = <0>;
  427. clocks = <&clk CLK_I2C>;
  428. i2c-scl-rising-time-ns = <76>;
  429. i2c-scl-falling-time-ns = <164>;
  430. clock-frequency = <400000>;
  431. i2c,speeds = <100000 400000>;
  432. elan_touchscreen: elan-touchscreen@10 {
  433. compatible = "i2c-chip";
  434. reg = <0x10>;
  435. acpi,hid = "ELAN0001";
  436. acpi,ddn = "ELAN Touchscreen";
  437. interrupts-extended = <&acpi_gpe GPIO_21_IRQ
  438. IRQ_TYPE_EDGE_FALLING>;
  439. linux,probed;
  440. reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>;
  441. reset-delay-ms = <20>;
  442. enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>;
  443. enable-delay-ms = <1>;
  444. acpi,has-power-resource;
  445. };
  446. raydium_touchscreen: raydium-touchscreen@39 {
  447. compatible = "i2c-chip";
  448. reg = <0x39>;
  449. acpi,hid = "RAYD0001";
  450. acpi,ddn = "Raydium Touchscreen";
  451. interrupts-extended = <&acpi_gpe GPIO_21_IRQ
  452. IRQ_TYPE_EDGE_FALLING>;
  453. linux,probed;
  454. reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>;
  455. reset-delay-ms = <1>;
  456. enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>;
  457. enable-delay-ms = <50>;
  458. acpi,has-power-resource;
  459. };
  460. };
  461. i2c_4: i2c2@17,0 {
  462. compatible = "intel,apl-i2c";
  463. reg = <0x0200b810 0 0 0 0>;
  464. #address-cells = <1>;
  465. #size-cells = <0>;
  466. clocks = <&clk CLK_I2C>;
  467. i2c-sda-hold-time-ns = <350>;
  468. i2c-scl-rising-time-ns = <114>;
  469. i2c-scl-falling-time-ns = <164>;
  470. clock-frequency = <400000>;
  471. i2c,speeds = <100000 400000>;
  472. elan_touchpad: elan-touchpad@15 {
  473. compatible = "i2c-chip";
  474. reg = <0x15>;
  475. u-boot,i2c-offset-len = <0>;
  476. acpi,hid = "ELAN0000";
  477. acpi,ddn = "ELAN Touchpad";
  478. interrupts-extended = <&acpi_gpe GPIO_18_IRQ
  479. IRQ_TYPE_EDGE_FALLING>;
  480. acpi,wake = <GPE0_DW1_15>;
  481. linux,probed;
  482. };
  483. synaptics_touchpad: synaptics-touchpad@2c {
  484. compatible = "hid-over-i2c";
  485. reg = <0x2c>;
  486. acpi,hid = "PNP0C50";
  487. acpi,ddn = "Synaptics Touchpad";
  488. interrupts-extended = <&acpi_gpe GPIO_18_IRQ
  489. IRQ_TYPE_EDGE_FALLING>;
  490. acpi,wake = <GPE0_DW1_15>;
  491. linux,probed;
  492. hid-descr-addr = <0x20>;
  493. };
  494. };
  495. i2c_5: i2c2@17,1 {
  496. compatible = "intel,apl-i2c";
  497. reg = <0x0200b910 0 0 0 0>;
  498. #address-cells = <1>;
  499. #size-cells = <0>;
  500. clocks = <&clk CLK_I2C>;
  501. i2c-scl-rising-time-ns = <76>;
  502. i2c-scl-falling-time-ns = <164>;
  503. clock-frequency = <400000>;
  504. i2c,speeds = <100000 400000 1000000>;
  505. wacom_digitizer: wacom-digitizer@9 {
  506. compatible = "hid-over-i2c";
  507. reg = <0x9>;
  508. acpi,hid = "WCOM50C1";
  509. acpi,ddn = "WCOM Digitizer";
  510. interrupts-extended = <&acpi_gpe GPIO_13_IRQ
  511. (IRQ_TYPE_LEVEL_LOW | X86_IRQ_TYPE_SHARED)>;
  512. hid-descr-addr = <0x1>;
  513. };
  514. };
  515. i2c_6: i2c2@17,2 {
  516. compatible = "intel,apl-i2c";
  517. reg = <0x0200ba10 0 0 0 0>;
  518. clocks = <&clk CLK_I2C>;
  519. status = "disabled";
  520. };
  521. i2c_7: i2c2@17,3 {
  522. compatible = "intel,apl-i2c";
  523. reg = <0x0200bb10 0 0 0 0>;
  524. clocks = <&clk CLK_I2C>;
  525. status = "disabled";
  526. };
  527. serial: serial@18,2 {
  528. reg = <0x0200c210 0 0 0 0>;
  529. u-boot,dm-pre-reloc;
  530. compatible = "intel,apl-ns16550";
  531. early-regs = <0xde000000 0x20>;
  532. reg-shift = <2>;
  533. clock-frequency = <1843200>;
  534. current-speed = <115200>;
  535. acpi,name = "URT3";
  536. pci,no-autoconfig;
  537. };
  538. sdmmc: sdmmc@1b,0 {
  539. reg = <0x0000d800 0 0 0 0>;
  540. compatible = "intel,apl-sd";
  541. cd-gpios = <&gpio_sw GPIO_177 GPIO_ACTIVE_LOW>;
  542. acpi,name = "SDCD";
  543. };
  544. emmc: emmc@1c,0 {
  545. reg = <0x0000e000 0 0 0 0>;
  546. compatible = "intel,apl-emmc";
  547. non-removable;
  548. };
  549. pch: pch@1f,0 {
  550. reg = <0x0000f800 0 0 0 0>;
  551. compatible = "intel,apl-pch";
  552. u-boot,dm-pre-reloc;
  553. #address-cells = <1>;
  554. #size-cells = <1>;
  555. lpc: lpc {
  556. compatible = "intel,apl-lpc";
  557. #address-cells = <1>;
  558. #size-cells = <0>;
  559. u-boot,dm-pre-reloc;
  560. cros_ec: cros-ec {
  561. u-boot,dm-pre-proper;
  562. u-boot,dm-vpl;
  563. compatible = "google,cros-ec-lpc";
  564. reg = <0x204 1 0x200 1 0x880 0x80>;
  565. /*
  566. * Describes the flash memory within
  567. * the EC
  568. */
  569. #address-cells = <1>;
  570. #size-cells = <1>;
  571. flash@8000000 {
  572. reg = <0x08000000 0x20000>;
  573. erase-value = <0xff>;
  574. };
  575. };
  576. };
  577. };
  578. };
  579. };
  580. &host_bridge {
  581. /*
  582. * PL1 override 12000 mW: the energy calculation is wrong with the
  583. * current VR solution. Experiments show that SoC TDP max (6W) can be
  584. * reached when RAPL PL1 is set to 12W. Set RAPL PL2 to 15W.
  585. */
  586. tdp-pl-override-mw = <12000 15000>;
  587. early-pads = <
  588. /* These two are for the debug UART */
  589. GPIO_46 /* UART2 RX */
  590. (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
  591. (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
  592. GPIO_47 /* UART2 TX */
  593. (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
  594. (PAD_CFG1_PULL_NATIVE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
  595. GPIO_75 /* I2S1_BCLK -- PCH_WP */
  596. (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP)
  597. (PAD_CFG1_PULL_UP_20K | PAD_CFG1_IOSSTATE_TXD_RXE)
  598. /* I2C2 - TPM */
  599. GPIO_128 /* LPSS_I2C2_SDA */
  600. (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
  601. (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
  602. GPIO_129 /* LPSS_I2C2_SCL */
  603. (PAD_CFG0_MODE_NF1 | PAD_CFG0_LOGICAL_RESET_DEEP)
  604. (PAD_CFG1_PULL_UP_2K | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
  605. GPIO_28 /* TPM IRQ */
  606. (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
  607. PAD_CFG0_TX_DISABLE | PAD_CFG0_ROUTE_IOAPIC |
  608. PAD_CFG0_TRIG_LEVEL | PAD_CFG0_RX_POL_INVERT)
  609. (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TXD_RXE)
  610. PAD_CFG_GPI(GPIO_25, UP_20K, DEEP) /* unused */
  611. /*
  612. * WLAN_PE_RST - default to deasserted just in case FSP
  613. * misbehaves
  614. */
  615. GPIO_122 /* SIO_SPI_2_RXD */
  616. (PAD_CFG0_MODE_GPIO | PAD_CFG0_LOGICAL_RESET_DEEP |
  617. PAD_CFG0_RX_DISABLE | 0)
  618. (PAD_CFG1_PULL_NONE | PAD_CFG1_IOSSTATE_TX_LAST_RXE)
  619. /* LPC */
  620. PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */
  621. PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */
  622. PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
  623. PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1) /* LPC_AD0 */
  624. PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1) /* LPC_AD1 */
  625. PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1) /* LPC_AD2 */
  626. PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */
  627. PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
  628. PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
  629. PAD_CFG_GPI(GPIO_101, NONE, DEEP) /* FST_IO2 -- MEM_CONFIG0 */
  630. PAD_CFG_GPI(GPIO_102, NONE, DEEP) /* FST_IO3 -- MEM_CONFIG1 */
  631. PAD_CFG_GPI(GPIO_38, NONE, DEEP) /* LPSS_UART0_RXD - MEM_CONFIG2*/
  632. PAD_CFG_GPI(GPIO_45, NONE, DEEP) /* LPSS_UART1_CTS - MEM_CONFIG3 */
  633. >;
  634. };
  635. &fsp_m {
  636. fspm,package = <PACKAGE_BGA>;
  637. fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>;
  638. fspm,memory-down = <MEMORY_DOWN_YES>;
  639. fspm,scrambler-support = <1>;
  640. fspm,interleaved-mode = <INTERLEAVED_MODE_ENABLE>;
  641. fspm,channel-hash-mask = <0x36>;
  642. fspm,slice-hash-mask = <0x9>;
  643. fspm,dual-rank-support-enable = <1>;
  644. fspm,low-memory-max-value = <2048>;
  645. fspm,ch0-rank-enable = <1>;
  646. fspm,ch0-device-width = <CHX_DEVICE_WIDTH_X16>;
  647. fspm,ch0-dram-density = <CHX_DEVICE_DENSITY_8GB>;
  648. fspm,ch0-option = <(CHX_OPTION_RANK_INTERLEAVING |
  649. CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
  650. fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
  651. fspm,ch1-rank-enable = <1>;
  652. fspm,ch1-device-width = <CHX_DEVICE_WIDTH_X16>;
  653. fspm,ch1-dram-density = <CHX_DEVICE_DENSITY_8GB>;
  654. fspm,ch1-option = <(CHX_OPTION_RANK_INTERLEAVING |
  655. CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
  656. fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
  657. fspm,ch2-rank-enable = <1>;
  658. fspm,ch2-device-width = <CHX_DEVICE_WIDTH_X16>;
  659. fspm,ch2-dram-density = <CHX_DEVICE_DENSITY_8GB>;
  660. fspm,ch2-option = <(CHX_OPTION_RANK_INTERLEAVING |
  661. CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
  662. fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
  663. fspm,ch3-rank-enable = <1>;
  664. fspm,ch3-device-width = <CHX_DEVICE_WIDTH_X16>;
  665. fspm,ch3-dram-density = <CHX_DEVICE_DENSITY_8GB>;
  666. fspm,ch3-option = <(CHX_OPTION_RANK_INTERLEAVING |
  667. CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
  668. fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
  669. fspm,fspm,skip-cse-rbp = <1>;
  670. fspm,ch-bit-swizzling = /bits/ 8 <
  671. /* LP4_PHYS_CH0A */
  672. /* DQA[0:7] pins of LPDDR4 module */
  673. 6 7 5 4 3 1 0 2
  674. /* DQA[8:15] pins of LPDDR4 module */
  675. 12 10 11 13 14 8 9 15
  676. /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
  677. 16 22 23 20 18 17 19 21
  678. /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
  679. 30 28 29 25 24 26 27 31
  680. /* LP4_PHYS_CH0B */
  681. /* DQA[0:7] pins of LPDDR4 module */
  682. 7 3 5 2 6 0 1 4
  683. /* DQA[8:15] pins of LPDDR4 module */
  684. 9 14 12 13 10 11 8 15
  685. /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
  686. 20 22 23 16 19 17 18 21
  687. /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
  688. 28 24 26 27 29 30 31 25
  689. /* LP4_PHYS_CH1A */
  690. /* DQA[0:7] pins of LPDDR4 module */
  691. 2 1 6 7 5 4 3 0
  692. /* DQA[8:15] pins of LPDDR4 module */
  693. 11 10 8 9 12 15 13 14
  694. /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
  695. 17 23 19 16 21 22 20 18
  696. /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
  697. 31 29 26 25 28 27 24 30
  698. /* LP4_PHYS_CH1B */
  699. /* DQA[0:7] pins of LPDDR4 module */
  700. 4 3 7 5 6 1 0 2
  701. /* DQA[8:15] pins of LPDDR4 module */
  702. 15 9 8 11 14 13 12 10
  703. /* DQB[0:7] pins of LPDDR4 module with offset of 16 */
  704. 20 23 22 21 18 19 16 17
  705. /* DQB[7:15] pins of LPDDR4 module with offset of 16 */
  706. 25 28 30 31 26 27 24 29>;
  707. fspm,dimm0-spd-address = <0>;
  708. fspm,dimm1-spd-address = <0>;
  709. fspm,skip-cse-rbp = <1>;
  710. fspm,enable-s3-heci2 = <0>;
  711. };
  712. &fsp_s {
  713. u-boot,dm-pre-proper;
  714. fsps,ish-enable = <0>;
  715. fsps,enable-sata = <0>;
  716. fsps,i2c6-enable = <I2CX_ENABLE_DISABLED>;
  717. fsps,i2c7-enable = <I2CX_ENABLE_DISABLED>;
  718. fsps,hsuart3-enable = <HSUARTX_ENABLE_DISABLED>;
  719. fsps,spi1-enable = <SPIX_ENABLE_DISABLED>;
  720. fsps,spi2-enable = <SPIX_ENABLE_DISABLED>;
  721. fsps,sdio-enabled = <0>;
  722. /* Disable unused clkreq of PCIe root ports */
  723. fsps,pcie-rp-clk-req-number = /bits/ 8 <0 /* wifi/bt */
  724. CLKREQ_DISABLED
  725. CLKREQ_DISABLED
  726. CLKREQ_DISABLED
  727. CLKREQ_DISABLED
  728. CLKREQ_DISABLED>;
  729. /*
  730. * GPIO for PERST_0
  731. * If the Board has PERST_0 signal, assign the GPIO
  732. * If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
  733. *
  734. * This are not used yet, so comment them out for now.
  735. *
  736. * prt0-gpio = <GPIO_122>;
  737. *
  738. * GPIO for SD card detect
  739. * sdcard-cd-gpio = <GPIO_177>;
  740. */
  741. /*
  742. * Order is emmc-tx-data-cntl1, emmc-tx-data-cntl2,
  743. * emmc-rx-cmd-data-cntl1, emmc-rx-cmd-data-cntl2
  744. *
  745. * EMMC TX DATA Delay 1
  746. * Refer to EDS-Vol2-22.3
  747. * [14:8] steps of delay for HS400, each 125ps
  748. * [6:0] steps of delay for SDR104/HS200, each 125ps
  749. /*
  750. * EMMC TX DATA Delay 2
  751. * Refer to EDS-Vol2-22.3.
  752. * [30:24] steps of delay for SDR50, each 125ps
  753. * [22:16] steps of delay for DDR50, each 125ps
  754. * [14:8] steps of delay for SDR25/HS50, each 125ps
  755. * [6:0] steps of delay for SDR12, each 125ps
  756. */
  757. /*
  758. * EMMC RX CMD/DATA Delay 1
  759. * Refer to EDS-Vol2-22.3.
  760. * [30:24] steps of delay for SDR50, each 125ps
  761. * [22:16] steps of delay for DDR50, each 125ps
  762. * [14:8] steps of delay for SDR25/HS50, each 125ps
  763. * [6:0] steps of delay for SDR12, each 125ps
  764. */
  765. /*
  766. * EMMC RX CMD/DATA Delay 2
  767. * Refer to EDS-Vol2-22.3.
  768. * [17:16] stands for Rx Clock before Output Buffer
  769. * [14:8] steps of delay for Auto Tuning Mode, each 125ps
  770. * [6:0] steps of delay for HS200, each 125ps
  771. */
  772. /* Enable DPTF */
  773. fsps,dptf-enabled;
  774. fsps,emmc-tx-data-cntl1 = <0x0c16>;
  775. fsps,emmc-tx-data-cntl2 = <0x28162828>;
  776. fsps,emmc-rx-cmd-data-cntl1 = <0x00181717>;
  777. fsps,emmc-rx-cmd-data-cntl2 = <0x10008>;
  778. /* Enable Audio Clock and Power gating */
  779. fsps,hd-audio-clk-gate = <1>;
  780. fsps,hd-audio-pwr-gate = <1>;
  781. fsps,bios-cfg-lock-down = <1>;
  782. /* Enable WiFi */
  783. fsps,pcie-root-port-en = [01 00 00 00 00 00];
  784. fsps,pcie-rp-hot-plug = [00 00 00 00 00 00];
  785. fsps,skip-mp-init = <1>;
  786. fsps,spi-eiss = <0>;
  787. fsps,rtc-lock = <0>;
  788. fsps,port-usb20-per-port-pe-txi-set = [07 07 06 06 07 07 07 01];
  789. fsps,port-usb20-per-port-txi-set = [00 02 00 00 00 00 00 03];
  790. fsps,lpss-s0ix-enable = <1>;
  791. fsps,usb-otg = <0>;
  792. fsps,monitor-mwait-enable = <0>;
  793. /*
  794. * TODO(sjg@chromium.org): Move this to the I2C nodes
  795. * Intel Common SoC Config
  796. *+-------------------+---------------------------+
  797. *| Field | Value |
  798. *+-------------------+---------------------------+
  799. *| I2C0 | Audio |
  800. *| I2C2 | TPM |
  801. *| I2C3 | Touchscreen |
  802. *| I2C4 | Trackpad |
  803. *| I2C5 | Digitizer |
  804. *+-------------------+---------------------------+
  805. *
  806. common_soc_config" = "{
  807. .i2c[0] = {
  808. .speed = I2C_SPEED_FAST,
  809. .rise-time-ns = 104,
  810. .fall-time-ns = 52,
  811. },
  812. .i2c[2] = {
  813. .early_init = 1,
  814. .speed = I2C_SPEED_FAST,
  815. .rise-time-ns = 57,
  816. .fall-time-ns = 28,
  817. },
  818. .i2c[3] = {
  819. .speed = I2C_SPEED_FAST,
  820. .rise-time-ns = 76,
  821. .fall-time-ns = 164,
  822. },
  823. .i2c[4] = {
  824. .speed = I2C_SPEED_FAST,
  825. .rise-time-ns = 114,
  826. .fall-time-ns = 164,
  827. .data_hold_time_ns = 350,
  828. },
  829. .i2c[5] = {
  830. .speed = I2C_SPEED_FAST,
  831. .rise-time-ns = 152,
  832. .fall-time-ns = 30,
  833. },
  834. }"
  835. */
  836. /* Minimum SLP S3 assertion width 28ms */
  837. slp-s3-assertion-width-usecs = <28000>;
  838. pads = <
  839. /* PCIE_WAKE[0:3]_N */
  840. PAD_CFG_GPI_SCI_LOW(GPIO_205, UP_20K, DEEP, EDGE_SINGLE) /* WLAN */
  841. PAD_CFG_GPI(GPIO_206, UP_20K, DEEP) /* Unused */
  842. PAD_CFG_GPI(GPIO_207, UP_20K, DEEP) /* Unused */
  843. PAD_CFG_GPI(GPIO_208, UP_20K, DEEP) /* Unused */
  844. /* EMMC interface */
  845. PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1) /* EMMC_CLK */
  846. PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D0 */
  847. PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D1 */
  848. PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D2 */
  849. PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_160, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D3 */
  850. PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_161, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D4 */
  851. PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D5 */
  852. PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D6 */
  853. PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_164, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_D7 */
  854. PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, UP_20K, DEEP, NF1, HIZCRX1, DISPUPD) /* EMMC_CMD */
  855. PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1) /* EMMC_RCLK */
  856. /* SDIO -- unused */
  857. PAD_CFG_GPI(GPIO_166, UP_20K, DEEP) /* SDIO_CLK */
  858. PAD_CFG_GPI(GPIO_167, UP_20K, DEEP) /* SDIO_D0 */
  859. /* Configure SDIO to enable power gating */
  860. PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1) /* SDIO_D1 */
  861. PAD_CFG_GPI(GPIO_169, UP_20K, DEEP) /* SDIO_D2 */
  862. PAD_CFG_GPI(GPIO_170, UP_20K, DEEP) /* SDIO_D3 */
  863. PAD_CFG_GPI(GPIO_171, UP_20K, DEEP) /* SDIO_CMD */
  864. /* SDCARD */
  865. /* Pull down clock by 20K */
  866. PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1) /* SDCARD_CLK */
  867. PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1) /* SDCARD_D0 */
  868. PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1) /* SDCARD_D1 */
  869. PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1) /* SDCARD_D2 */
  870. PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1) /* SDCARD_D3 */
  871. /* Card detect is active LOW with external pull up */
  872. PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1) /* SDCARD_CD_N */
  873. PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1) /* SDCARD_CMD */
  874. /* CLK feedback, internal signal, needs 20K pull down */
  875. PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1) /* SDCARD_CLK_FB */
  876. /* No h/w write proect for uSD cards, pull down by 20K */
  877. PAD_CFG_NF(GPIO_186, DN_20K, DEEP, NF1) /* SDCARD_LVL_WP */
  878. /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on */
  879. PAD_CFG_GPO(GPIO_183, 0, DEEP) /* SDIO_PWR_DOWN_N */
  880. /* SMBus -- unused */
  881. PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP) /* SMB_ALERT _N */
  882. PAD_CFG_GPI(SMB_CLK, UP_20K, DEEP) /* SMB_CLK */
  883. PAD_CFG_GPI(SMB_DATA, UP_20K, DEEP) /* SMB_DATA */
  884. /* LPC */
  885. PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1) /* LPC_SERIRQ */
  886. PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1) /* LPC_CLKOUT0 */
  887. PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1)
  888. PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1) /* LPC_AD0 */
  889. PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1) /* LPC_AD1 */
  890. PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1) /* LPC_AD2 */
  891. PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1) /* LPC_AD3 */
  892. PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
  893. PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
  894. /* I2C0 - Audio */
  895. PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1) /* LPSS_I2C0_SDA */
  896. PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1) /* LPSS_I2C0_SCL */
  897. /* I2C1 - NFC with external pulls */
  898. PAD_CFG_NF(GPIO_126, NONE, DEEP, NF1) /* LPSS_I2C1_SDA */
  899. PAD_CFG_NF(GPIO_127, NONE, DEEP, NF1) /* LPSS_I2C1_SCL */
  900. /* I2C2 - TPM */
  901. PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1) /* LPSS_I2C2_SDA */
  902. PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1) /* LPSS_I2C2_SCL */
  903. /* I2C3 - touch */
  904. PAD_CFG_NF(GPIO_130, UP_2K, DEEP, NF1) /* LPSS_I2C3_SDA */
  905. PAD_CFG_NF(GPIO_131, UP_2K, DEEP, NF1) /* LPSS_I2C3_SCL */
  906. /* I2C4 - trackpad */
  907. /* LPSS_I2C4_SDA */
  908. PAD_CFG_NF_IOSSTATE(GPIO_132, UP_2K, DEEP, NF1, HIZCRX1)
  909. /* LPSS_I2C4_SCL */
  910. PAD_CFG_NF_IOSSTATE(GPIO_133, UP_2K, DEEP, NF1, HIZCRX1)
  911. /* I2C5 -- pen with external pulls */
  912. PAD_CFG_NF(GPIO_134, NONE, DEEP, NF1) /* LPSS_I2C5_SDA */
  913. PAD_CFG_NF(GPIO_135, NONE, DEEP, NF1) /* LPSS_I2C5_SCL */
  914. /* I2C6-7 -- unused */
  915. PAD_CFG_GPI(GPIO_136, UP_20K, DEEP) /* LPSS_I2C6_SDA */
  916. PAD_CFG_GPI(GPIO_137, UP_20K, DEEP) /* LPSS_I2C6_SCL */
  917. PAD_CFG_GPI(GPIO_138, UP_20K, DEEP) /* LPSS_I2C7_SDA */
  918. PAD_CFG_GPI(GPIO_139, UP_20K, DEEP) /* LPSS_I2C7_SCL */
  919. /* Audio Amp - I2S6 */
  920. PAD_CFG_NF(GPIO_146, NATIVE, DEEP, NF2) /* ISH_GPIO_0 - I2S6_BCLK */
  921. PAD_CFG_NF(GPIO_147, NATIVE, DEEP, NF2) /* ISH_GPIO_1 - I2S6_WS_SYNC */
  922. PAD_CFG_GPI(GPIO_148, UP_20K, DEEP) /* ISH_GPIO_2 - unused */
  923. PAD_CFG_NF(GPIO_149, NATIVE, DEEP, NF2) /* ISH_GPIO_3 - I2S6_SDO */
  924. /* NFC Reset */
  925. PAD_CFG_GPO(GPIO_150, 1, DEEP) /* ISH_GPIO_4 */
  926. PAD_CFG_GPI(GPIO_151, UP_20K, DEEP) /* ISH_GPIO_5 - unused */
  927. /* Touch enable */
  928. PAD_CFG_GPO(GPIO_152, 1, DEEP) /* ISH_GPIO_6 */
  929. PAD_CFG_GPI(GPIO_153, UP_20K, DEEP) /* ISH_GPIO_7 - unused */
  930. PAD_CFG_GPI(GPIO_154, UP_20K, DEEP) /* ISH_GPIO_8 - unused */
  931. PAD_CFG_GPI(GPIO_155, UP_20K, DEEP) /* ISH_GPIO_9 - unused */
  932. /* PCIE_CLKREQ[0:3]_N */
  933. PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1) /* WLAN with external pull */
  934. PAD_CFG_GPI(GPIO_210, UP_20K, DEEP) /* unused */
  935. PAD_CFG_GPI(GPIO_211, UP_20K, DEEP) /* unused */
  936. PAD_CFG_GPI(GPIO_212, UP_20K, DEEP) /* unused */
  937. /* OSC_CLK_OUT_[0:4] -- unused */
  938. PAD_CFG_GPI(OSC_CLK_OUT_0, UP_20K, DEEP)
  939. PAD_CFG_GPI(OSC_CLK_OUT_1, UP_20K, DEEP)
  940. PAD_CFG_GPI(OSC_CLK_OUT_2, UP_20K, DEEP)
  941. PAD_CFG_GPI(OSC_CLK_OUT_3, UP_20K, DEEP)
  942. PAD_CFG_GPI(OSC_CLK_OUT_4, UP_20K, DEEP)
  943. /* PMU Signals */
  944. PAD_CFG_GPI(PMU_AC_PRESENT, UP_20K, DEEP) /* PMU_AC_PRESENT - unused */
  945. PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1) /* PMU_BATLOW_N */
  946. PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1) /* PMU_PLTRST_N */
  947. PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1) /* PMU_PWRBTN_N */
  948. PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1) /* PMU_RSTBTN_N */
  949. PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE) /* PMU_SLP_S0_N */
  950. PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1) /* PMU_SLP_S3_N */
  951. PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1) /* PMU_SLP_S4_N */
  952. PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1) /* PMU_SUSCLK */
  953. PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP) /* EN_PP3300_EMMC */
  954. PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1) /* SUS_STAT_N */
  955. PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1) /* SUSPWRDNACK */
  956. /* DDI[0:1] SDA and SCL -- unused */
  957. PAD_CFG_GPI(GPIO_187, UP_20K, DEEP) /* HV_DDI0_DDC_SDA */
  958. PAD_CFG_GPI(GPIO_188, UP_20K, DEEP) /* HV_DDI0_DDC_SCL */
  959. PAD_CFG_GPI(GPIO_189, UP_20K, DEEP) /* HV_DDI1_DDC_SDA */
  960. PAD_CFG_GPI(GPIO_190, UP_20K, DEEP) /* HV_DDI1_DDC_SCL */
  961. /* MIPI I2C -- unused */
  962. PAD_CFG_GPI(GPIO_191, UP_20K, DEEP) /* MIPI_I2C_SDA */
  963. PAD_CFG_GPI(GPIO_192, UP_20K, DEEP) /* MIPI_I2C_SCL */
  964. /* Panel 0 control */
  965. PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1) /* PNL0_VDDEN */
  966. PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1) /* PNL0_BKLTEN */
  967. PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1) /* PNL0_BKLTCTL */
  968. /* Panel 1 control -- unused */
  969. PAD_CFG_NF(GPIO_196, NATIVE, DEEP, NF1) /* PNL1_VDDEN */
  970. PAD_CFG_NF(GPIO_197, NATIVE, DEEP, NF1) /* PNL1_BKLTEN */
  971. PAD_CFG_NF(GPIO_198, NATIVE, DEEP, NF1) /* PNL1_BKLTCTL */
  972. /* Hot plug detect */
  973. PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2) /* HV_DDI1_HPD */
  974. PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2) /* HV_DDI0_HPD */
  975. /* MDSI signals -- unused */
  976. PAD_CFG_GPI(GPIO_201, UP_20K, DEEP) /* MDSI_A_TE */
  977. PAD_CFG_GPI(GPIO_202, UP_20K, DEEP) /* MDSI_A_TE */
  978. /* USB overcurrent pins */
  979. PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1) /* USB_OC0_N */
  980. PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1) /* USB_OC1_N */
  981. /* PMC SPI -- almost entirely unused */
  982. PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP)
  983. PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2) /* HV_DDI2_HPD -- EDP HPD */
  984. PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP)
  985. PAD_CFG_GPI(PMC_SPI_RXD, UP_20K, DEEP)
  986. PAD_CFG_GPI(PMC_SPI_TXD, UP_20K, DEEP)
  987. PAD_CFG_GPI(PMC_SPI_CLK, UP_20K, DEEP)
  988. /* PMIC Signals Unused signals related to an old PMIC interface */
  989. PAD_CFG_NF_IOSSTATE(PMIC_RESET_B, NATIVE, DEEP, NF1, IGNORE) /* PMIC_RESET_B */
  990. PAD_CFG_GPI(GPIO_213, NONE, DEEP) /* unused external pull */
  991. PAD_CFG_GPI(GPIO_214, UP_20K, DEEP) /* unused */
  992. PAD_CFG_GPI(GPIO_215, UP_20K, DEEP) /* unused */
  993. PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1) /* THERMTRIP_N */
  994. PAD_CFG_GPI(PMIC_STDBY, UP_20K, DEEP) /* unused */
  995. PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1) /* PROCHOT_N */
  996. PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1) /* PMIC_I2C_SCL */
  997. PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1) /* PMIC_I2C_SDA */
  998. /* I2S1 -- largely unused */
  999. PAD_CFG_GPI(GPIO_74, UP_20K, DEEP) /* I2S1_MCLK */
  1000. PAD_CFG_GPI(GPIO_75, UP_20K, DEEP) /* I2S1_BCLK -- PCH_WP */
  1001. PAD_CFG_GPO(GPIO_76, 0, DEEP) /* I2S1_WS_SYNC -- SPK_PA_EN */
  1002. PAD_CFG_GPI(GPIO_77, UP_20K, DEEP) /* I2S1_SDI */
  1003. PAD_CFG_GPO(GPIO_78, 1, DEEP) /* I2S1_SDO -- EN_PP3300_DX_LTE_SOC */
  1004. /* DMIC or I2S4 */
  1005. /* AVS_DMIC_CLK_A1 */
  1006. PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, IGNORE)
  1007. PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1) /* AVS_DMIC_CLK_B1 */
  1008. PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_1 */
  1009. PAD_CFG_GPI(GPIO_82, DN_20K, DEEP) /* unused -- strap */
  1010. PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1) /* AVS_DMIC_DATA_2 */
  1011. /* I2S2 -- Headset amp */
  1012. PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1) /* AVS_I2S2_MCLK */
  1013. PAD_CFG_NF(GPIO_85, NATIVE, DEEP, NF1) /* AVS_I2S2_BCLK */
  1014. PAD_CFG_NF(GPIO_86, NATIVE, DEEP, NF1) /* AVS_I2S2_SW_SYNC */
  1015. PAD_CFG_NF(GPIO_87, NATIVE, DEEP, NF1) /* AVS_I2S2_SDI */
  1016. PAD_CFG_NF(GPIO_88, NATIVE, DEEP, NF1) /* AVS_I2S2_SDO */
  1017. /* I2S3 -- largely unused */
  1018. PAD_CFG_GPI(GPIO_89, UP_20K, DEEP) /* unused */
  1019. PAD_CFG_GPI(GPIO_90, UP_20K, DEEP) /* GPS_HOST_WAKE */
  1020. PAD_CFG_GPO(GPIO_91, 1, DEEP) /* GPS_EN */
  1021. PAD_CFG_GPI(GPIO_92, DN_20K, DEEP) /* unused -- strap */
  1022. /* Fast SPI */
  1023. PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CS0_B */
  1024. PAD_CFG_GPI(GPIO_98, UP_20K, DEEP) /* FST_SPI_CS1_B -- unused */
  1025. PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MOSI_IO0 */
  1026. PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_MISO_IO1 */
  1027. PAD_CFG_GPI(GPIO_101, NONE, DEEP) /* FST_IO2 -- MEM_CONFIG0 */
  1028. PAD_CFG_GPI(GPIO_102, NONE, DEEP) /* FST_IO3 -- MEM_CONFIG1 */
  1029. PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK */
  1030. PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE) /* FST_SPI_CLK_FB */
  1031. PAD_CFG_NF_IOSSTATE(GPIO_106, NATIVE, DEEP, NF3, IGNORE) /* FST_SPI_CS2_N */
  1032. /* SIO_SPI_0 - Used for FP */
  1033. PAD_CFG_NF(GPIO_104, NATIVE, DEEP, NF1) /* SIO_SPI_0_CLK */
  1034. PAD_CFG_NF(GPIO_105, NATIVE, DEEP, NF1) /* SIO_SPI_0_FS0 */
  1035. PAD_CFG_NF(GPIO_109, NATIVE, DEEP, NF1) /* SIO_SPI_0_RXD */
  1036. PAD_CFG_NF(GPIO_110, NATIVE, DEEP, NF1) /* SIO_SPI_0_TXD */
  1037. /* SIO_SPI_1 -- largely unused */
  1038. PAD_CFG_GPI(GPIO_111, UP_20K, DEEP) /* SIO_SPI_1_CLK */
  1039. PAD_CFG_GPI(GPIO_112, UP_20K, DEEP) /* SIO_SPI_1_FS0 */
  1040. PAD_CFG_GPI(GPIO_113, UP_20K, DEEP) /* SIO_SPI_1_FS1 */
  1041. /* Headset interrupt */
  1042. PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP) /* SIO_SPI_1_RXD */
  1043. PAD_CFG_GPI(GPIO_117, UP_20K, DEEP) /* SIO_SPI_1_TXD */
  1044. /* SIO_SPI_2 -- unused */
  1045. PAD_CFG_GPI(GPIO_118, UP_20K, DEEP) /* SIO_SPI_2_CLK */
  1046. PAD_CFG_GPI(GPIO_119, UP_20K, DEEP) /* SIO_SPI_2_FS0 */
  1047. PAD_CFG_GPI(GPIO_120, UP_20K, DEEP) /* SIO_SPI_2_FS1 */
  1048. PAD_CFG_GPI(GPIO_121, UP_20K, DEEP) /* SIO_SPI_2_FS2 */
  1049. /* WLAN_PE_RST - default to deasserted */
  1050. PAD_CFG_GPO(GPIO_122, 0, DEEP) /* SIO_SPI_2_RXD */
  1051. PAD_CFG_GPI(GPIO_123, UP_20K, DEEP) /* SIO_SPI_2_TXD */
  1052. /* Debug tracing */
  1053. PAD_CFG_GPI(GPIO_0, UP_20K, DEEP)
  1054. PAD_CFG_GPI(GPIO_1, UP_20K, DEEP)
  1055. PAD_CFG_GPI(GPIO_2, UP_20K, DEEP)
  1056. PAD_CFG_GPI_SCI_HIGH(GPIO_3, DN_20K, DEEP, LEVEL) /* FP_INT */
  1057. PAD_CFG_GPI(GPIO_4, UP_20K, DEEP)
  1058. PAD_CFG_GPI(GPIO_5, UP_20K, DEEP)
  1059. PAD_CFG_GPI(GPIO_6, UP_20K, DEEP)
  1060. PAD_CFG_GPI(GPIO_7, UP_20K, DEEP)
  1061. PAD_CFG_GPI(GPIO_8, UP_20K, DEEP)
  1062. PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP) /* dTPM IRQ */
  1063. PAD_CFG_GPI(GPIO_10, DN_20K, DEEP) /* Board phase enforcement */
  1064. PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE) /* EC SCI */
  1065. PAD_CFG_GPI(GPIO_12, UP_20K, DEEP) /* unused */
  1066. PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP) /* PEN_INT_ODL */
  1067. PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP) /* FP_INT */
  1068. PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE) /* TRACKPAD_INT_1V8_ODL */
  1069. PAD_CFG_GPI(GPIO_16, UP_20K, DEEP) /* unused */
  1070. PAD_CFG_GPI(GPIO_17, UP_20K, DEEP) /* 1 vs 4 DMIC config */
  1071. PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP) /* Trackpad IRQ */
  1072. PAD_CFG_GPI(GPIO_19, UP_20K, DEEP) /* unused */
  1073. PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP) /* NFC IRQ */
  1074. PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP) /* Touch IRQ */
  1075. PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, EDGE_SINGLE) /* EC wake */
  1076. PAD_CFG_GPI(GPIO_23, UP_20K, DEEP) /* unused */
  1077. PAD_CFG_GPI(GPIO_24, NONE, DEEP) /* PEN_PDCT_ODL */
  1078. PAD_CFG_GPI(GPIO_25, UP_20K, DEEP) /* unused */
  1079. PAD_CFG_GPI(GPIO_26, UP_20K, DEEP) /* unused */
  1080. PAD_CFG_GPI(GPIO_27, UP_20K, DEEP) /* unused */
  1081. PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP) /* TPM IRQ */
  1082. PAD_CFG_GPO(GPIO_29, 1, DEEP) /* FP reset */
  1083. PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP) /* KB IRQ */
  1084. PAD_CFG_GPO(GPIO_31, 0, DEEP) /* NFC FW DL */
  1085. PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5) /* SUS_CLK2 */
  1086. PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP) /* PMIC IRQ */
  1087. PAD_CFG_GPI(GPIO_34, UP_20K, DEEP) /* unused */
  1088. PAD_CFG_GPO(GPIO_35, 0, DEEP) /* PEN_RESET - active high */
  1089. PAD_CFG_GPO(GPIO_36, 0, DEEP) /* touch reset */
  1090. PAD_CFG_GPI(GPIO_37, UP_20K, DEEP) /* unused */
  1091. /* LPSS_UART[0:2] */
  1092. PAD_CFG_GPI(GPIO_38, NONE, DEEP) /* LPSS_UART0_RXD - MEM_CONFIG2*/
  1093. /* Next 2 are straps */
  1094. PAD_CFG_GPI(GPIO_39, DN_20K, DEEP) /* LPSS_UART0_TXD - unused */
  1095. PAD_CFG_GPI(GPIO_40, DN_20K, DEEP) /* LPSS_UART0_RTS - unused */
  1096. PAD_CFG_GPI(GPIO_41, NONE, DEEP) /* LPSS_UART0_CTS - EC_IN_RW */
  1097. PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1) /* LPSS_UART1_RXD */
  1098. PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1) /* LPSS_UART1_TXD */
  1099. PAD_CFG_GPO(GPIO_44, 1, DEEP) /* GPS_RST_ODL */
  1100. PAD_CFG_GPI(GPIO_45, NONE, DEEP) /* LPSS_UART1_CTS - MEM_CONFIG3 */
  1101. PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1) /* LPSS_UART2_RXD */
  1102. PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, TX1_RX_DCR_X0) /* UART2 TX */
  1103. PAD_CFG_GPI(GPIO_48, UP_20K, DEEP) /* LPSS_UART2_RTS - unused */
  1104. PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE) /* LPSS_UART2_CTS - EC_SMI_L */
  1105. /* Camera interface -- completely unused */
  1106. PAD_CFG_GPI(GPIO_62, UP_20K, DEEP) /* GP_CAMERASB00 */
  1107. PAD_CFG_GPI(GPIO_63, UP_20K, DEEP) /* GP_CAMERASB01 */
  1108. PAD_CFG_GPI(GPIO_64, UP_20K, DEEP) /* GP_CAMERASB02 */
  1109. PAD_CFG_GPI(GPIO_65, UP_20K, DEEP) /* GP_CAMERASB03 */
  1110. PAD_CFG_GPI(GPIO_66, UP_20K, DEEP) /* GP_CAMERASB04 */
  1111. PAD_CFG_GPI(GPIO_67, UP_20K, DEEP) /* GP_CAMERASB05 */
  1112. PAD_CFG_GPI(GPIO_68, UP_20K, DEEP) /* GP_CAMERASB06 */
  1113. PAD_CFG_GPI(GPIO_69, UP_20K, DEEP) /* GP_CAMERASB07 */
  1114. PAD_CFG_GPI(GPIO_70, UP_20K, DEEP) /* GP_CAMERASB08 */
  1115. PAD_CFG_GPI(GPIO_71, UP_20K, DEEP) /* GP_CAMERASB09 */
  1116. PAD_CFG_GPI(GPIO_72, UP_20K, DEEP) /* GP_CAMERASB10 */
  1117. PAD_CFG_GPI(GPIO_73, UP_20K, DEEP) /* GP_CAMERASB11 */
  1118. >;
  1119. };
  1120. &rtc {
  1121. #address-cells = <1>;
  1122. #size-cells = <0>;
  1123. u-boot,dm-pre-proper;
  1124. };