baytrail_som-db5800-som-6867.dts 6.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
  4. * Copyright (C) 2016, George McCollister <george.mccollister@gmail.com>
  5. */
  6. /dts-v1/;
  7. #include <asm/arch-baytrail/fsp/fsp_configs.h>
  8. #include <dt-bindings/gpio/x86-gpio.h>
  9. #include <dt-bindings/interrupt-router/intel-irq.h>
  10. /include/ "skeleton.dtsi"
  11. /include/ "serial.dtsi"
  12. /include/ "reset.dtsi"
  13. /include/ "rtc.dtsi"
  14. #include "tsc_timer.dtsi"
  15. #include "smbios.dtsi"
  16. / {
  17. model = "Advantech SOM-DB5800-SOM-6867";
  18. compatible = "advantech,som-db5800-som-6867", "intel,baytrail";
  19. aliases {
  20. serial0 = &serial;
  21. spi0 = &spi;
  22. };
  23. config {
  24. silent_console = <0>;
  25. };
  26. pch_pinctrl {
  27. compatible = "intel,x86-pinctrl";
  28. reg = <0 0>;
  29. /* HDA_RSTB */
  30. soc_gpio_s0_8@0 {
  31. pad-offset = <0x220>;
  32. mode-func = <2>;
  33. };
  34. /* HDA_SYNC */
  35. soc_gpio_s0_9@0 {
  36. pad-offset = <0x250>;
  37. mode-func = <2>;
  38. pull-assign = <1>;
  39. };
  40. /* HDA_CLK */
  41. soc_gpio_s0_10@0 {
  42. pad-offset = <0x240>;
  43. mode-func = <2>;
  44. };
  45. /* HDA_SDO */
  46. soc_gpio_s0_11@0 {
  47. pad-offset = <0x260>;
  48. mode-func = <2>;
  49. pull-assign = <1>;
  50. };
  51. /* HDA_SDI0 */
  52. soc_gpio_s0_12@0 {
  53. pad-offset = <0x270>;
  54. mode-func = <2>;
  55. };
  56. /* SERIRQ */
  57. soc_gpio_s0_50@0 {
  58. pad-offset = <0x560>;
  59. mode-func = <1>;
  60. };
  61. };
  62. chosen {
  63. stdout-path = "/serial";
  64. };
  65. cpus {
  66. #address-cells = <1>;
  67. #size-cells = <0>;
  68. cpu@0 {
  69. device_type = "cpu";
  70. compatible = "intel,baytrail-cpu";
  71. reg = <0>;
  72. intel,apic-id = <0>;
  73. };
  74. cpu@1 {
  75. device_type = "cpu";
  76. compatible = "intel,baytrail-cpu";
  77. reg = <1>;
  78. intel,apic-id = <2>;
  79. };
  80. cpu@2 {
  81. device_type = "cpu";
  82. compatible = "intel,baytrail-cpu";
  83. reg = <2>;
  84. intel,apic-id = <4>;
  85. };
  86. cpu@3 {
  87. device_type = "cpu";
  88. compatible = "intel,baytrail-cpu";
  89. reg = <3>;
  90. intel,apic-id = <6>;
  91. };
  92. };
  93. pci {
  94. compatible = "intel,pci-baytrail", "pci-x86";
  95. #address-cells = <3>;
  96. #size-cells = <2>;
  97. u-boot,dm-pre-reloc;
  98. ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
  99. 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
  100. 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  101. pch@1f,0 {
  102. reg = <0x0000f800 0 0 0 0>;
  103. compatible = "pci8086,0f1c", "intel,pch9";
  104. #address-cells = <1>;
  105. #size-cells = <1>;
  106. irq-router {
  107. compatible = "intel,irq-router";
  108. intel,pirq-config = "ibase";
  109. intel,ibase-offset = <0x50>;
  110. intel,actl-addr = <0>;
  111. intel,pirq-link = <8 8>;
  112. intel,pirq-mask = <0xdee0>;
  113. intel,pirq-routing = <
  114. /* BayTrail PCI devices */
  115. PCI_BDF(0, 2, 0) INTA PIRQA
  116. PCI_BDF(0, 3, 0) INTA PIRQA
  117. PCI_BDF(0, 16, 0) INTA PIRQA
  118. PCI_BDF(0, 17, 0) INTA PIRQA
  119. PCI_BDF(0, 18, 0) INTA PIRQA
  120. PCI_BDF(0, 19, 0) INTA PIRQA
  121. PCI_BDF(0, 20, 0) INTA PIRQA
  122. PCI_BDF(0, 21, 0) INTA PIRQA
  123. PCI_BDF(0, 22, 0) INTA PIRQA
  124. PCI_BDF(0, 23, 0) INTA PIRQA
  125. PCI_BDF(0, 24, 0) INTA PIRQA
  126. PCI_BDF(0, 24, 1) INTC PIRQC
  127. PCI_BDF(0, 24, 2) INTD PIRQD
  128. PCI_BDF(0, 24, 3) INTB PIRQB
  129. PCI_BDF(0, 24, 4) INTA PIRQA
  130. PCI_BDF(0, 24, 5) INTC PIRQC
  131. PCI_BDF(0, 24, 6) INTD PIRQD
  132. PCI_BDF(0, 24, 7) INTB PIRQB
  133. PCI_BDF(0, 26, 0) INTA PIRQA
  134. PCI_BDF(0, 27, 0) INTA PIRQA
  135. PCI_BDF(0, 28, 0) INTA PIRQA
  136. PCI_BDF(0, 28, 1) INTB PIRQB
  137. PCI_BDF(0, 28, 2) INTC PIRQC
  138. PCI_BDF(0, 28, 3) INTD PIRQD
  139. PCI_BDF(0, 29, 0) INTA PIRQA
  140. PCI_BDF(0, 30, 0) INTA PIRQA
  141. PCI_BDF(0, 30, 1) INTD PIRQD
  142. PCI_BDF(0, 30, 2) INTB PIRQB
  143. PCI_BDF(0, 30, 3) INTC PIRQC
  144. PCI_BDF(0, 30, 4) INTD PIRQD
  145. PCI_BDF(0, 30, 5) INTB PIRQB
  146. PCI_BDF(0, 31, 3) INTB PIRQB
  147. /*
  148. * PCIe root ports downstream
  149. * interrupts
  150. */
  151. PCI_BDF(1, 0, 0) INTA PIRQA
  152. PCI_BDF(1, 0, 0) INTB PIRQB
  153. PCI_BDF(1, 0, 0) INTC PIRQC
  154. PCI_BDF(1, 0, 0) INTD PIRQD
  155. PCI_BDF(2, 0, 0) INTA PIRQB
  156. PCI_BDF(2, 0, 0) INTB PIRQC
  157. PCI_BDF(2, 0, 0) INTC PIRQD
  158. PCI_BDF(2, 0, 0) INTD PIRQA
  159. PCI_BDF(3, 0, 0) INTA PIRQC
  160. PCI_BDF(3, 0, 0) INTB PIRQD
  161. PCI_BDF(3, 0, 0) INTC PIRQA
  162. PCI_BDF(3, 0, 0) INTD PIRQB
  163. PCI_BDF(4, 0, 0) INTA PIRQD
  164. PCI_BDF(4, 0, 0) INTB PIRQA
  165. PCI_BDF(4, 0, 0) INTC PIRQB
  166. PCI_BDF(4, 0, 0) INTD PIRQC
  167. >;
  168. };
  169. spi: spi {
  170. #address-cells = <1>;
  171. #size-cells = <0>;
  172. compatible = "intel,ich9-spi";
  173. spi-flash@0 {
  174. #address-cells = <1>;
  175. #size-cells = <1>;
  176. reg = <0>;
  177. m25p,fast-read;
  178. compatible = "macronix,mx25l6405d",
  179. "jedec,spi-nor";
  180. memory-map = <0xff800000 0x00800000>;
  181. rw-mrc-cache {
  182. label = "rw-mrc-cache";
  183. reg = <0x006f0000 0x00010000>;
  184. };
  185. };
  186. };
  187. gpioa {
  188. compatible = "intel,ich6-gpio";
  189. u-boot,dm-pre-reloc;
  190. reg = <0 0x20>;
  191. bank-name = "A";
  192. use-lvl-write-cache;
  193. };
  194. gpiob {
  195. compatible = "intel,ich6-gpio";
  196. u-boot,dm-pre-reloc;
  197. reg = <0x20 0x20>;
  198. bank-name = "B";
  199. use-lvl-write-cache;
  200. };
  201. gpioc {
  202. compatible = "intel,ich6-gpio";
  203. u-boot,dm-pre-reloc;
  204. reg = <0x40 0x20>;
  205. bank-name = "C";
  206. use-lvl-write-cache;
  207. };
  208. gpiod {
  209. compatible = "intel,ich6-gpio";
  210. u-boot,dm-pre-reloc;
  211. reg = <0x60 0x20>;
  212. bank-name = "D";
  213. use-lvl-write-cache;
  214. };
  215. gpioe {
  216. compatible = "intel,ich6-gpio";
  217. u-boot,dm-pre-reloc;
  218. reg = <0x80 0x20>;
  219. bank-name = "E";
  220. use-lvl-write-cache;
  221. };
  222. gpiof {
  223. compatible = "intel,ich6-gpio";
  224. u-boot,dm-pre-reloc;
  225. reg = <0xA0 0x20>;
  226. bank-name = "F";
  227. use-lvl-write-cache;
  228. };
  229. };
  230. };
  231. fsp {
  232. compatible = "intel,baytrail-fsp";
  233. fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
  234. fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
  235. fsp,mrc-init-spd-addr1 = <0xa0>;
  236. fsp,mrc-init-spd-addr2 = <0xa2>;
  237. fsp,enable-spi;
  238. fsp,enable-sata;
  239. fsp,sata-mode = <SATA_MODE_AHCI>;
  240. fsp,enable-azalia;
  241. fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
  242. fsp,enable-dma0;
  243. fsp,enable-dma1;
  244. fsp,enable-i2c0;
  245. fsp,enable-i2c1;
  246. fsp,enable-i2c2;
  247. fsp,enable-i2c3;
  248. fsp,enable-i2c4;
  249. fsp,enable-i2c5;
  250. fsp,enable-i2c6;
  251. fsp,enable-pwm0;
  252. fsp,enable-pwm1;
  253. fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
  254. fsp,aperture-size = <APERTURE_SIZE_256MB>;
  255. fsp,gtt-size = <GTT_SIZE_2MB>;
  256. fsp,scc-mode = <SCC_MODE_PCI>;
  257. fsp,os-selection = <OS_SELECTION_LINUX>;
  258. fsp,enable-igd;
  259. };
  260. microcode {
  261. update@0 {
  262. #include "microcode/m0130673325.dtsi"
  263. };
  264. update@1 {
  265. #include "microcode/m0130679907.dtsi"
  266. };
  267. };
  268. };