bayleybay.dts 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  4. */
  5. /dts-v1/;
  6. #include <asm/arch-baytrail/fsp/fsp_configs.h>
  7. #include <dt-bindings/gpio/x86-gpio.h>
  8. #include <dt-bindings/interrupt-router/intel-irq.h>
  9. /include/ "skeleton.dtsi"
  10. /include/ "keyboard.dtsi"
  11. /include/ "serial.dtsi"
  12. /include/ "reset.dtsi"
  13. /include/ "rtc.dtsi"
  14. #include "tsc_timer.dtsi"
  15. #include "smbios.dtsi"
  16. / {
  17. model = "Intel Bayley Bay";
  18. compatible = "intel,bayleybay", "intel,baytrail";
  19. aliases {
  20. serial0 = &serial;
  21. spi0 = &spi;
  22. };
  23. config {
  24. silent_console = <0>;
  25. };
  26. chosen {
  27. stdout-path = "/serial";
  28. };
  29. cpus {
  30. #address-cells = <1>;
  31. #size-cells = <0>;
  32. cpu@0 {
  33. device_type = "cpu";
  34. compatible = "intel,baytrail-cpu";
  35. reg = <0>;
  36. intel,apic-id = <0>;
  37. };
  38. cpu@1 {
  39. device_type = "cpu";
  40. compatible = "intel,baytrail-cpu";
  41. reg = <1>;
  42. intel,apic-id = <2>;
  43. };
  44. cpu@2 {
  45. device_type = "cpu";
  46. compatible = "intel,baytrail-cpu";
  47. reg = <2>;
  48. intel,apic-id = <4>;
  49. };
  50. cpu@3 {
  51. device_type = "cpu";
  52. compatible = "intel,baytrail-cpu";
  53. reg = <3>;
  54. intel,apic-id = <6>;
  55. };
  56. };
  57. pch_pinctrl {
  58. compatible = "intel,x86-pinctrl";
  59. reg = <0 0>;
  60. /*
  61. * As of today, the latest version FSP (gold4) for BayTrail
  62. * misses the PAD configuration of the SD controller's Card
  63. * Detect signal. The default PAD value for the CD pin sets
  64. * the pin to work in GPIO mode, which causes card detect
  65. * status cannot be reflected by the Present State register
  66. * in the SD controller (bit 16 & bit 18 are always zero).
  67. *
  68. * Configure this pin to function 1 (SD controller).
  69. */
  70. sdmmc3_cd@0 {
  71. pad-offset = <0x3a0>;
  72. mode-func = <1>;
  73. };
  74. };
  75. pci {
  76. compatible = "pci-x86";
  77. #address-cells = <3>;
  78. #size-cells = <2>;
  79. u-boot,dm-pre-reloc;
  80. ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
  81. 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
  82. 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  83. pch@1f,0 {
  84. reg = <0x0000f800 0 0 0 0>;
  85. compatible = "intel,pch9";
  86. #address-cells = <1>;
  87. #size-cells = <1>;
  88. irq-router {
  89. compatible = "intel,irq-router";
  90. intel,pirq-config = "ibase";
  91. intel,ibase-offset = <0x50>;
  92. intel,actl-addr = <0>;
  93. intel,pirq-link = <8 8>;
  94. intel,pirq-mask = <0xdee0>;
  95. intel,pirq-routing = <
  96. /* BayTrail PCI devices */
  97. PCI_BDF(0, 2, 0) INTA PIRQA
  98. PCI_BDF(0, 3, 0) INTA PIRQA
  99. PCI_BDF(0, 16, 0) INTA PIRQA
  100. PCI_BDF(0, 17, 0) INTA PIRQA
  101. PCI_BDF(0, 18, 0) INTA PIRQA
  102. PCI_BDF(0, 19, 0) INTA PIRQA
  103. PCI_BDF(0, 20, 0) INTA PIRQA
  104. PCI_BDF(0, 21, 0) INTA PIRQA
  105. PCI_BDF(0, 22, 0) INTA PIRQA
  106. PCI_BDF(0, 23, 0) INTA PIRQA
  107. PCI_BDF(0, 24, 0) INTA PIRQA
  108. PCI_BDF(0, 24, 1) INTC PIRQC
  109. PCI_BDF(0, 24, 2) INTD PIRQD
  110. PCI_BDF(0, 24, 3) INTB PIRQB
  111. PCI_BDF(0, 24, 4) INTA PIRQA
  112. PCI_BDF(0, 24, 5) INTC PIRQC
  113. PCI_BDF(0, 24, 6) INTD PIRQD
  114. PCI_BDF(0, 24, 7) INTB PIRQB
  115. PCI_BDF(0, 26, 0) INTA PIRQA
  116. PCI_BDF(0, 27, 0) INTA PIRQA
  117. PCI_BDF(0, 28, 0) INTA PIRQA
  118. PCI_BDF(0, 28, 1) INTB PIRQB
  119. PCI_BDF(0, 28, 2) INTC PIRQC
  120. PCI_BDF(0, 28, 3) INTD PIRQD
  121. PCI_BDF(0, 29, 0) INTA PIRQA
  122. PCI_BDF(0, 30, 0) INTA PIRQA
  123. PCI_BDF(0, 30, 1) INTD PIRQD
  124. PCI_BDF(0, 30, 2) INTB PIRQB
  125. PCI_BDF(0, 30, 3) INTC PIRQC
  126. PCI_BDF(0, 30, 4) INTD PIRQD
  127. PCI_BDF(0, 30, 5) INTB PIRQB
  128. PCI_BDF(0, 31, 3) INTB PIRQB
  129. /*
  130. * PCIe root ports downstream
  131. * interrupts
  132. */
  133. PCI_BDF(1, 0, 0) INTA PIRQA
  134. PCI_BDF(1, 0, 0) INTB PIRQB
  135. PCI_BDF(1, 0, 0) INTC PIRQC
  136. PCI_BDF(1, 0, 0) INTD PIRQD
  137. PCI_BDF(2, 0, 0) INTA PIRQB
  138. PCI_BDF(2, 0, 0) INTB PIRQC
  139. PCI_BDF(2, 0, 0) INTC PIRQD
  140. PCI_BDF(2, 0, 0) INTD PIRQA
  141. PCI_BDF(3, 0, 0) INTA PIRQC
  142. PCI_BDF(3, 0, 0) INTB PIRQD
  143. PCI_BDF(3, 0, 0) INTC PIRQA
  144. PCI_BDF(3, 0, 0) INTD PIRQB
  145. PCI_BDF(4, 0, 0) INTA PIRQD
  146. PCI_BDF(4, 0, 0) INTB PIRQA
  147. PCI_BDF(4, 0, 0) INTC PIRQB
  148. PCI_BDF(4, 0, 0) INTD PIRQC
  149. >;
  150. };
  151. spi: spi {
  152. #address-cells = <1>;
  153. #size-cells = <0>;
  154. compatible = "intel,ich9-spi";
  155. spi-flash@0 {
  156. #address-cells = <1>;
  157. #size-cells = <1>;
  158. reg = <0>;
  159. m25p,fast-read;
  160. compatible = "winbond,w25q64dw",
  161. "jedec,spi-nor";
  162. memory-map = <0xff800000 0x00800000>;
  163. rw-mrc-cache {
  164. label = "rw-mrc-cache";
  165. reg = <0x006e0000 0x00010000>;
  166. };
  167. };
  168. };
  169. gpioa {
  170. compatible = "intel,ich6-gpio";
  171. u-boot,dm-pre-reloc;
  172. reg = <0 0x20>;
  173. bank-name = "A";
  174. use-lvl-write-cache;
  175. };
  176. gpiob {
  177. compatible = "intel,ich6-gpio";
  178. u-boot,dm-pre-reloc;
  179. reg = <0x20 0x20>;
  180. bank-name = "B";
  181. use-lvl-write-cache;
  182. };
  183. gpioc {
  184. compatible = "intel,ich6-gpio";
  185. u-boot,dm-pre-reloc;
  186. reg = <0x40 0x20>;
  187. bank-name = "C";
  188. use-lvl-write-cache;
  189. };
  190. gpiod {
  191. compatible = "intel,ich6-gpio";
  192. u-boot,dm-pre-reloc;
  193. reg = <0x60 0x20>;
  194. bank-name = "D";
  195. use-lvl-write-cache;
  196. };
  197. gpioe {
  198. compatible = "intel,ich6-gpio";
  199. u-boot,dm-pre-reloc;
  200. reg = <0x80 0x20>;
  201. bank-name = "E";
  202. use-lvl-write-cache;
  203. };
  204. gpiof {
  205. compatible = "intel,ich6-gpio";
  206. u-boot,dm-pre-reloc;
  207. reg = <0xA0 0x20>;
  208. bank-name = "F";
  209. use-lvl-write-cache;
  210. };
  211. };
  212. };
  213. fsp {
  214. compatible = "intel,baytrail-fsp";
  215. fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_1MB>;
  216. fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;
  217. fsp,mrc-init-spd-addr1 = <0xa0>;
  218. fsp,mrc-init-spd-addr2 = <0xa2>;
  219. fsp,emmc-boot-mode = <EMMC_BOOT_MODE_AUTO>;
  220. fsp,enable-sdio;
  221. fsp,enable-sdcard;
  222. fsp,enable-hsuart1;
  223. fsp,enable-spi;
  224. fsp,enable-sata;
  225. fsp,sata-mode = <SATA_MODE_AHCI>;
  226. fsp,lpe-mode = <LPE_MODE_PCI>;
  227. fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
  228. fsp,enable-dma0;
  229. fsp,enable-dma1;
  230. fsp,enable-i2c0;
  231. fsp,enable-i2c1;
  232. fsp,enable-i2c2;
  233. fsp,enable-i2c3;
  234. fsp,enable-i2c4;
  235. fsp,enable-i2c5;
  236. fsp,enable-i2c6;
  237. fsp,enable-pwm0;
  238. fsp,enable-pwm1;
  239. fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
  240. fsp,aperture-size = <APERTURE_SIZE_256MB>;
  241. fsp,gtt-size = <GTT_SIZE_2MB>;
  242. fsp,scc-mode = <SCC_MODE_PCI>;
  243. fsp,os-selection = <OS_SELECTION_LINUX>;
  244. fsp,emmc45-ddr50-enabled;
  245. fsp,emmc45-retune-timer-value = <8>;
  246. fsp,enable-igd;
  247. };
  248. microcode {
  249. update@0 {
  250. #include "microcode/m0230671117.dtsi"
  251. };
  252. update@1 {
  253. #include "microcode/m0130673325.dtsi"
  254. };
  255. update@2 {
  256. #include "microcode/m0130679907.dtsi"
  257. };
  258. };
  259. };