tnc.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <init.h>
  8. #include <dm/device-internal.h>
  9. #include <pci.h>
  10. #include <asm/io.h>
  11. #include <asm/irq.h>
  12. #include <asm/post.h>
  13. #include <asm/arch/device.h>
  14. #include <asm/arch/tnc.h>
  15. #include <asm/fsp1/fsp_support.h>
  16. #include <asm/processor.h>
  17. static int __maybe_unused disable_igd(void)
  18. {
  19. struct udevice *igd = NULL;
  20. struct udevice *sdvo = NULL;
  21. int ret;
  22. /*
  23. * In case the IGD and SDVO devices were already in disabled state,
  24. * we should return and not proceed any further.
  25. */
  26. dm_pci_bus_find_bdf(TNC_IGD, &igd);
  27. dm_pci_bus_find_bdf(TNC_SDVO, &sdvo);
  28. if (!igd || !sdvo)
  29. return 0;
  30. /*
  31. * According to Atom E6xx datasheet, setting VGA Disable (bit17)
  32. * of Graphics Controller register (offset 0x50) prevents IGD
  33. * (D2:F0) from reporting itself as a VGA display controller
  34. * class in the PCI configuration space, and should also prevent
  35. * it from responding to VGA legacy memory range and I/O addresses.
  36. *
  37. * However test result shows that with just VGA Disable bit set and
  38. * a PCIe graphics card connected to one of the PCIe controllers on
  39. * the E6xx, accessing the VGA legacy space still causes system hang.
  40. * After a number of attempts, it turns out besides VGA Disable bit,
  41. * the SDVO (D3:F0) device should be disabled to make it work.
  42. *
  43. * To simplify, use the Function Disable register (offset 0xc4)
  44. * to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these
  45. * two devices will be completely disabled (invisible in the PCI
  46. * configuration space) unless a system reset is performed.
  47. */
  48. dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE);
  49. dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE);
  50. /*
  51. * After setting the function disable bit, IGD and SDVO devices will
  52. * disappear in the PCI configuration space. This however creates an
  53. * inconsistent state from a driver model PCI controller point of view,
  54. * as these two PCI devices are still attached to its parent's child
  55. * device list as maintained by the driver model. Some driver model PCI
  56. * APIs like dm_pci_find_class(), are referring to the list to speed up
  57. * the finding process instead of re-enumerating the whole PCI bus, so
  58. * it gets the stale cached data which is wrong.
  59. *
  60. * Note x86 PCI enueration normally happens twice, in pre-relocation
  61. * phase and post-relocation. One option might be to call disable_igd()
  62. * in one of the pre-relocation initialization hooks so that it gets
  63. * disabled in the first round, and when it comes to the second round
  64. * driver model PCI will construct a correct list. Unfortunately this
  65. * does not work as Intel FSP is used on this platform to perform low
  66. * level initialization, and fsp_init_phase_pci() is called only once
  67. * in the post-relocation phase. If we disable IGD and SDVO devices,
  68. * fsp_init_phase_pci() simply hangs and never returns.
  69. *
  70. * So the only option we have is to manually remove these two devices.
  71. */
  72. ret = device_remove(igd, DM_REMOVE_NORMAL);
  73. if (ret)
  74. return ret;
  75. ret = device_unbind(igd);
  76. if (ret)
  77. return ret;
  78. ret = device_remove(sdvo, DM_REMOVE_NORMAL);
  79. if (ret)
  80. return ret;
  81. ret = device_unbind(sdvo);
  82. if (ret)
  83. return ret;
  84. return 0;
  85. }
  86. int arch_cpu_init(void)
  87. {
  88. post_code(POST_CPU_INIT);
  89. return x86_cpu_init_f();
  90. }
  91. static void tnc_irq_init(void)
  92. {
  93. struct tnc_rcba *rcba;
  94. u32 base;
  95. pci_read_config32(TNC_LPC, LPC_RCBA, &base);
  96. base &= ~MEM_BAR_EN;
  97. rcba = (struct tnc_rcba *)base;
  98. /* Make sure all internal PCI devices are using INTA */
  99. writel(INTA, &rcba->d02ip);
  100. writel(INTA, &rcba->d03ip);
  101. writel(INTA, &rcba->d27ip);
  102. writel(INTA, &rcba->d31ip);
  103. writel(INTA, &rcba->d23ip);
  104. writel(INTA, &rcba->d24ip);
  105. writel(INTA, &rcba->d25ip);
  106. writel(INTA, &rcba->d26ip);
  107. /*
  108. * Route TunnelCreek PCI device interrupt pin to PIRQ
  109. *
  110. * Since PCIe downstream ports received INTx are routed to PIRQ
  111. * A/B/C/D directly and not configurable, we have to route PCIe
  112. * root ports' INTx to PIRQ A/B/C/D as well. For other devices
  113. * on TunneCreek, route them to PIRQ E/F/G/H.
  114. */
  115. writew(PIRQE, &rcba->d02ir);
  116. writew(PIRQF, &rcba->d03ir);
  117. writew(PIRQG, &rcba->d27ir);
  118. writew(PIRQH, &rcba->d31ir);
  119. writew(PIRQA, &rcba->d23ir);
  120. writew(PIRQB, &rcba->d24ir);
  121. writew(PIRQC, &rcba->d25ir);
  122. writew(PIRQD, &rcba->d26ir);
  123. }
  124. int arch_early_init_r(void)
  125. {
  126. int ret = 0;
  127. #ifdef CONFIG_DISABLE_IGD
  128. ret = disable_igd();
  129. #endif
  130. tnc_irq_init();
  131. return ret;
  132. }