sdhci.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2011, Marvell Semiconductor Inc.
  4. * Lei Wen <leiwen@marvell.com>
  5. *
  6. * Back ported to the 8xx platform (from the 8260 platform) by
  7. * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  8. */
  9. #ifndef __SDHCI_HW_H
  10. #define __SDHCI_HW_H
  11. #include <asm/io.h>
  12. #include <mmc.h>
  13. #include <asm/gpio.h>
  14. /*
  15. * Controller registers
  16. */
  17. #define SDHCI_DMA_ADDRESS 0x00
  18. #define SDHCI_BLOCK_SIZE 0x04
  19. #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
  20. #define SDHCI_BLOCK_COUNT 0x06
  21. #define SDHCI_ARGUMENT 0x08
  22. #define SDHCI_TRANSFER_MODE 0x0C
  23. #define SDHCI_TRNS_DMA BIT(0)
  24. #define SDHCI_TRNS_BLK_CNT_EN BIT(1)
  25. #define SDHCI_TRNS_ACMD12 BIT(2)
  26. #define SDHCI_TRNS_READ BIT(4)
  27. #define SDHCI_TRNS_MULTI BIT(5)
  28. #define SDHCI_COMMAND 0x0E
  29. #define SDHCI_CMD_RESP_MASK 0x03
  30. #define SDHCI_CMD_CRC 0x08
  31. #define SDHCI_CMD_INDEX 0x10
  32. #define SDHCI_CMD_DATA 0x20
  33. #define SDHCI_CMD_ABORTCMD 0xC0
  34. #define SDHCI_CMD_RESP_NONE 0x00
  35. #define SDHCI_CMD_RESP_LONG 0x01
  36. #define SDHCI_CMD_RESP_SHORT 0x02
  37. #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
  38. #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
  39. #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
  40. #define SDHCI_RESPONSE 0x10
  41. #define SDHCI_BUFFER 0x20
  42. #define SDHCI_PRESENT_STATE 0x24
  43. #define SDHCI_CMD_INHIBIT BIT(0)
  44. #define SDHCI_DATA_INHIBIT BIT(1)
  45. #define SDHCI_DOING_WRITE BIT(8)
  46. #define SDHCI_DOING_READ BIT(9)
  47. #define SDHCI_SPACE_AVAILABLE BIT(10)
  48. #define SDHCI_DATA_AVAILABLE BIT(11)
  49. #define SDHCI_CARD_PRESENT BIT(16)
  50. #define SDHCI_CARD_STATE_STABLE BIT(17)
  51. #define SDHCI_CARD_DETECT_PIN_LEVEL BIT(18)
  52. #define SDHCI_WRITE_PROTECT BIT(19)
  53. #define SDHCI_HOST_CONTROL 0x28
  54. #define SDHCI_CTRL_LED BIT(0)
  55. #define SDHCI_CTRL_4BITBUS BIT(1)
  56. #define SDHCI_CTRL_HISPD BIT(2)
  57. #define SDHCI_CTRL_DMA_MASK 0x18
  58. #define SDHCI_CTRL_SDMA 0x00
  59. #define SDHCI_CTRL_ADMA1 0x08
  60. #define SDHCI_CTRL_ADMA32 0x10
  61. #define SDHCI_CTRL_ADMA64 0x18
  62. #define SDHCI_CTRL_8BITBUS BIT(5)
  63. #define SDHCI_CTRL_CD_TEST_INS BIT(6)
  64. #define SDHCI_CTRL_CD_TEST BIT(7)
  65. #define SDHCI_POWER_CONTROL 0x29
  66. #define SDHCI_POWER_ON 0x01
  67. #define SDHCI_POWER_180 0x0A
  68. #define SDHCI_POWER_300 0x0C
  69. #define SDHCI_POWER_330 0x0E
  70. #define SDHCI_BLOCK_GAP_CONTROL 0x2A
  71. #define SDHCI_WAKE_UP_CONTROL 0x2B
  72. #define SDHCI_WAKE_ON_INT BIT(0)
  73. #define SDHCI_WAKE_ON_INSERT BIT(1)
  74. #define SDHCI_WAKE_ON_REMOVE BIT(2)
  75. #define SDHCI_CLOCK_CONTROL 0x2C
  76. #define SDHCI_DIVIDER_SHIFT 8
  77. #define SDHCI_DIVIDER_HI_SHIFT 6
  78. #define SDHCI_DIV_MASK 0xFF
  79. #define SDHCI_DIV_MASK_LEN 8
  80. #define SDHCI_DIV_HI_MASK 0x300
  81. #define SDHCI_PROG_CLOCK_MODE BIT(5)
  82. #define SDHCI_CLOCK_CARD_EN BIT(2)
  83. #define SDHCI_CLOCK_INT_STABLE BIT(1)
  84. #define SDHCI_CLOCK_INT_EN BIT(0)
  85. #define SDHCI_TIMEOUT_CONTROL 0x2E
  86. #define SDHCI_SOFTWARE_RESET 0x2F
  87. #define SDHCI_RESET_ALL 0x01
  88. #define SDHCI_RESET_CMD 0x02
  89. #define SDHCI_RESET_DATA 0x04
  90. #define SDHCI_INT_STATUS 0x30
  91. #define SDHCI_INT_ENABLE 0x34
  92. #define SDHCI_SIGNAL_ENABLE 0x38
  93. #define SDHCI_INT_RESPONSE BIT(0)
  94. #define SDHCI_INT_DATA_END BIT(1)
  95. #define SDHCI_INT_DMA_END BIT(3)
  96. #define SDHCI_INT_SPACE_AVAIL BIT(4)
  97. #define SDHCI_INT_DATA_AVAIL BIT(5)
  98. #define SDHCI_INT_CARD_INSERT BIT(6)
  99. #define SDHCI_INT_CARD_REMOVE BIT(7)
  100. #define SDHCI_INT_CARD_INT BIT(8)
  101. #define SDHCI_INT_ERROR BIT(15)
  102. #define SDHCI_INT_TIMEOUT BIT(16)
  103. #define SDHCI_INT_CRC BIT(17)
  104. #define SDHCI_INT_END_BIT BIT(18)
  105. #define SDHCI_INT_INDEX BIT(19)
  106. #define SDHCI_INT_DATA_TIMEOUT BIT(20)
  107. #define SDHCI_INT_DATA_CRC BIT(21)
  108. #define SDHCI_INT_DATA_END_BIT BIT(22)
  109. #define SDHCI_INT_BUS_POWER BIT(23)
  110. #define SDHCI_INT_ACMD12ERR BIT(24)
  111. #define SDHCI_INT_ADMA_ERROR BIT(25)
  112. #define SDHCI_INT_NORMAL_MASK 0x00007FFF
  113. #define SDHCI_INT_ERROR_MASK 0xFFFF8000
  114. #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
  115. SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
  116. #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
  117. SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
  118. SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
  119. SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
  120. #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
  121. #define SDHCI_ACMD12_ERR 0x3C
  122. /* 3E-3F reserved */
  123. #define SDHCI_CAPABILITIES 0x40
  124. #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
  125. #define SDHCI_TIMEOUT_CLK_SHIFT 0
  126. #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
  127. #define SDHCI_CLOCK_BASE_MASK 0x00003F00
  128. #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
  129. #define SDHCI_CLOCK_BASE_SHIFT 8
  130. #define SDHCI_MAX_BLOCK_MASK 0x00030000
  131. #define SDHCI_MAX_BLOCK_SHIFT 16
  132. #define SDHCI_CAN_DO_8BIT BIT(18)
  133. #define SDHCI_CAN_DO_ADMA2 BIT(19)
  134. #define SDHCI_CAN_DO_ADMA1 BIT(20)
  135. #define SDHCI_CAN_DO_HISPD BIT(21)
  136. #define SDHCI_CAN_DO_SDMA BIT(22)
  137. #define SDHCI_CAN_VDD_330 BIT(24)
  138. #define SDHCI_CAN_VDD_300 BIT(25)
  139. #define SDHCI_CAN_VDD_180 BIT(26)
  140. #define SDHCI_CAN_64BIT BIT(28)
  141. #define SDHCI_CAPABILITIES_1 0x44
  142. #define SDHCI_SUPPORT_SDR50 0x00000001
  143. #define SDHCI_SUPPORT_SDR104 0x00000002
  144. #define SDHCI_SUPPORT_DDR50 0x00000004
  145. #define SDHCI_USE_SDR50_TUNING 0x00002000
  146. #define SDHCI_CLOCK_MUL_MASK 0x00FF0000
  147. #define SDHCI_CLOCK_MUL_SHIFT 16
  148. #define SDHCI_MAX_CURRENT 0x48
  149. /* 4C-4F reserved for more max current */
  150. #define SDHCI_SET_ACMD12_ERROR 0x50
  151. #define SDHCI_SET_INT_ERROR 0x52
  152. #define SDHCI_ADMA_ERROR 0x54
  153. /* 55-57 reserved */
  154. #define SDHCI_ADMA_ADDRESS 0x58
  155. /* 60-FB reserved */
  156. #define SDHCI_SLOT_INT_STATUS 0xFC
  157. #define SDHCI_HOST_VERSION 0xFE
  158. #define SDHCI_VENDOR_VER_MASK 0xFF00
  159. #define SDHCI_VENDOR_VER_SHIFT 8
  160. #define SDHCI_SPEC_VER_MASK 0x00FF
  161. #define SDHCI_SPEC_VER_SHIFT 0
  162. #define SDHCI_SPEC_100 0
  163. #define SDHCI_SPEC_200 1
  164. #define SDHCI_SPEC_300 2
  165. #define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
  166. /*
  167. * End of controller registers.
  168. */
  169. #define SDHCI_MAX_DIV_SPEC_200 256
  170. #define SDHCI_MAX_DIV_SPEC_300 2046
  171. /*
  172. * quirks
  173. */
  174. #define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0)
  175. #define SDHCI_QUIRK_REG32_RW (1 << 1)
  176. #define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
  177. #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
  178. #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
  179. /*
  180. * SDHCI_QUIRK_BROKEN_HISPD_MODE
  181. * the hardware cannot operate correctly in high-speed mode,
  182. * this quirk forces the sdhci host-controller to non high-speed mode
  183. */
  184. #define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5)
  185. #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
  186. #define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
  187. #define SDHCI_QUIRK_NO_1_8_V (1 << 9)
  188. /* to make gcc happy */
  189. struct sdhci_host;
  190. /*
  191. * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
  192. */
  193. #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
  194. #define SDHCI_DEFAULT_BOUNDARY_ARG (7)
  195. struct sdhci_ops {
  196. #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
  197. u32 (*read_l)(struct sdhci_host *host, int reg);
  198. u16 (*read_w)(struct sdhci_host *host, int reg);
  199. u8 (*read_b)(struct sdhci_host *host, int reg);
  200. void (*write_l)(struct sdhci_host *host, u32 val, int reg);
  201. void (*write_w)(struct sdhci_host *host, u16 val, int reg);
  202. void (*write_b)(struct sdhci_host *host, u8 val, int reg);
  203. #endif
  204. int (*get_cd)(struct sdhci_host *host);
  205. void (*set_control_reg)(struct sdhci_host *host);
  206. void (*set_ios_post)(struct sdhci_host *host);
  207. void (*set_clock)(struct sdhci_host *host, u32 div);
  208. int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
  209. void (*set_delay)(struct sdhci_host *host);
  210. };
  211. struct sdhci_host {
  212. const char *name;
  213. void *ioaddr;
  214. unsigned int quirks;
  215. unsigned int host_caps;
  216. unsigned int version;
  217. unsigned int max_clk; /* Maximum Base Clock frequency */
  218. unsigned int clk_mul; /* Clock Multiplier value */
  219. unsigned int clock;
  220. struct mmc *mmc;
  221. const struct sdhci_ops *ops;
  222. int index;
  223. int bus_width;
  224. struct gpio_desc pwr_gpio; /* Power GPIO */
  225. struct gpio_desc cd_gpio; /* Card Detect GPIO */
  226. uint voltages;
  227. struct mmc_config cfg;
  228. };
  229. #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
  230. static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
  231. {
  232. if (unlikely(host->ops->write_l))
  233. host->ops->write_l(host, val, reg);
  234. else
  235. writel(val, host->ioaddr + reg);
  236. }
  237. static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
  238. {
  239. if (unlikely(host->ops->write_w))
  240. host->ops->write_w(host, val, reg);
  241. else
  242. writew(val, host->ioaddr + reg);
  243. }
  244. static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
  245. {
  246. if (unlikely(host->ops->write_b))
  247. host->ops->write_b(host, val, reg);
  248. else
  249. writeb(val, host->ioaddr + reg);
  250. }
  251. static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
  252. {
  253. if (unlikely(host->ops->read_l))
  254. return host->ops->read_l(host, reg);
  255. else
  256. return readl(host->ioaddr + reg);
  257. }
  258. static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
  259. {
  260. if (unlikely(host->ops->read_w))
  261. return host->ops->read_w(host, reg);
  262. else
  263. return readw(host->ioaddr + reg);
  264. }
  265. static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
  266. {
  267. if (unlikely(host->ops->read_b))
  268. return host->ops->read_b(host, reg);
  269. else
  270. return readb(host->ioaddr + reg);
  271. }
  272. #else
  273. static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
  274. {
  275. writel(val, host->ioaddr + reg);
  276. }
  277. static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
  278. {
  279. writew(val, host->ioaddr + reg);
  280. }
  281. static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
  282. {
  283. writeb(val, host->ioaddr + reg);
  284. }
  285. static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
  286. {
  287. return readl(host->ioaddr + reg);
  288. }
  289. static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
  290. {
  291. return readw(host->ioaddr + reg);
  292. }
  293. static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
  294. {
  295. return readb(host->ioaddr + reg);
  296. }
  297. #endif
  298. #ifdef CONFIG_BLK
  299. /**
  300. * sdhci_setup_cfg() - Set up the configuration for DWMMC
  301. *
  302. * This is used to set up an SDHCI device when you are using CONFIG_BLK.
  303. *
  304. * This should be called from your MMC driver's probe() method once you have
  305. * the information required.
  306. *
  307. * Generally your driver will have a platform data structure which holds both
  308. * the configuration (struct mmc_config) and the MMC device info (struct mmc).
  309. * For example:
  310. *
  311. * struct msm_sdhc_plat {
  312. * struct mmc_config cfg;
  313. * struct mmc mmc;
  314. * };
  315. *
  316. * ...
  317. *
  318. * Inside U_BOOT_DRIVER():
  319. * .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat),
  320. *
  321. * To access platform data:
  322. * struct msm_sdhc_plat *plat = dev_get_platdata(dev);
  323. *
  324. * See msm_sdhci.c for an example.
  325. *
  326. * @cfg: Configuration structure to fill in (generally &plat->mmc)
  327. * @host: SDHCI host structure
  328. * @f_max: Maximum supported clock frequency in HZ (0 for default)
  329. * @f_min: Minimum supported clock frequency in HZ (0 for default)
  330. */
  331. int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
  332. u32 f_max, u32 f_min);
  333. /**
  334. * sdhci_bind() - Set up a new MMC block device
  335. *
  336. * This is used to set up an SDHCI block device when you are using CONFIG_BLK.
  337. * It should be called from your driver's bind() method.
  338. *
  339. * See msm_sdhci.c for an example.
  340. *
  341. * @dev: Device to set up
  342. * @mmc: Pointer to mmc structure (normally &plat->mmc)
  343. * @cfg: Empty configuration structure (generally &plat->cfg). This is
  344. * normally all zeroes at this point. The only purpose of passing
  345. * this in is to set mmc->cfg to it.
  346. * @return 0 if OK, -ve if the block device could not be created
  347. */
  348. int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
  349. #else
  350. /**
  351. * add_sdhci() - Add a new SDHCI interface
  352. *
  353. * This is used when you are not using CONFIG_BLK. Convert your driver over!
  354. *
  355. * @host: SDHCI host structure
  356. * @f_max: Maximum supported clock frequency in HZ (0 for default)
  357. * @f_min: Minimum supported clock frequency in HZ (0 for default)
  358. * @return 0 if OK, -ve on error
  359. */
  360. int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
  361. #endif /* !CONFIG_BLK */
  362. #ifdef CONFIG_DM_MMC
  363. /* Export the operations to drivers */
  364. int sdhci_probe(struct udevice *dev);
  365. extern const struct dm_mmc_ops sdhci_ops;
  366. #else
  367. #endif
  368. #endif /* __SDHCI_HW_H */