zynq_sdhci.c 7.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 - 2015 Xilinx, Inc.
  4. *
  5. * Xilinx Zynq SD Host Controller Interface
  6. */
  7. #include <clk.h>
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include "mmc_private.h"
  12. #include <linux/libfdt.h>
  13. #include <malloc.h>
  14. #include <sdhci.h>
  15. #include <zynqmp_tap_delay.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. struct arasan_sdhci_plat {
  18. struct mmc_config cfg;
  19. struct mmc mmc;
  20. unsigned int f_max;
  21. };
  22. struct arasan_sdhci_priv {
  23. struct sdhci_host *host;
  24. u8 deviceid;
  25. u8 bank;
  26. u8 no_1p8;
  27. bool pwrseq;
  28. };
  29. #if defined(CONFIG_ARCH_ZYNQMP)
  30. static const u8 mode2timing[] = {
  31. [UHS_SDR12] = UHS_SDR12_BUS_SPEED,
  32. [UHS_SDR25] = UHS_SDR25_BUS_SPEED,
  33. [UHS_SDR50] = UHS_SDR50_BUS_SPEED,
  34. [UHS_SDR104] = UHS_SDR104_BUS_SPEED,
  35. [UHS_DDR50] = UHS_DDR50_BUS_SPEED,
  36. };
  37. #define SDHCI_HOST_CTRL2 0x3E
  38. #define SDHCI_CTRL2_MODE_MASK 0x7
  39. #define SDHCI_18V_SIGNAL 0x8
  40. #define SDHCI_CTRL_EXEC_TUNING 0x0040
  41. #define SDHCI_CTRL_TUNED_CLK 0x80
  42. #define SDHCI_TUNING_LOOP_COUNT 40
  43. static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
  44. {
  45. u16 clk;
  46. unsigned long timeout;
  47. clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  48. clk &= ~(SDHCI_CLOCK_CARD_EN);
  49. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  50. /* Issue DLL Reset */
  51. zynqmp_dll_reset(deviceid);
  52. /* Wait max 20 ms */
  53. timeout = 100;
  54. while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  55. & SDHCI_CLOCK_INT_STABLE)) {
  56. if (timeout == 0) {
  57. dev_err(mmc_dev(host->mmc),
  58. ": Internal clock never stabilised.\n");
  59. return;
  60. }
  61. timeout--;
  62. udelay(1000);
  63. }
  64. clk |= SDHCI_CLOCK_CARD_EN;
  65. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  66. }
  67. static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
  68. {
  69. struct mmc_cmd cmd;
  70. struct mmc_data data;
  71. u32 ctrl;
  72. struct sdhci_host *host;
  73. struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
  74. u8 tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
  75. u8 deviceid;
  76. debug("%s\n", __func__);
  77. host = priv->host;
  78. deviceid = priv->deviceid;
  79. ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
  80. ctrl |= SDHCI_CTRL_EXEC_TUNING;
  81. sdhci_writew(host, ctrl, SDHCI_HOST_CTRL2);
  82. mdelay(1);
  83. arasan_zynqmp_dll_reset(host, deviceid);
  84. sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
  85. sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
  86. do {
  87. cmd.cmdidx = opcode;
  88. cmd.resp_type = MMC_RSP_R1;
  89. cmd.cmdarg = 0;
  90. data.blocksize = 64;
  91. data.blocks = 1;
  92. data.flags = MMC_DATA_READ;
  93. if (tuning_loop_counter-- == 0)
  94. break;
  95. if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
  96. mmc->bus_width == 8)
  97. data.blocksize = 128;
  98. sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
  99. data.blocksize),
  100. SDHCI_BLOCK_SIZE);
  101. sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
  102. sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
  103. mmc_send_cmd(mmc, &cmd, NULL);
  104. ctrl = sdhci_readw(host, SDHCI_HOST_CTRL2);
  105. if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
  106. udelay(1);
  107. } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
  108. if (tuning_loop_counter < 0) {
  109. ctrl &= ~SDHCI_CTRL_TUNED_CLK;
  110. sdhci_writel(host, ctrl, SDHCI_HOST_CTRL2);
  111. }
  112. if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
  113. printf("%s:Tuning failed\n", __func__);
  114. return -1;
  115. }
  116. udelay(1);
  117. arasan_zynqmp_dll_reset(host, deviceid);
  118. /* Enable only interrupts served by the SD controller */
  119. sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
  120. SDHCI_INT_ENABLE);
  121. /* Mask all sdhci interrupt sources */
  122. sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
  123. return 0;
  124. }
  125. static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
  126. {
  127. struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
  128. struct mmc *mmc = (struct mmc *)host->mmc;
  129. u8 uhsmode;
  130. if (!IS_SD(mmc))
  131. return;
  132. uhsmode = mode2timing[mmc->selected_mode];
  133. if (uhsmode >= UHS_SDR25_BUS_SPEED)
  134. arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
  135. priv->bank);
  136. }
  137. static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
  138. {
  139. struct mmc *mmc = (struct mmc *)host->mmc;
  140. u32 reg;
  141. if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
  142. reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
  143. reg |= SDHCI_18V_SIGNAL;
  144. sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
  145. }
  146. if (mmc->selected_mode > SD_HS &&
  147. mmc->selected_mode <= UHS_DDR50) {
  148. reg = sdhci_readw(host, SDHCI_HOST_CTRL2);
  149. reg &= ~SDHCI_CTRL2_MODE_MASK;
  150. switch (mmc->selected_mode) {
  151. case UHS_SDR12:
  152. reg |= UHS_SDR12_BUS_SPEED;
  153. break;
  154. case UHS_SDR25:
  155. reg |= UHS_SDR25_BUS_SPEED;
  156. break;
  157. case UHS_SDR50:
  158. reg |= UHS_SDR50_BUS_SPEED;
  159. break;
  160. case UHS_SDR104:
  161. reg |= UHS_SDR104_BUS_SPEED;
  162. break;
  163. case UHS_DDR50:
  164. reg |= UHS_DDR50_BUS_SPEED;
  165. break;
  166. default:
  167. break;
  168. }
  169. sdhci_writew(host, reg, SDHCI_HOST_CTRL2);
  170. }
  171. }
  172. #endif
  173. #if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
  174. const struct sdhci_ops arasan_ops = {
  175. .platform_execute_tuning = &arasan_sdhci_execute_tuning,
  176. .set_delay = &arasan_sdhci_set_tapdelay,
  177. .set_control_reg = &arasan_sdhci_set_control_reg,
  178. };
  179. #endif
  180. static int arasan_sdhci_probe(struct udevice *dev)
  181. {
  182. struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
  183. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  184. struct arasan_sdhci_priv *priv = dev_get_priv(dev);
  185. struct sdhci_host *host;
  186. struct clk clk;
  187. unsigned long clock;
  188. int ret;
  189. host = priv->host;
  190. ret = clk_get_by_index(dev, 0, &clk);
  191. if (ret < 0) {
  192. dev_err(dev, "failed to get clock\n");
  193. return ret;
  194. }
  195. clock = clk_get_rate(&clk);
  196. if (IS_ERR_VALUE(clock)) {
  197. dev_err(dev, "failed to get rate\n");
  198. return clock;
  199. }
  200. debug("%s: CLK %ld\n", __func__, clock);
  201. ret = clk_enable(&clk);
  202. if (ret && ret != -ENOSYS) {
  203. dev_err(dev, "failed to enable clock\n");
  204. return ret;
  205. }
  206. host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
  207. SDHCI_QUIRK_BROKEN_R1B;
  208. #ifdef CONFIG_ZYNQ_HISPD_BROKEN
  209. host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
  210. #endif
  211. if (priv->no_1p8)
  212. host->quirks |= SDHCI_QUIRK_NO_1_8_V;
  213. host->max_clk = clock;
  214. ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
  215. CONFIG_ZYNQ_SDHCI_MIN_FREQ);
  216. host->mmc = &plat->mmc;
  217. if (ret)
  218. return ret;
  219. host->mmc->priv = host;
  220. host->mmc->dev = dev;
  221. upriv->mmc = host->mmc;
  222. return sdhci_probe(dev);
  223. }
  224. static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
  225. {
  226. struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
  227. struct arasan_sdhci_priv *priv = dev_get_priv(dev);
  228. priv->host = calloc(1, sizeof(struct sdhci_host));
  229. if (!priv->host)
  230. return -1;
  231. priv->host->name = dev->name;
  232. priv->host->ioaddr = (void *)devfdt_get_addr(dev);
  233. priv->deviceid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  234. "xlnx,device_id", -1);
  235. priv->bank = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  236. "xlnx,mio_bank", -1);
  237. if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev),
  238. "no-1-8-v", NULL))
  239. priv->no_1p8 = 1;
  240. else
  241. priv->no_1p8 = 0;
  242. #if defined(CONFIG_DM_MMC) && defined(CONFIG_ARCH_ZYNQMP)
  243. priv->host->ops = &arasan_ops;
  244. #endif
  245. plat->f_max = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  246. "max-frequency", CONFIG_ZYNQ_SDHCI_MAX_FREQ);
  247. return 0;
  248. }
  249. static int arasan_sdhci_bind(struct udevice *dev)
  250. {
  251. struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
  252. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  253. }
  254. static const struct udevice_id arasan_sdhci_ids[] = {
  255. { .compatible = "arasan,sdhci-8.9a" },
  256. { }
  257. };
  258. U_BOOT_DRIVER(arasan_sdhci_drv) = {
  259. .name = "arasan_sdhci",
  260. .id = UCLASS_MMC,
  261. .of_match = arasan_sdhci_ids,
  262. .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
  263. .ops = &sdhci_ops,
  264. .bind = arasan_sdhci_bind,
  265. .probe = arasan_sdhci_probe,
  266. .priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
  267. .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
  268. };